1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11CXX_GUARD_START
 12
 13#include "core/log.h"
 14#include "core/timing.h"
 15#include "gb/interface.h"
 16#include "lr35902/lr35902.h"
 17
 18#include <time.h>
 19
 20mLOG_DECLARE_CATEGORY(GB_MBC);
 21mLOG_DECLARE_CATEGORY(GB_MEM);
 22
 23struct GB;
 24
 25enum {
 26	GB_BASE_CART_BANK0 = 0x0000,
 27	GB_BASE_CART_BANK1 = 0x4000,
 28	GB_BASE_VRAM = 0x8000,
 29	GB_BASE_EXTERNAL_RAM = 0xA000,
 30	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 31	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 32	GB_BASE_OAM = 0xFE00,
 33	GB_BASE_UNUSABLE = 0xFEA0,
 34	GB_BASE_IO = 0xFF00,
 35	GB_BASE_HRAM = 0xFF80,
 36	GB_BASE_IE = 0xFFFF
 37};
 38
 39enum {
 40	GB_REGION_CART_BANK0 = 0x0,
 41	GB_REGION_CART_BANK1 = 0x4,
 42	GB_REGION_VRAM = 0x8,
 43	GB_REGION_EXTERNAL_RAM = 0xA,
 44	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 45	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 46	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 47	GB_REGION_OTHER = 0xF,
 48};
 49
 50enum {
 51	GB_SIZE_CART_BANK0 = 0x4000,
 52	GB_SIZE_CART_MAX = 0x800000,
 53	GB_SIZE_VRAM = 0x4000,
 54	GB_SIZE_VRAM_BANK0 = 0x2000,
 55	GB_SIZE_EXTERNAL_RAM = 0x2000,
 56	GB_SIZE_WORKING_RAM = 0x8000,
 57	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 58	GB_SIZE_OAM = 0xA0,
 59	GB_SIZE_IO = 0x80,
 60	GB_SIZE_HRAM = 0x7F,
 61};
 62
 63enum {
 64	GB_SRAM_DIRT_NEW = 1,
 65	GB_SRAM_DIRT_SEEN = 2
 66};
 67
 68struct GBMemory;
 69typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
 70
 71DECL_BITFIELD(GBMBC7Field, uint8_t);
 72DECL_BIT(GBMBC7Field, SK, 6);
 73DECL_BIT(GBMBC7Field, CS, 7);
 74DECL_BIT(GBMBC7Field, IO, 1);
 75
 76enum GBMBC7MachineState {
 77	GBMBC7_STATE_NULL = -1,
 78	GBMBC7_STATE_IDLE = 0,
 79	GBMBC7_STATE_READ_COMMAND = 1,
 80	GBMBC7_STATE_READ_ADDRESS = 2,
 81	GBMBC7_STATE_COMMAND_0 = 3,
 82	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 83	GBMBC7_STATE_COMMAND_SR_READ = 5,
 84	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 85	GBMBC7_STATE_READ = 7,
 86	GBMBC7_STATE_WRITE = 8,
 87};
 88
 89struct GBMBC1State {
 90	int mode;
 91};
 92
 93struct GBMBC7State {
 94	enum GBMBC7MachineState state;
 95	uint32_t sr;
 96	uint8_t address;
 97	bool writable;
 98	int srBits;
 99	int command;
100	GBMBC7Field field;
101};
102
103union GBMBCState {
104	struct GBMBC1State mbc1;
105	struct GBMBC7State mbc7;
106};
107
108struct mRotationSource;
109struct GBMemory {
110	uint8_t* rom;
111	uint8_t* romBase;
112	uint8_t* romBank;
113	enum GBMemoryBankControllerType mbcType;
114	GBMemoryBankController mbc;
115	union GBMBCState mbcState;
116	int currentBank;
117
118	uint8_t* wram;
119	uint8_t* wramBank;
120	int wramCurrentBank;
121
122	bool sramAccess;
123	uint8_t* sram;
124	uint8_t* sramBank;
125	int sramCurrentBank;
126
127	uint8_t io[GB_SIZE_IO];
128	bool ime;
129	uint8_t ie;
130
131	uint8_t hram[GB_SIZE_HRAM];
132
133	uint16_t dmaSource;
134	uint16_t dmaDest;
135	int dmaRemaining;
136
137	uint16_t hdmaSource;
138	uint16_t hdmaDest;
139	int hdmaRemaining;
140	bool isHdma;
141
142	struct mTimingEvent dmaEvent;
143	struct mTimingEvent hdmaEvent;
144
145	size_t romSize;
146
147	bool rtcAccess;
148	int activeRtcReg;
149	bool rtcLatched;
150	uint8_t rtcRegs[5];
151	time_t rtcLastLatch;
152	struct mRTCSource* rtc;
153	struct mRotationSource* rotation;
154	struct mRumble* rumble;
155};
156
157void GBMemoryInit(struct GB* gb);
158void GBMemoryDeinit(struct GB* gb);
159
160void GBMemoryReset(struct GB* gb);
161void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
162
163uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
164void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
165
166uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
167
168void GBMemoryDMA(struct GB* gb, uint16_t base);
169void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
170
171uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
172void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
173
174void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
175
176struct GBSerializedState;
177void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
178void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
179
180CXX_GUARD_END
181
182#endif