src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define THUMB_SUBTRACTION(D, M, N) \
42 int n = N; \
43 int m = M; \
44 D = M - N; \
45 THUMB_SUBTRACTION_S(m, n, D)
46
47#define APPLY(F, ...) F(__VA_ARGS__)
48
49#define COUNT_1(EMITTER, PREFIX, ...) \
50 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
51 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
52
53#define COUNT_2(EMITTER, PREFIX, ...) \
54 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
55 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
56 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
57
58#define COUNT_3(EMITTER, PREFIX, ...) \
59 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
60 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
61 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
62 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
63 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
64
65#define COUNT_4(EMITTER, PREFIX, ...) \
66 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
67 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
68 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
69 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
70 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
71 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
72 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
73 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
74 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
75
76#define COUNT_5(EMITTER, PREFIX, ...) \
77 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
78 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
79 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
80 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
81 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
82 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
83 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
84 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
85 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
86 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
87 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
88 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
89 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
90 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
91 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
92 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
93 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
94
95#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
96 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
97 BODY; \
98 cpu->cycles += 1 + cpu->memory->activePrefetchCycles16; \
99 }
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
102 DEFINE_INSTRUCTION_THUMB(NAME, \
103 int immediate = IMMEDIATE; \
104 int rd = opcode & 0x0007; \
105 int rm = (opcode >> 3) & 0x0007; \
106 BODY;)
107
108#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
109 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
110
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
112 if (!immediate) { \
113 cpu->gprs[rd] = cpu->gprs[rm]; \
114 } else { \
115 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
116 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
117 } \
118 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
119
120DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
121 if (!immediate) { \
122 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
123 cpu->gprs[rd] = 0; \
124 } else { \
125 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
126 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
127 } \
128 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
129
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
131
132DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
133DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate))
134DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2))
135DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
136DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd]))
137DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
138
139#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
140 DEFINE_INSTRUCTION_THUMB(NAME, \
141 int rm = RM; \
142 int rd = opcode & 0x0007; \
143 int rn = (opcode >> 3) & 0x0007; \
144 BODY;)
145
146#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
147 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
148
149DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
150DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
151
152#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
153 DEFINE_INSTRUCTION_THUMB(NAME, \
154 int immediate = IMMEDIATE; \
155 int rd = opcode & 0x0007; \
156 int rn = (opcode >> 3) & 0x0007; \
157 BODY;)
158
159#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
160 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
161
162DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
163DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
164
165#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
166 DEFINE_INSTRUCTION_THUMB(NAME, \
167 int rd = RD; \
168 int immediate = opcode & 0x00FF; \
169 BODY;)
170
171#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
172 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
173
174DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
175DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
176DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
177DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
178
179#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
180 DEFINE_INSTRUCTION_THUMB(NAME, \
181 int rd = opcode & 0x0007; \
182 int rn = (opcode >> 3) & 0x0007; \
183 BODY;)
184
185DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
186DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
187DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
188DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, \
189 int rs = cpu->gprs[rn] & 0xFF; \
190 if (rs) { \
191 if (rs < 32) { \
192 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
193 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs; \
194 } else { \
195 if (rs > 32) { \
196 cpu->cpsr.c = 0; \
197 } else { \
198 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
199 } \
200 cpu->gprs[rd] = 0; \
201 } \
202 } \
203 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
204
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, \
206 int rs = cpu->gprs[rn] & 0xFF; \
207 if (rs) { \
208 if (rs < 32) { \
209 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
210 cpu->gprs[rd] >>= rs; \
211 } else { \
212 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
213 if (cpu->cpsr.c) { \
214 cpu->gprs[rd] = 0xFFFFFFFF; \
215 } else { \
216 cpu->gprs[rd] = 0; \
217 } \
218 } \
219 } \
220 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
221
222DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
224DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
225DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
226DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
227DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
231DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
232DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
233
234#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
235 DEFINE_INSTRUCTION_THUMB(NAME, \
236 int rd = opcode & 0x0007 | H1; \
237 int rm = (opcode >> 3) & 0x0007 | H2; \
238 BODY;)
239
240#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
241 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
242 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
243 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
244 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
245
246DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, cpu->gprs[rd] += cpu->gprs[rm])
247DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
248DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
249
250#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
251 DEFINE_INSTRUCTION_THUMB(NAME, \
252 int rd = RD; \
253 int immediate = (opcode & 0x00FF) << 2; \
254 BODY;)
255
256#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
257 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
258
259DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
260DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
261DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
262
263DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
264DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
265
266#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
267 DEFINE_INSTRUCTION_THUMB(NAME, \
268 int rm = RM; \
269 int rd = opcode & 0x0007; \
270 int rn = (opcode >> 3) & 0x0007; \
271 BODY;)
272
273#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
274 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
275
276DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
277DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
278DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
279DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
280DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
281DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
282DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
283DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
284
285#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
286 DEFINE_INSTRUCTION_THUMB(NAME, \
287 int rn = (opcode >> 8) & 0x000F; \
288 int rs = RS; \
289 int32_t address = ADDRESS; \
290 int m; \
291 int i; \
292 PRE_BODY; \
293 for LOOP { \
294 if (rs & m) { \
295 BODY; \
296 address OP 4; \
297 } \
298 } \
299 POST_BODY; \
300 WRITEBACK;)
301
302#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
303 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
304
305DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
306 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
307 if (!((1 << rn) & rs)) { \
308 cpu->gprs[rn] = address; \
309 })
310
311DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
312 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
313 cpu->gprs[rn] = address)
314
315#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
316 DEFINE_INSTRUCTION_THUMB(B ## COND, \
317 if (ARM_COND_ ## COND) { \
318 int8_t immediate = opcode; \
319 cpu->gprs[ARM_PC] += immediate << 1; \
320 THUMB_WRITE_PC; \
321 })
322
323DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
324DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
325DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
326DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
327DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
328DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
329DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
330DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
331DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
332DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
333DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
334DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
335DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
336DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
337
338DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
339DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
340
341DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
342 opcode & 0x00FF, \
343 cpu->gprs[ARM_SP], \
344 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
345 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
346 +=, \
347 , , \
348 cpu->gprs[ARM_SP] = address)
349
350DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
351 opcode & 0x00FF, \
352 cpu->gprs[ARM_SP], \
353 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
354 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
355 +=, \
356 , \
357 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
358 address += 4;, \
359 cpu->gprs[ARM_SP] = address; \
360 THUMB_WRITE_PC;)
361
362DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
363 opcode & 0x00FF, \
364 cpu->gprs[ARM_SP] - 4, \
365 (m = 0x80, i = 7; m; m >>= 1, --i), \
366 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
367 -=, \
368 , , \
369 cpu->gprs[ARM_SP] = address + 4)
370
371DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
372 opcode & 0x00FF, \
373 cpu->gprs[ARM_SP] - 4, \
374 (m = 0x80, i = 7; m; m >>= 1, --i), \
375 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
376 -=, \
377 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
378 address -= 4;, \
379 , \
380 cpu->gprs[ARM_SP] = address + 4)
381
382DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
383DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
384DEFINE_INSTRUCTION_THUMB(B, \
385 int16_t immediate = (opcode & 0x07FF) << 5; \
386 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4); \
387 THUMB_WRITE_PC;)
388
389DEFINE_INSTRUCTION_THUMB(BL1, \
390 int16_t immediate = (opcode & 0x07FF) << 5; \
391 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
392
393DEFINE_INSTRUCTION_THUMB(BL2, \
394 uint16_t immediate = (opcode & 0x07FF) << 1; \
395 uint32_t pc = cpu->gprs[ARM_PC]; \
396 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
397 cpu->gprs[ARM_LR] = pc - 1; \
398 THUMB_WRITE_PC;)
399
400DEFINE_INSTRUCTION_THUMB(BX, \
401 int rm = (opcode >> 3) & 0xF; \
402 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
403 int misalign = 0;
404 if (rm == ARM_PC) {
405 misalign = cpu->gprs[rm] & 0x00000002;
406 }
407 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign; \
408 if (cpu->executionMode == MODE_THUMB) { \
409 THUMB_WRITE_PC; \
410 } else { \
411 ARM_WRITE_PC; \
412 })
413
414DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
415
416#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
417 EMITTER ## NAME
418
419#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
420 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
421 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
422 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
423 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
424
425#define DUMMY(X, ...) X,
426#define DUMMY_4(...) \
427 DUMMY(__VA_ARGS__) \
428 DUMMY(__VA_ARGS__) \
429 DUMMY(__VA_ARGS__) \
430 DUMMY(__VA_ARGS__)
431
432#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
433 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
434 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
435 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
436 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
437 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
438 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
439 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
440 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
441 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
442 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
443 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
444 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
445 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
446 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
447 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
448 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
449 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
450 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
451 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
452 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
453 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
454 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
455 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
456 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
457 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
458 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
459 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
460 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
461 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
462 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
463 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
464 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
465 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
466 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
467 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
468 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
469 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
470 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
471 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
472 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
473 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
474 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
475 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
476 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
477 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
478 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
479 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
480 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
481 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
482 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
483 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
484 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
485 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
486 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
487 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
488 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
489 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
490 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
491 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
492 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
493 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
494 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
495 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
496 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
497 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
498 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
499 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
500 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
501 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
502 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
503 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
504 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
505 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
506 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
507 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
508 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
509 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
510 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
511 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
512 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
513 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
514 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
515 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
516 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
517 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
518 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
519 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
520 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
521 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
522 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
523 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
524
525static const ThumbInstruction _thumbTable[0x400] = {
526 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
527};