src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 ARM_STUB;
28}
29
30static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
31 int rm = opcode & 0x0000000F;
32 int immediate = (opcode & 0x00000F80) >> 7;
33 if (immediate) {
34 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
35 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
39 }
40}
41
42static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
43 int rm = opcode & 0x0000000F;
44 ARM_STUB;
45}
46
47static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
48 int rm = opcode & 0x0000000F;
49 int immediate = (opcode & 0x00000F80) >> 7;
50 if (immediate) {
51 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
52 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
53 } else {
54 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
55 cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
56 }
57}
58
59static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
60 int rm = opcode & 0x0000000F;
61 ARM_STUB;
62}
63
64static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int immediate = (opcode & 0x00000F80) >> 7;
67 if (immediate) {
68 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
69 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
70 } else {
71 // RRX
72 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
73 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
74 }
75}
76
77static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
78 int rm = opcode & 0x0000000F;
79 ARM_STUB;
80}
81
82static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
83 int rotate = (opcode & 0x00000F00) >> 7;
84 int immediate = opcode & 0x000000FF;
85 if (!rotate) {
86 cpu->shifterOperand = immediate;
87 cpu->shifterCarryOut = cpu->cpsr.c;
88 } else {
89 cpu->shifterOperand = ARM_ROR(immediate, rotate);
90 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
91 }
92}
93
94static const ARMInstruction _armTable[0x1000];
95
96static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
97 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
98 *opcodeOut = opcode;
99 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
100}
101
102void ARMStep(struct ARMCore* cpu) {
103 // TODO
104 uint32_t opcode;
105 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
106 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
107
108 int condition = opcode >> 28;
109 if (condition == 0xE) {
110 instruction(cpu, opcode);
111 return;
112 } else {
113 switch (condition) {
114 case 0x0:
115 if (!ARM_COND_EQ) {
116 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
117 return;
118 }
119 break;
120 case 0x1:
121 if (!ARM_COND_NE) {
122 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
123 return;
124 }
125 break;
126 case 0x2:
127 if (!ARM_COND_CS) {
128 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
129 return;
130 }
131 break;
132 case 0x3:
133 if (!ARM_COND_CC) {
134 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
135 return;
136 }
137 break;
138 case 0x4:
139 if (!ARM_COND_MI) {
140 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
141 return;
142 }
143 break;
144 case 0x5:
145 if (!ARM_COND_PL) {
146 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
147 return;
148 }
149 break;
150 case 0x6:
151 if (!ARM_COND_VS) {
152 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
153 return;
154 }
155 break;
156 case 0x7:
157 if (!ARM_COND_VC) {
158 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
159 return;
160 }
161 break;
162 case 0x8:
163 if (!ARM_COND_HI) {
164 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
165 return;
166 }
167 break;
168 case 0x9:
169 if (!ARM_COND_LS) {
170 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
171 return;
172 }
173 break;
174 case 0xA:
175 if (!ARM_COND_GE) {
176 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
177 return;
178 }
179 break;
180 case 0xB:
181 if (!ARM_COND_LT) {
182 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
183 return;
184 }
185 break;
186 case 0xC:
187 if (!ARM_COND_GT) {
188 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
189 return;
190 }
191 break;
192 case 0xD:
193 if (!ARM_COND_GE) {
194 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
195 return;
196 }
197 break;
198 default:
199 break;
200 }
201 }
202 instruction(cpu, opcode);
203}
204
205// Instruction definitions
206// Beware pre-processor antics
207
208#define ARM_ADDITION_S(M, N, D) \
209 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
210 cpu->cpsr = cpu->spsr; \
211 _ARMReadCPSR(cpu); \
212 } else { \
213 cpu->cpsr.n = ARM_SIGN(D); \
214 cpu->cpsr.z = !(D); \
215 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
216 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
217 }
218
219#define ARM_SUBTRACTION_S(M, N, D) \
220 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
221 cpu->cpsr = cpu->spsr; \
222 _ARMReadCPSR(cpu); \
223 } else { \
224 cpu->cpsr.n = ARM_SIGN(D); \
225 cpu->cpsr.z = !(D); \
226 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
227 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
228 }
229
230#define ARM_NEUTRAL_S(M, N, D) \
231 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
232 cpu->cpsr = cpu->spsr; \
233 _ARMReadCPSR(cpu); \
234 } else { \
235 cpu->cpsr.n = ARM_SIGN(D); \
236 cpu->cpsr.z = !(D); \
237 cpu->cpsr.c = cpu->shifterCarryOut; \
238 }
239
240#define ARM_NEUTRAL_HI_S(DLO, DHI) \
241 cpu->cpsr.n = ARM_SIGN(DHI); \
242 cpu->cpsr.z = !((DHI) | (DLO));
243
244#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
245#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
246#define ADDR_MODE_2_ADDRESS (address)
247#define ADDR_MODE_2_RN (cpu->gprs[rn])
248#define ADDR_MODE_2_RM (cpu->gprs[rm])
249#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
250#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
251#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
252#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
253#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
254#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
255#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
256
257#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
258#define ADDR_MODE_3_RN ADDR_MODE_2_RN
259#define ADDR_MODE_3_RM ADDR_MODE_2_RM
260#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
261#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
262#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
263
264#define ARM_LOAD_POST_BODY \
265 if (rd == ARM_PC) { \
266 ARM_WRITE_PC; \
267 }
268
269#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
270 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
271 BODY; \
272 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
273 }
274
275#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
276 DEFINE_INSTRUCTION_ARM(NAME, \
277 int rd = (opcode >> 12) & 0xF; \
278 int rn = (opcode >> 16) & 0xF; \
279 UNUSED(rn); \
280 SHIFTER(cpu, opcode); \
281 BODY; \
282 S_BODY; \
283 POST_BODY; \
284 if (rd == ARM_PC) { \
285 if (cpu->executionMode == MODE_ARM) { \
286 ARM_WRITE_PC; \
287 } else { \
288 THUMB_WRITE_PC; \
289 } \
290 })
291
292#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
311
312#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
322
323#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
324 DEFINE_INSTRUCTION_ARM(NAME, \
325 int rd = (opcode >> 12) & 0xF; \
326 int rdHi = (opcode >> 16) & 0xF; \
327 int rs = (opcode >> 8) & 0xF; \
328 int rm = opcode & 0xF; \
329 UNUSED(rdHi); \
330 BODY; \
331 S_BODY; \
332 if (rd == ARM_PC) { \
333 ARM_WRITE_PC; \
334 })
335
336#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
337 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
338 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
339
340#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
341 DEFINE_INSTRUCTION_ARM(NAME, \
342 uint32_t address; \
343 int rn = (opcode >> 16) & 0xF; \
344 int rd = (opcode >> 12) & 0xF; \
345 int rm = opcode & 0xF; \
346 UNUSED(rm); \
347 address = ADDRESS; \
348 BODY; \
349 WRITEBACK;)
350
351#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
358
359#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
370
371#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
384
385#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
388
389#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
390 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
391 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
392 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
393 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
396
397#define ARM_MS_PRE \
398 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
399 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
400
401#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
402
403#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
404#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
405#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
406#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
407#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
408#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
409#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
410#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
411
412#define ARM_M_INCREMENT(BODY) \
413 for (m = rs, i = 0; m; m >>= 1, ++i) { \
414 if (m & 1) { \
415 BODY; \
416 addr += 4; \
417 } \
418 }
419
420#define ARM_M_DECREMENT(BODY) \
421 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
422 if (rs & m) { \
423 BODY; \
424 addr -= 4; \
425 } \
426 }
427
428#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
429 DEFINE_INSTRUCTION_ARM(NAME, \
430 int rn = (opcode >> 16) & 0xF; \
431 int rs = opcode & 0x0000FFFF; \
432 int m; \
433 int i; \
434 ADDRESS; \
435 S_PRE; \
436 LOOP(BODY); \
437 S_POST; \
438 WRITEBACK; \
439 POST_BODY;)
440
441
442#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
450 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
451 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
459
460// Begin ALU definitions
461
462DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
463 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
464
465DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
466 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
467 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
468
469DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
470 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
471
472DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
473 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
474
475DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
476 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
477
478DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
479 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
480
481DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
482 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
483
484DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
485 cpu->gprs[rd] = cpu->shifterOperand;, )
486
487DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
488 cpu->gprs[rd] = ~cpu->shifterOperand;, )
489
490DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
491 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
492
493DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d),
494 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
495
496DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d),
497 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
498 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
499
500DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d),
501 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
502 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
503
504DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d),
505 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
506
507DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
508 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
509
510DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
511 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
512
513// End ALU definitions
514
515// Begin multiply definitions
516
517DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
518DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
519DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
520DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
521DEFINE_INSTRUCTION_ARM(SMULL, ARM_STUB)
522DEFINE_INSTRUCTION_ARM(SMULLS, ARM_STUB)
523DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
524DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
525DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
526 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
527 cpu->gprs[rd] = d;
528 cpu->gprs[rdHi] = d >> 32;,
529 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
530
531// End multiply definitions
532
533// Begin load/store definitions
534
535DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;)
536DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;)
537DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;)
538DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;)
539DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;)
540DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
541DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
542DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
543
544DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
545 enum PrivilegeMode priv = cpu->privilegeMode;
546 ARMSetPrivilegeMode(cpu, MODE_USER);
547 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
548 ARMSetPrivilegeMode(cpu, priv);
549 ARM_LOAD_POST_BODY;)
550
551DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
552 enum PrivilegeMode priv = cpu->privilegeMode;
553 ARMSetPrivilegeMode(cpu, MODE_USER);
554 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
555 ARMSetPrivilegeMode(cpu, priv);
556 ARM_LOAD_POST_BODY;)
557
558DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
559 enum PrivilegeMode priv = cpu->privilegeMode;
560 ARMSetPrivilegeMode(cpu, MODE_USER);
561 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
562 ARMSetPrivilegeMode(cpu, priv);)
563
564DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
565 enum PrivilegeMode priv = cpu->privilegeMode;
566 ARMSetPrivilegeMode(cpu, MODE_USER);
567 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
568 ARMSetPrivilegeMode(cpu, priv);)
569
570DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
571 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr);,
572 if (rs & 0x8000) {
573 ARM_WRITE_PC;
574 })
575
576DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i]);, )
577
578DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
579DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
580
581// End load/store definitions
582
583// Begin branch definitions
584
585DEFINE_INSTRUCTION_ARM(B,
586 int32_t offset = opcode << 8;
587 offset >>= 6;
588 cpu->gprs[ARM_PC] += offset;
589 ARM_WRITE_PC;)
590
591DEFINE_INSTRUCTION_ARM(BL,
592 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
593 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
594 cpu->gprs[ARM_PC] += immediate >> 6;
595 ARM_WRITE_PC;)
596
597DEFINE_INSTRUCTION_ARM(BX,
598 int rm = opcode & 0x0000000F;
599 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
600 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
601 if (cpu->executionMode == MODE_THUMB) {
602 THUMB_WRITE_PC;
603 } else {
604 ARM_WRITE_PC;
605 })
606
607// End branch definitions
608
609// Begin miscellaneous definitions
610
611DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
612DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
613
614DEFINE_INSTRUCTION_ARM(MSR,
615 int c = opcode & 0x00010000;
616 int f = opcode & 0x00080000;
617 int32_t operand = cpu->gprs[opcode & 0x0000000F];
618 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
619 if (mask & PSR_USER_MASK) {
620 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
621 }
622 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
623 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
624 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
625 })
626
627DEFINE_INSTRUCTION_ARM(MSRR,
628 int c = opcode & 0x00010000;
629 int f = opcode & 0x00080000;
630 int32_t operand = cpu->gprs[opcode & 0x0000000F];
631 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
632 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
633 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
634
635DEFINE_INSTRUCTION_ARM(MRS, \
636 int rd = (opcode >> 12) & 0xF; \
637 cpu->gprs[rd] = cpu->cpsr.packed;)
638
639DEFINE_INSTRUCTION_ARM(MRSR, \
640 int rd = (opcode >> 12) & 0xF; \
641 cpu->gprs[rd] = cpu->spsr.packed;)
642
643DEFINE_INSTRUCTION_ARM(MSRI,
644 int c = opcode & 0x00010000;
645 int f = opcode & 0x00080000;
646 int rotate = (opcode & 0x00000F00) >> 8;
647 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
648 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
649 if (mask & PSR_USER_MASK) {
650 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
651 }
652 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
653 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
654 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
655 })
656
657DEFINE_INSTRUCTION_ARM(MSRRI,
658 int c = opcode & 0x00010000;
659 int f = opcode & 0x00080000;
660 int rotate = (opcode & 0x00000F00) >> 8;
661 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
662 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
663 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
664 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
665
666DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
667
668#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
669 EMITTER ## NAME
670
671#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
672 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
673 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
674
675#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
676 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
677 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
678 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
679 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
680 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
681 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
682 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
683 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
684 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
685 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
686 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
687 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
688 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
689 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
690 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
691 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
692
693#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
694 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
695 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
696
697#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
698 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
699 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
700 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
701 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
702 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
703 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
704 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
705 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
706 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
707 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
708 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
709 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
710 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
711 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
712 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
713 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
714
715#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
716 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
717 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
718
719#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
720 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
721
722// TODO: Support coprocessors
723#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
724 DO_8(0), \
725 DO_8(0)
726
727#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
728 DO_8(DO_8(DO_INTERLACE(0, 0))), \
729 DO_8(DO_8(DO_INTERLACE(0, 0)))
730
731#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
732 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
733
734#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
735 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
736 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
737 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
738 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
739 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
740 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
741 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
742 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
743 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
744 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
745 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
746 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
747 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
748 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
749 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
750 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
751 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
752 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
753 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
754 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
755 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
756 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
757 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
758 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
759 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
760 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
761 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
762 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
763 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
764 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
765 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
766 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
767 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
768 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
769 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
770 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
771 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
772 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
773 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
774 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
775 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
776 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
777 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
778 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
779 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
780 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
781 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
782 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
783 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
784 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
785 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
786 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
787 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
788 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
789 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
790 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
791 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
792 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
793 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
794 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
795 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
796 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
797 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
798 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
799 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
800 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
801 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
802 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
803 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
804 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
805 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
806 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
807 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
808 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
809 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
818 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
819 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
820 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
821 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
822 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
823 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
824 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
825 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
826 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
827 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
828 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
829 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
830 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
831 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
832 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
833 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
834 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
835 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
836 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
837 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
838 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
839 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
840 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
841 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
842 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
843 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
844 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
845 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
846 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
847 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
848 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
849 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
850 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
851 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
852 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
853 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
854 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
855 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
856 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
857 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
858 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
859 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
860 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
861 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
862 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
863 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
864 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
865 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
866 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
867 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
868 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
869 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
870 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
871 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
872 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
873 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
874 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
875 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
876 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
877 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
878 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
879 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
880 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
881 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
882 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
883 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
884 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
885 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
886 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
887 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
888 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
889 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
890 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
891 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
892 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
893 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
894 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
895 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
896 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
897 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
898 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
899 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
900 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
901 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
902 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
903 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
904 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
905 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
906 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
907 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
908 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
909 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
910 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
911 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
912 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
913 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
914 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
915 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
916 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
917 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
918 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
919 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
920 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
921 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
922 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
923 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
924 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
925 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
926 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
927 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
928 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
929 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
930 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
931 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
932 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
933 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
934 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
935 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
936 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
937 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
938 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
939 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
940 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
941 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
942 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
943 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
944 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
945 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
946 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
947 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
948 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
949 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
950 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
951 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
952 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
953 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
954 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
955 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
956 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
957 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
958 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
959 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
960 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
961 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
962 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
963 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
964 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
965 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
966 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
967 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
968 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
969 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
970 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
971 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
972 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
973 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
974 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
975 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
976 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
977 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
978 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
979 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
980 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
981 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
982 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
983 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
984 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
985 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
986 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
987 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
988 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
989 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
990 DECLARE_ARM_SWI_BLOCK(EMITTER)
991
992static const ARMInstruction _armTable[0x1000] = {
993 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
994};