src/arm/decoder.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef ARM_DECODER_H
7#define ARM_DECODER_H
8
9#include "util/common.h"
10
11CXX_GUARD_START
12
13#include "arm.h"
14
15// Bit 0: a register is involved with this operand
16// Bit 1: an immediate is invovled with this operand
17// Bit 2: a memory access is invovled with this operand
18// Bit 3: the destination of this operand is affected by this opcode
19// Bit 4: this operand is shifted by a register
20// Bit 5: this operand is shifted by an immediate
21#define ARM_OPERAND_NONE 0x00000000
22#define ARM_OPERAND_REGISTER_1 0x00000001
23#define ARM_OPERAND_IMMEDIATE_1 0x00000002
24#define ARM_OPERAND_MEMORY_1 0x00000004
25#define ARM_OPERAND_AFFECTED_1 0x00000008
26#define ARM_OPERAND_SHIFT_REGISTER_1 0x00000010
27#define ARM_OPERAND_SHIFT_IMMEDIATE_1 0x00000020
28#define ARM_OPERAND_1 0x000000FF
29
30#define ARM_OPERAND_REGISTER_2 0x00000100
31#define ARM_OPERAND_IMMEDIATE_2 0x00000200
32#define ARM_OPERAND_MEMORY_2 0x00000400
33#define ARM_OPERAND_AFFECTED_2 0x00000800
34#define ARM_OPERAND_SHIFT_REGISTER_2 0x00001000
35#define ARM_OPERAND_SHIFT_IMMEDIATE_2 0x00002000
36#define ARM_OPERAND_2 0x0000FF00
37
38#define ARM_OPERAND_REGISTER_3 0x00010000
39#define ARM_OPERAND_IMMEDIATE_3 0x00020000
40#define ARM_OPERAND_MEMORY_3 0x00040000
41#define ARM_OPERAND_AFFECTED_3 0x00080000
42#define ARM_OPERAND_SHIFT_REGISTER_3 0x00100000
43#define ARM_OPERAND_SHIFT_IMMEDIATE_3 0x00200000
44#define ARM_OPERAND_3 0x00FF0000
45
46#define ARM_OPERAND_REGISTER_4 0x01000000
47#define ARM_OPERAND_IMMEDIATE_4 0x02000000
48#define ARM_OPERAND_MEMORY_4 0x04000000
49#define ARM_OPERAND_AFFECTED_4 0x08000000
50#define ARM_OPERAND_SHIFT_REGISTER_4 0x10000000
51#define ARM_OPERAND_SHIFT_IMMEDIATE_4 0x20000000
52#define ARM_OPERAND_4 0xFF000000
53
54#define ARM_OPERAND_MEMORY (ARM_OPERAND_MEMORY_1 | ARM_OPERAND_MEMORY_2 | ARM_OPERAND_MEMORY_3 | ARM_OPERAND_MEMORY_4)
55
56#define ARM_MEMORY_REGISTER_BASE 0x0001
57#define ARM_MEMORY_IMMEDIATE_OFFSET 0x0002
58#define ARM_MEMORY_REGISTER_OFFSET 0x0004
59#define ARM_MEMORY_SHIFTED_OFFSET 0x0008
60#define ARM_MEMORY_PRE_INCREMENT 0x0010
61#define ARM_MEMORY_POST_INCREMENT 0x0020
62#define ARM_MEMORY_OFFSET_SUBTRACT 0x0040
63#define ARM_MEMORY_WRITEBACK 0x0080
64#define ARM_MEMORY_DECREMENT_AFTER 0x0000
65#define ARM_MEMORY_INCREMENT_AFTER 0x0100
66#define ARM_MEMORY_DECREMENT_BEFORE 0x0200
67#define ARM_MEMORY_INCREMENT_BEFORE 0x0300
68#define ARM_MEMORY_SPSR_SWAP 0x0400
69
70#define ARM_PSR_C 1
71#define ARM_PSR_X 2
72#define ARM_PSR_S 4
73#define ARM_PSR_F 8
74#define ARM_PSR_MASK 0xF
75
76#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
77
78enum ARMCondition {
79 ARM_CONDITION_EQ = 0x0,
80 ARM_CONDITION_NE = 0x1,
81 ARM_CONDITION_CS = 0x2,
82 ARM_CONDITION_CC = 0x3,
83 ARM_CONDITION_MI = 0x4,
84 ARM_CONDITION_PL = 0x5,
85 ARM_CONDITION_VS = 0x6,
86 ARM_CONDITION_VC = 0x7,
87 ARM_CONDITION_HI = 0x8,
88 ARM_CONDITION_LS = 0x9,
89 ARM_CONDITION_GE = 0xA,
90 ARM_CONDITION_LT = 0xB,
91 ARM_CONDITION_GT = 0xC,
92 ARM_CONDITION_LE = 0xD,
93 ARM_CONDITION_AL = 0xE,
94 ARM_CONDITION_NV = 0xF
95};
96
97enum ARMShifterOperation {
98 ARM_SHIFT_NONE = 0,
99 ARM_SHIFT_LSL,
100 ARM_SHIFT_LSR,
101 ARM_SHIFT_ASR,
102 ARM_SHIFT_ROR,
103 ARM_SHIFT_RRX
104};
105
106union ARMOperand {
107 struct {
108 uint8_t reg;
109 uint8_t shifterOp;
110 union {
111 uint8_t shifterReg;
112 uint8_t shifterImm;
113 uint8_t psrBits;
114 };
115 };
116 int32_t immediate;
117};
118
119enum ARMMemoryAccessType {
120 ARM_ACCESS_WORD = 4,
121 ARM_ACCESS_HALFWORD = 2,
122 ARM_ACCESS_SIGNED_HALFWORD = 10,
123 ARM_ACCESS_BYTE = 1,
124 ARM_ACCESS_SIGNED_BYTE = 9,
125 ARM_ACCESS_TRANSLATED_WORD = 20,
126 ARM_ACCESS_TRANSLATED_BYTE = 17
127};
128
129enum ARMBranchType {
130 ARM_BRANCH_NONE = 0,
131 ARM_BRANCH = 1,
132 ARM_BRANCH_INDIRECT = 2,
133 ARM_BRANCH_LINKED = 4
134};
135
136struct ARMMemoryAccess {
137 uint8_t baseReg;
138 uint8_t width;
139 uint16_t format;
140 union ARMOperand offset;
141};
142
143enum ARMMnemonic {
144 ARM_MN_ILL = 0,
145 ARM_MN_ADC,
146 ARM_MN_ADD,
147 ARM_MN_AND,
148 ARM_MN_ASR,
149 ARM_MN_B,
150 ARM_MN_BIC,
151 ARM_MN_BKPT,
152 ARM_MN_BL,
153 ARM_MN_BX,
154 ARM_MN_CMN,
155 ARM_MN_CMP,
156 ARM_MN_EOR,
157 ARM_MN_LDM,
158 ARM_MN_LDR,
159 ARM_MN_LSL,
160 ARM_MN_LSR,
161 ARM_MN_MLA,
162 ARM_MN_MOV,
163 ARM_MN_MRS,
164 ARM_MN_MSR,
165 ARM_MN_MUL,
166 ARM_MN_MVN,
167 ARM_MN_NEG,
168 ARM_MN_ORR,
169 ARM_MN_ROR,
170 ARM_MN_RSB,
171 ARM_MN_RSC,
172 ARM_MN_SBC,
173 ARM_MN_SMLAL,
174 ARM_MN_SMULL,
175 ARM_MN_STM,
176 ARM_MN_STR,
177 ARM_MN_SUB,
178 ARM_MN_SWI,
179 ARM_MN_SWP,
180 ARM_MN_TEQ,
181 ARM_MN_TST,
182 ARM_MN_UMLAL,
183 ARM_MN_UMULL,
184
185 ARM_MN_MAX
186};
187
188enum {
189 ARM_CPSR = 16,
190 ARM_SPSR = 17
191};
192
193struct ARMInstructionInfo {
194 uint32_t opcode;
195 union ARMOperand op1;
196 union ARMOperand op2;
197 union ARMOperand op3;
198 union ARMOperand op4;
199 struct ARMMemoryAccess memory;
200 int operandFormat;
201 unsigned execMode : 1;
202 bool traps : 1;
203 bool affectsCPSR : 1;
204 unsigned branchType : 3;
205 unsigned condition : 4;
206 unsigned mnemonic : 6;
207 unsigned iCycles : 3;
208 unsigned cCycles : 4;
209 unsigned sInstructionCycles : 4;
210 unsigned nInstructionCycles : 4;
211 unsigned sDataCycles : 10;
212 unsigned nDataCycles : 10;
213};
214
215void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
216void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
217bool ARMDecodeThumbCombine(struct ARMInstructionInfo* info1, struct ARMInstructionInfo* info2,
218 struct ARMInstructionInfo* out);
219int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
220
221CXX_GUARD_END
222
223#endif