src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-thumb.h"
7
8#include "isa-inlines.h"
9#include "emitter-thumb.h"
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 cpu->cpsr.n = ARM_SIGN(D); \
16 cpu->cpsr.z = !(D); \
17 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
18 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
19
20#define THUMB_SUBTRACTION_S(M, N, D) \
21 cpu->cpsr.n = ARM_SIGN(D); \
22 cpu->cpsr.z = !(D); \
23 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
24 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
25
26#define THUMB_NEUTRAL_S(M, N, D) \
27 cpu->cpsr.n = ARM_SIGN(D); \
28 cpu->cpsr.z = !(D);
29
30#define THUMB_ADDITION(D, M, N) \
31 int n = N; \
32 int m = M; \
33 D = M + N; \
34 THUMB_ADDITION_S(m, n, D)
35
36#define THUMB_SUBTRACTION(D, M, N) \
37 int n = N; \
38 int m = M; \
39 D = M - N; \
40 THUMB_SUBTRACTION_S(m, n, D)
41
42#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
43
44#define THUMB_LOAD_POST_BODY \
45 currentCycles += 1 + cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
46
47#define THUMB_STORE_POST_BODY \
48 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
49
50#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
51 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
52 int currentCycles = THUMB_PREFETCH_CYCLES; \
53 BODY; \
54 cpu->cycles += currentCycles; \
55 }
56
57#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
58 DEFINE_INSTRUCTION_THUMB(NAME, \
59 int immediate = IMMEDIATE; \
60 int rd = opcode & 0x0007; \
61 int rm = (opcode >> 3) & 0x0007; \
62 BODY;)
63
64#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
65 COUNT_CALL_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
66
67DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
68 if (!immediate) {
69 cpu->gprs[rd] = cpu->gprs[rm];
70 } else {
71 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
72 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
73 }
74 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
75
76DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
77 if (!immediate) {
78 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
79 cpu->gprs[rd] = 0;
80 } else {
81 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
82 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
83 }
84 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
85
86DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
87 if (!immediate) {
88 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
89 if (cpu->cpsr.c) {
90 cpu->gprs[rd] = 0xFFFFFFFF;
91 } else {
92 cpu->gprs[rd] = 0;
93 }
94 } else {
95 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
96 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
97 }
98 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
99
100DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
103DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
105DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
106
107#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
108 DEFINE_INSTRUCTION_THUMB(NAME, \
109 int rm = RM; \
110 int rd = opcode & 0x0007; \
111 int rn = (opcode >> 3) & 0x0007; \
112 BODY;)
113
114#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
115 COUNT_CALL_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
116
117DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
118DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
119
120#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
121 DEFINE_INSTRUCTION_THUMB(NAME, \
122 int immediate = IMMEDIATE; \
123 int rd = opcode & 0x0007; \
124 int rn = (opcode >> 3) & 0x0007; \
125 BODY;)
126
127#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
128 COUNT_CALL_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
129
130DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
131DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
132
133#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
134 DEFINE_INSTRUCTION_THUMB(NAME, \
135 int rd = RD; \
136 int immediate = opcode & 0x00FF; \
137 BODY;)
138
139#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
140 COUNT_CALL_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
141
142DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
143DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
144DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
145DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
146
147#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
148 DEFINE_INSTRUCTION_THUMB(NAME, \
149 int rd = opcode & 0x0007; \
150 int rn = (opcode >> 3) & 0x0007; \
151 BODY;)
152
153DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
154DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
155DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
156 int rs = cpu->gprs[rn] & 0xFF;
157 if (rs) {
158 if (rs < 32) {
159 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
160 cpu->gprs[rd] <<= rs;
161 } else {
162 if (rs > 32) {
163 cpu->cpsr.c = 0;
164 } else {
165 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
166 }
167 cpu->gprs[rd] = 0;
168 }
169 }
170 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
171
172DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
173 int rs = cpu->gprs[rn] & 0xFF;
174 if (rs) {
175 if (rs < 32) {
176 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
177 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
178 } else {
179 if (rs > 32) {
180 cpu->cpsr.c = 0;
181 } else {
182 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
183 }
184 cpu->gprs[rd] = 0;
185 }
186 }
187 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
188
189DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
190 int rs = cpu->gprs[rn] & 0xFF;
191 if (rs) {
192 if (rs < 32) {
193 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
194 cpu->gprs[rd] >>= rs;
195 } else {
196 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
197 if (cpu->cpsr.c) {
198 cpu->gprs[rd] = 0xFFFFFFFF;
199 } else {
200 cpu->gprs[rd] = 0;
201 }
202 }
203 }
204 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
205
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
207 int n = cpu->gprs[rn];
208 int d = cpu->gprs[rd];
209 cpu->gprs[rd] = d + n + cpu->cpsr.c;
210 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
211
212DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
213 int n = cpu->gprs[rn] + !cpu->cpsr.c;
214 int d = cpu->gprs[rd];
215 cpu->gprs[rd] = d - n;
216 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
217DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
218 int rs = cpu->gprs[rn] & 0xFF;
219 if (rs) {
220 int r4 = rs & 0x1F;
221 if (r4 > 0) {
222 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
223 cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
224 } else {
225 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
226 }
227 }
228 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
231DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
232DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
233DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
234DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
235DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
236DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
237
238#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
239 DEFINE_INSTRUCTION_THUMB(NAME, \
240 int rd = (opcode & 0x0007) | H1; \
241 int rm = ((opcode >> 3) & 0x0007) | H2; \
242 BODY;)
243
244#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
245 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
246 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
247 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
248 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
249
250DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
251 cpu->gprs[rd] += cpu->gprs[rm];
252 if (rd == ARM_PC) {
253 THUMB_WRITE_PC;
254 })
255
256DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
257DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
258 cpu->gprs[rd] = cpu->gprs[rm];
259 if (rd == ARM_PC) {
260 THUMB_WRITE_PC;
261 })
262
263#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
264 DEFINE_INSTRUCTION_THUMB(NAME, \
265 int rd = RD; \
266 int immediate = (opcode & 0x00FF) << 2; \
267 BODY;)
268
269#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
270 COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
271
272DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
273DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
274DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
275
276DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
277DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
278
279#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
280 DEFINE_INSTRUCTION_THUMB(NAME, \
281 int rm = RM; \
282 int rd = opcode & 0x0007; \
283 int rn = (opcode >> 3) & 0x0007; \
284 BODY;)
285
286#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
287 COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
288
289DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
290DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
291DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
292DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
293DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = ARM_SXT_16(cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
294DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
295DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
296DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
297
298#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
299 DEFINE_INSTRUCTION_THUMB(NAME, \
300 int rn = RN; \
301 UNUSED(rn); \
302 int rs = opcode & 0xFF; \
303 int32_t address = cpu->gprs[RN]; \
304 PRE_BODY; \
305 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
306 WRITEBACK;)
307
308#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, LS, DIRECTION, WRITEBACK) \
309 COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, LS, DIRECTION, , WRITEBACK)
310
311DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
312 load,
313 IA,
314 THUMB_LOAD_POST_BODY;
315 if (!((1 << rn) & rs)) {
316 cpu->gprs[rn] = address;
317 })
318
319DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
320 store,
321 IA,
322 THUMB_STORE_POST_BODY;
323 cpu->gprs[rn] = address;)
324
325#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
326 DEFINE_INSTRUCTION_THUMB(B ## COND, \
327 if (ARM_COND_ ## COND) { \
328 int8_t immediate = opcode; \
329 cpu->gprs[ARM_PC] += immediate << 1; \
330 THUMB_WRITE_PC; \
331 })
332
333DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
334DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
335DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
336DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
337DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
338DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
339DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
340DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
341DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
342DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
343DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
344DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
345DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
346DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
347
348DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
349DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
350
351DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
352 ARM_SP,
353 load,
354 IA,
355 ,
356 THUMB_LOAD_POST_BODY;
357 cpu->gprs[ARM_SP] = address)
358
359DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
360 ARM_SP,
361 load,
362 IA,
363 rs |= 1 << ARM_PC,
364 THUMB_LOAD_POST_BODY;
365 cpu->gprs[ARM_SP] = address;
366 THUMB_WRITE_PC;)
367
368DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
369 ARM_SP,
370 store,
371 DB,
372 ,
373 THUMB_STORE_POST_BODY;
374 cpu->gprs[ARM_SP] = address)
375
376DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
377 ARM_SP,
378 store,
379 DB,
380 rs |= 1 << ARM_LR,
381 THUMB_STORE_POST_BODY;
382 cpu->gprs[ARM_SP] = address)
383
384DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
385DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
386DEFINE_INSTRUCTION_THUMB(B,
387 int16_t immediate = (opcode & 0x07FF) << 5;
388 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
389 THUMB_WRITE_PC;)
390
391DEFINE_INSTRUCTION_THUMB(BL1,
392 int16_t immediate = (opcode & 0x07FF) << 5;
393 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
394
395DEFINE_INSTRUCTION_THUMB(BL2,
396 uint16_t immediate = (opcode & 0x07FF) << 1;
397 uint32_t pc = cpu->gprs[ARM_PC];
398 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
399 cpu->gprs[ARM_LR] = pc - 1;
400 THUMB_WRITE_PC;)
401
402DEFINE_INSTRUCTION_THUMB(BX,
403 int rm = (opcode >> 3) & 0xF;
404 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
405 int misalign = 0;
406 if (rm == ARM_PC) {
407 misalign = cpu->gprs[rm] & 0x00000002;
408 }
409 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
410 if (cpu->executionMode == MODE_THUMB) {
411 THUMB_WRITE_PC;
412 } else {
413 ARM_WRITE_PC;
414 })
415
416DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
417
418const ThumbInstruction _thumbTable[0x400] = {
419 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
420};