1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_2Mb.gb".
  3
  4[labels]
  501:4c00 print_load_font
  601:4c0d print_string
  701:4c17 print_a
  801:4c21 print_newline
  901:4c2c print_digit
 1001:4c39 print_regs
 1101:4c42 _print_sl_data0
 1201:4c48 _print_sl_out0
 1301:4c55 _print_sl_data1
 1401:4c5b _print_sl_out1
 1501:4c6d _print_sl_data2
 1601:4c73 _print_sl_out2
 1701:4c80 _print_sl_data3
 1801:4c86 _print_sl_out3
 1901:4c98 _print_sl_data4
 2001:4c9e _print_sl_out4
 2101:4cab _print_sl_data5
 2201:4cb1 _print_sl_out5
 2301:4cc3 _print_sl_data6
 2401:4cc9 _print_sl_out6
 2501:4cd6 _print_sl_data7
 2601:4cdc _print_sl_out7
 2701:4001 font
 2800:c000 regs_save
 2900:c000 regs_save.f
 3000:c001 regs_save.a
 3100:c002 regs_save.c
 3200:c003 regs_save.b
 3300:c004 regs_save.e
 3400:c005 regs_save.d
 3500:c006 regs_save.l
 3600:c007 regs_save.h
 3700:c008 regs_flags
 3800:c009 regs_assert
 3900:c009 regs_assert.f
 4000:c00a regs_assert.a
 4100:c00b regs_assert.c
 4200:c00c regs_assert.b
 4300:c00d regs_assert.e
 4400:c00e regs_assert.d
 4500:c00f regs_assert.l
 4600:c010 regs_assert.h
 4700:c011 memdump_len
 4800:c012 memdump_addr
 4901:47f1 memcpy
 5001:47fa memset
 5101:4803 memcmp
 5201:4811 clear_vram
 5301:481b clear_oam
 5401:4825 disable_lcd_safe
 5501:482b _wait_ly_0
 5601:4831 _wait_ly_1
 5701:483a reset_screen
 5801:484e process_results
 5901:4862 _wait_ly_2
 6001:4868 _wait_ly_3
 6101:487e _print_results_halt_0
 6201:4881 _process_results_cb
 6301:488c _print_sl_data8
 6401:4896 _print_sl_out8
 6501:48b0 _print_sl_data9
 6601:48bb _print_sl_out9
 6701:48d3 _print_sl_data10
 6801:48df _print_sl_out10
 6901:48e0 dump_mem
 7001:48ff _dump_mem_line
 7101:4929 _check_asserts
 7201:4937 _print_sl_data11
 7301:493a _print_sl_out11
 7401:4946 _print_sl_data12
 7501:4948 _print_sl_out12
 7601:4950 _print_sl_data13
 7701:4953 _print_sl_out13
 7801:495d __check_assert_fail0
 7901:4968 _print_sl_data14
 8001:496b _print_sl_out14
 8101:496e __check_assert_ok0
 8201:4976 _print_sl_data15
 8301:497b _print_sl_out15
 8401:497d __check_assert_skip0
 8501:4985 _print_sl_data16
 8601:498d _print_sl_out16
 8701:498d __check_assert_out0
 8801:4999 _print_sl_data17
 8901:499b _print_sl_out17
 9001:49a3 _print_sl_data18
 9101:49a6 _print_sl_out18
 9201:49b0 __check_assert_fail1
 9301:49bb _print_sl_data19
 9401:49be _print_sl_out19
 9501:49c1 __check_assert_ok1
 9601:49c9 _print_sl_data20
 9701:49ce _print_sl_out20
 9801:49d0 __check_assert_skip1
 9901:49d8 _print_sl_data21
10001:49e0 _print_sl_out21
10101:49e0 __check_assert_out1
10201:49eb _print_sl_data22
10301:49ee _print_sl_out22
10401:49fa _print_sl_data23
10501:49fc _print_sl_out23
10601:4a04 _print_sl_data24
10701:4a07 _print_sl_out24
10801:4a11 __check_assert_fail2
10901:4a1c _print_sl_data25
11001:4a1f _print_sl_out25
11101:4a22 __check_assert_ok2
11201:4a2a _print_sl_data26
11301:4a2f _print_sl_out26
11401:4a31 __check_assert_skip2
11501:4a39 _print_sl_data27
11601:4a41 _print_sl_out27
11701:4a41 __check_assert_out2
11801:4a4d _print_sl_data28
11901:4a4f _print_sl_out28
12001:4a57 _print_sl_data29
12101:4a5a _print_sl_out29
12201:4a64 __check_assert_fail3
12301:4a6f _print_sl_data30
12401:4a72 _print_sl_out30
12501:4a75 __check_assert_ok3
12601:4a7d _print_sl_data31
12701:4a82 _print_sl_out31
12801:4a84 __check_assert_skip3
12901:4a8c _print_sl_data32
13001:4a94 _print_sl_out32
13101:4a94 __check_assert_out3
13201:4a9f _print_sl_data33
13301:4aa2 _print_sl_out33
13401:4aae _print_sl_data34
13501:4ab0 _print_sl_out34
13601:4ab8 _print_sl_data35
13701:4abb _print_sl_out35
13801:4ac5 __check_assert_fail4
13901:4ad0 _print_sl_data36
14001:4ad3 _print_sl_out36
14101:4ad6 __check_assert_ok4
14201:4ade _print_sl_data37
14301:4ae3 _print_sl_out37
14401:4ae5 __check_assert_skip4
14501:4aed _print_sl_data38
14601:4af5 _print_sl_out38
14701:4af5 __check_assert_out4
14801:4b01 _print_sl_data39
14901:4b03 _print_sl_out39
15001:4b0b _print_sl_data40
15101:4b0e _print_sl_out40
15201:4b18 __check_assert_fail5
15301:4b23 _print_sl_data41
15401:4b26 _print_sl_out41
15501:4b29 __check_assert_ok5
15601:4b31 _print_sl_data42
15701:4b36 _print_sl_out42
15801:4b38 __check_assert_skip5
15901:4b40 _print_sl_data43
16001:4b48 _print_sl_out43
16101:4b48 __check_assert_out5
16201:4b53 _print_sl_data44
16301:4b56 _print_sl_out44
16401:4b62 _print_sl_data45
16501:4b64 _print_sl_out45
16601:4b6c _print_sl_data46
16701:4b6f _print_sl_out46
16801:4b79 __check_assert_fail6
16901:4b84 _print_sl_data47
17001:4b87 _print_sl_out47
17101:4b8a __check_assert_ok6
17201:4b92 _print_sl_data48
17301:4b97 _print_sl_out48
17401:4b99 __check_assert_skip6
17501:4ba1 _print_sl_data49
17601:4ba9 _print_sl_out49
17701:4ba9 __check_assert_out6
17801:4bb5 _print_sl_data50
17901:4bb7 _print_sl_out50
18001:4bbf _print_sl_data51
18101:4bc2 _print_sl_out51
18201:4bcc __check_assert_fail7
18301:4bd7 _print_sl_data52
18401:4bda _print_sl_out52
18501:4bdd __check_assert_ok7
18601:4be5 _print_sl_data53
18701:4bea _print_sl_out53
18801:4bec __check_assert_skip7
18901:4bf4 _print_sl_data54
19001:4bfc _print_sl_out54
19101:4bfc __check_assert_out7
19200:016b fail
19300:017f _wait_ly_4
19400:0185 _wait_ly_5
19500:019b _print_results_halt_1
19600:019e _fail_cb
19700:01a6 _print_sl_data55
19800:01b2 _print_sl_out55
19900:01c2 _print_sl_data56
20000:01ce _print_sl_out56
20100:01d8 _print_sl_data57
20200:01e4 _print_sl_out57
20300:01ef _print_sl_data58
20400:01f5 _print_sl_out58
20500:0208 _print_sl_data59
20600:0215 _print_sl_out59
20700:0225 _print_sl_data60
20800:0232 _print_sl_out60
20900:0242 _print_sl_data61
21000:024f _print_sl_out61
21100:025a c000_functions_start
21200:025a run_test_suite
21300:0284 _wait_ly_6
21400:028a _wait_ly_7
21500:02a0 _print_results_halt_2
21600:02a3 _test_ok_cb_0
21700:02ab _print_sl_data62
21800:02b3 _print_sl_out62
21900:02b6 run_tests
22000:02c4 run_test_cases
22100:02d2 test_case
22200:02ef restore_mbc1
22300:02f8 switch_bank
22400:0309 fetch_expected_value
22500:0328 c000_functions_end
22600:0328 expected_banks