1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/internal/arm/arm.h>
 16#include <mgba/internal/ds/dma.h>
 17#include <mgba/internal/ds/io.h>
 18#include <mgba/internal/ds/slot1.h>
 19#include <mgba/internal/ds/spi.h>
 20
 21enum DSMemoryRegion {
 22	DS7_REGION_BIOS = 0x0,
 23	DS9_REGION_ITCM = 0x0,
 24	DS9_REGION_ITCM_MIRROR = 0x1,
 25	DS_REGION_RAM = 0x2,
 26	DS_REGION_WORKING_RAM = 0x3,
 27	DS_REGION_IO = 0x4,
 28	DS9_REGION_PALETTE_RAM = 0x5,
 29	DS_REGION_VRAM = 0x6,
 30	DS9_REGION_OAM = 0x7,
 31	DS_REGION_SLOT2 = 0x8,
 32	DS_REGION_SLOT2_EX = 0x9,
 33	DS_REGION_SLOT2_SRAM = 0xA,
 34	DS9_REGION_BIOS = 0xFF,
 35};
 36
 37enum DSMemoryBase {
 38	DS7_BASE_BIOS = 0x00000000,
 39	DS9_BASE_ITCM = 0x00000000,
 40	DS_BASE_RAM = 0x02000000,
 41	DS9_BASE_DTCM = 0x027C0000,
 42	DS_BASE_WORKING_RAM = 0x03000000,
 43	DS7_BASE_WORKING_RAM = 0x03800000,
 44	DS_BASE_IO = 0x04000000,
 45	DS9_BASE_PALETTE_RAM = 0x05000000,
 46	DS_BASE_VRAM = 0x06000000,
 47	DS9_BASE_OAM = 0x07000000,
 48	DS_BASE_SLOT2 = 0x08000000,
 49	DS_BASE_SLOT2_EX = 0x09000000,
 50	DS9_BASE_BIOS = 0xFFFF0000,
 51};
 52
 53enum {
 54	DS9_SIZE_ITCM = 0x00008000,
 55	DS9_SIZE_DTCM = 0x00004000,
 56	DS7_SIZE_BIOS = 0x00004000,
 57	DS9_SIZE_BIOS = 0x00008000,
 58	DS_SIZE_RAM = 0x00400000,
 59	DS_SIZE_VRAM = 0x000A4000,
 60	DS_SIZE_WORKING_RAM = 0x00008000,
 61	DS7_SIZE_WORKING_RAM = 0x00010000,
 62	DS9_SIZE_PALETTE_RAM = 0x00000800,
 63	DS9_SIZE_OAM = 0x00000800,
 64	DS_SIZE_SLOT2 = 0x02000000,
 65	DS_SIZE_SLOT2_SRAM = 0x00010000,
 66};
 67
 68enum {
 69	DS_OFFSET_MASK = 0x00FFFFFF,
 70	DS_BASE_OFFSET = 24,
 71	DS_VRAM_OFFSET = 14
 72};
 73
 74mLOG_DECLARE_CATEGORY(DS_MEM);
 75
 76struct DSMemory {
 77	uint32_t* bios7;
 78	uint32_t* bios9;
 79	uint32_t* itcm;
 80	uint32_t* dtcm;
 81	uint32_t* ram;
 82	uint32_t* wram;
 83	uint32_t* wramBase7;
 84	uint32_t* wramBase9;
 85	uint32_t* wram7;
 86	uint32_t* rom;
 87	uint16_t io7[DS7_REG_MAX >> 1];
 88	uint16_t io9[DS9_REG_MAX >> 1];
 89	struct DSSlot1 slot1;
 90	struct DSSPIBus spiBus;
 91
 92	uint16_t vramMirror[9][0x40];
 93	uint16_t vramMode[9][8];
 94	uint16_t* vramBank[9];
 95
 96	size_t romSize;
 97	size_t wramSize7;
 98	size_t wramSize9;
 99
100	uint32_t dtcmBase;
101	uint32_t dtcmSize;
102	uint32_t itcmSize;
103
104	bool slot1Owner;
105	bool slot2Owner;
106};
107
108struct DSCoreMemory {
109	uint16_t* io;
110	int activeRegion;
111
112	char waitstatesSeq32[256];
113	char waitstatesSeq16[256];
114	char waitstatesNonseq32[256];
115	char waitstatesNonseq16[256];
116	char waitstatesPrefetchSeq32[16];
117	char waitstatesPrefetchSeq16[16];
118	char waitstatesPrefetchNonseq32[16];
119	char waitstatesPrefetchNonseq16[16];
120
121	struct GBADMA dma[4];
122	struct mTimingEvent dmaEvent;
123	int activeDMA;
124	bool slot1Access;
125	bool slot2Access;
126};
127
128struct DS;
129void DSMemoryInit(struct DS* ds);
130void DSMemoryDeinit(struct DS* ds);
131
132void DSMemoryReset(struct DS* ds);
133
134uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
135uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
136uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
137
138void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
139void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
140void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
141
142uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
143                         int* cycleCounter);
144uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
145                          int* cycleCounter);
146
147uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
148uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
149uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
150
151void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
152void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
153void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
154
155uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
156                         int* cycleCounter);
157uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
158                          int* cycleCounter);
159
160void DSConfigureWRAM(struct DSMemory*, uint8_t config);
161void DSConfigureExternalMemory(struct DS*, uint16_t config);
162
163#endif