src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 ARM_STUB;
28}
29
30static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
31 int rm = opcode & 0x0000000F;
32 int immediate = (opcode & 0x00000F80) >> 7;
33 if (immediate) {
34 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
35 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
39 }
40}
41
42static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
43 int rm = opcode & 0x0000000F;
44 ARM_STUB;
45}
46
47static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
48 int rm = opcode & 0x0000000F;
49 int immediate = (opcode & 0x00000F80) >> 7;
50 if (immediate) {
51 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
52 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
53 } else {
54 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
55 cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
56 }
57}
58
59static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
60 int rm = opcode & 0x0000000F;
61 ARM_STUB;
62}
63
64static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int immediate = (opcode & 0x00000F80) >> 7;
67 if (immediate) {
68 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
69 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
70 } else {
71 // RRX
72 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
73 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
74 }
75}
76
77static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
78 int rm = opcode & 0x0000000F;
79 int rs = (opcode >> 8) & 0x0000000F;
80 ++cpu->cycles;
81 int shift = cpu->gprs[rs];
82 if (rs == ARM_PC) {
83 shift += 4;
84 }
85 shift &= 0xFF;
86 int shiftVal = cpu->gprs[rm];
87 if (rm == ARM_PC) {
88 shiftVal += 4;
89 }
90 int rotate = shift & 0x1F;
91 if (!shift) {
92 cpu->shifterOperand = shiftVal;
93 cpu->shifterCarryOut = cpu->cpsr.c;
94 } else if (rotate) {
95 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
96 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
97 } else {
98 cpu->shifterOperand = shiftVal;
99 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
100 }
101}
102
103static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
104 int rotate = (opcode & 0x00000F00) >> 7;
105 int immediate = opcode & 0x000000FF;
106 if (!rotate) {
107 cpu->shifterOperand = immediate;
108 cpu->shifterCarryOut = cpu->cpsr.c;
109 } else {
110 cpu->shifterOperand = ARM_ROR(immediate, rotate);
111 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
112 }
113}
114
115static const ARMInstruction _armTable[0x1000];
116
117static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
118 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
119 *opcodeOut = opcode;
120 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
121}
122
123void ARMStep(struct ARMCore* cpu) {
124 // TODO
125 uint32_t opcode;
126 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
127 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
128
129 int condition = opcode >> 28;
130 if (condition == 0xE) {
131 instruction(cpu, opcode);
132 return;
133 } else {
134 switch (condition) {
135 case 0x0:
136 if (!ARM_COND_EQ) {
137 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
138 return;
139 }
140 break;
141 case 0x1:
142 if (!ARM_COND_NE) {
143 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
144 return;
145 }
146 break;
147 case 0x2:
148 if (!ARM_COND_CS) {
149 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
150 return;
151 }
152 break;
153 case 0x3:
154 if (!ARM_COND_CC) {
155 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
156 return;
157 }
158 break;
159 case 0x4:
160 if (!ARM_COND_MI) {
161 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
162 return;
163 }
164 break;
165 case 0x5:
166 if (!ARM_COND_PL) {
167 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
168 return;
169 }
170 break;
171 case 0x6:
172 if (!ARM_COND_VS) {
173 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
174 return;
175 }
176 break;
177 case 0x7:
178 if (!ARM_COND_VC) {
179 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
180 return;
181 }
182 break;
183 case 0x8:
184 if (!ARM_COND_HI) {
185 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
186 return;
187 }
188 break;
189 case 0x9:
190 if (!ARM_COND_LS) {
191 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
192 return;
193 }
194 break;
195 case 0xA:
196 if (!ARM_COND_GE) {
197 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
198 return;
199 }
200 break;
201 case 0xB:
202 if (!ARM_COND_LT) {
203 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
204 return;
205 }
206 break;
207 case 0xC:
208 if (!ARM_COND_GT) {
209 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
210 return;
211 }
212 break;
213 case 0xD:
214 if (!ARM_COND_LE) {
215 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
216 return;
217 }
218 break;
219 default:
220 break;
221 }
222 }
223 instruction(cpu, opcode);
224}
225
226// Instruction definitions
227// Beware pre-processor antics
228
229#define ARM_ADDITION_S(M, N, D) \
230 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
231 cpu->cpsr = cpu->spsr; \
232 _ARMReadCPSR(cpu); \
233 } else { \
234 cpu->cpsr.n = ARM_SIGN(D); \
235 cpu->cpsr.z = !(D); \
236 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
237 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
238 }
239
240#define ARM_SUBTRACTION_S(M, N, D) \
241 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
242 cpu->cpsr = cpu->spsr; \
243 _ARMReadCPSR(cpu); \
244 } else { \
245 cpu->cpsr.n = ARM_SIGN(D); \
246 cpu->cpsr.z = !(D); \
247 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
248 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
249 }
250
251#define ARM_NEUTRAL_S(M, N, D) \
252 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
253 cpu->cpsr = cpu->spsr; \
254 _ARMReadCPSR(cpu); \
255 } else { \
256 cpu->cpsr.n = ARM_SIGN(D); \
257 cpu->cpsr.z = !(D); \
258 cpu->cpsr.c = !!cpu->shifterCarryOut; \
259 }
260
261#define ARM_NEUTRAL_HI_S(DLO, DHI) \
262 cpu->cpsr.n = ARM_SIGN(DHI); \
263 cpu->cpsr.z = !((DHI) | (DLO));
264
265#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
266#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
267#define ADDR_MODE_2_ADDRESS (address)
268#define ADDR_MODE_2_RN (cpu->gprs[rn])
269#define ADDR_MODE_2_RM (cpu->gprs[rm])
270#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
271#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
272#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
273#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
274#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
275#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
276#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
277
278#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
279#define ADDR_MODE_3_RN ADDR_MODE_2_RN
280#define ADDR_MODE_3_RM ADDR_MODE_2_RM
281#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
282#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
283#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
284
285#define ARM_LOAD_POST_BODY \
286 if (rd == ARM_PC) { \
287 ARM_WRITE_PC; \
288 }
289
290#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
291 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
292 BODY; \
293 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
294 }
295
296#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
297 DEFINE_INSTRUCTION_ARM(NAME, \
298 int rd = (opcode >> 12) & 0xF; \
299 int rn = (opcode >> 16) & 0xF; \
300 UNUSED(rn); \
301 SHIFTER(cpu, opcode); \
302 BODY; \
303 S_BODY; \
304 if (rd == ARM_PC) { \
305 if (cpu->executionMode == MODE_ARM) { \
306 ARM_WRITE_PC; \
307 } else { \
308 THUMB_WRITE_PC; \
309 } \
310 })
311
312#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
331
332#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
335 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
342
343#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
344 DEFINE_INSTRUCTION_ARM(NAME, \
345 int rd = (opcode >> 12) & 0xF; \
346 int rdHi = (opcode >> 16) & 0xF; \
347 int rs = (opcode >> 8) & 0xF; \
348 int rm = opcode & 0xF; \
349 UNUSED(rdHi); \
350 BODY; \
351 S_BODY; \
352 if (rd == ARM_PC) { \
353 ARM_WRITE_PC; \
354 })
355
356#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
357 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
358 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
359
360#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
361 DEFINE_INSTRUCTION_ARM(NAME, \
362 uint32_t address; \
363 int rn = (opcode >> 16) & 0xF; \
364 int rd = (opcode >> 12) & 0xF; \
365 int rm = opcode & 0xF; \
366 UNUSED(rm); \
367 address = ADDRESS; \
368 BODY; \
369 WRITEBACK;)
370
371#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
378
379#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
390
391#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
404
405#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
408
409#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
410 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
411 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
412 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
413 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
416
417#define ARM_MS_PRE \
418 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
419 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
420
421#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
422
423#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
424#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
425#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
426#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
427#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
428#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
429#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
430#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
431
432#define ARM_M_INCREMENT(BODY) \
433 for (m = rs, i = 0; m; m >>= 1, ++i) { \
434 if (m & 1) { \
435 BODY; \
436 addr += 4; \
437 } \
438 }
439
440#define ARM_M_DECREMENT(BODY) \
441 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
442 if (rs & m) { \
443 BODY; \
444 addr -= 4; \
445 } \
446 }
447
448#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
449 DEFINE_INSTRUCTION_ARM(NAME, \
450 int rn = (opcode >> 16) & 0xF; \
451 int rs = opcode & 0x0000FFFF; \
452 int m; \
453 int i; \
454 ADDRESS; \
455 S_PRE; \
456 LOOP(BODY); \
457 S_POST; \
458 WRITEBACK; \
459 POST_BODY;)
460
461
462#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
464 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
465 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
469 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
470 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
471 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
472 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
473 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
474 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
475 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
476 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
477 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
478 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
479
480// Begin ALU definitions
481
482DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
483 int32_t n = cpu->gprs[rn];
484 cpu->gprs[rd] = n + cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
487 int32_t n = cpu->gprs[rn];
488 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
489 cpu->gprs[rd] = n + shifterOperand;)
490
491DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
492 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
493
494DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
495 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
496
497DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
498 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
499
500DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
501 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
502
503DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
504 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
505
506DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
507 cpu->gprs[rd] = cpu->shifterOperand;)
508
509DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
510 cpu->gprs[rd] = ~cpu->shifterOperand;)
511
512DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
513 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
514
515DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
516 int32_t n = cpu->gprs[rn];
517 cpu->gprs[rd] = cpu->shifterOperand - n;)
518
519DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
520 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
521 cpu->gprs[rd] = cpu->shifterOperand - n;)
522
523DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
524 int32_t n = cpu->gprs[rn];
525 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
526 cpu->gprs[rd] = n - shifterOperand;)
527
528DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
529 int32_t n = cpu->gprs[rn];
530 cpu->gprs[rd] = n - cpu->shifterOperand;)
531
532DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
533 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
534
535DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
536 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
537
538// End ALU definitions
539
540// Begin multiply definitions
541
542DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
543DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
544DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
545DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
546DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
547 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
548 cpu->gprs[rd] = d;
549 cpu->gprs[rdHi] = d >> 32;,
550 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
551DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
552DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
553DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
554 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
555 cpu->gprs[rd] = d;
556 cpu->gprs[rdHi] = d >> 32;,
557 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
558
559// End multiply definitions
560
561// Begin load/store definitions
562
563DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;)
564DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;)
565DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;)
566DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;)
567DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;)
568DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
569DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
570DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
571
572DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
573 enum PrivilegeMode priv = cpu->privilegeMode;
574 ARMSetPrivilegeMode(cpu, MODE_USER);
575 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
576 ARMSetPrivilegeMode(cpu, priv);
577 ARM_LOAD_POST_BODY;)
578
579DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
580 enum PrivilegeMode priv = cpu->privilegeMode;
581 ARMSetPrivilegeMode(cpu, MODE_USER);
582 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
583 ARMSetPrivilegeMode(cpu, priv);
584 ARM_LOAD_POST_BODY;)
585
586DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
587 enum PrivilegeMode priv = cpu->privilegeMode;
588 ARMSetPrivilegeMode(cpu, MODE_USER);
589 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
590 ARMSetPrivilegeMode(cpu, priv);)
591
592DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
593 enum PrivilegeMode priv = cpu->privilegeMode;
594 ARMSetPrivilegeMode(cpu, MODE_USER);
595 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
596 ARMSetPrivilegeMode(cpu, priv);)
597
598DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
599 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr);,
600 if (rs & 0x8000) {
601 ARM_WRITE_PC;
602 })
603
604DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i]);, )
605
606DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
607DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
608
609// End load/store definitions
610
611// Begin branch definitions
612
613DEFINE_INSTRUCTION_ARM(B,
614 int32_t offset = opcode << 8;
615 offset >>= 6;
616 cpu->gprs[ARM_PC] += offset;
617 ARM_WRITE_PC;)
618
619DEFINE_INSTRUCTION_ARM(BL,
620 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
621 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
622 cpu->gprs[ARM_PC] += immediate >> 6;
623 ARM_WRITE_PC;)
624
625DEFINE_INSTRUCTION_ARM(BX,
626 int rm = opcode & 0x0000000F;
627 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
628 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
629 if (cpu->executionMode == MODE_THUMB) {
630 THUMB_WRITE_PC;
631 } else {
632 ARM_WRITE_PC;
633 })
634
635// End branch definitions
636
637// Begin miscellaneous definitions
638
639DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
640DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
641
642DEFINE_INSTRUCTION_ARM(MSR,
643 int c = opcode & 0x00010000;
644 int f = opcode & 0x00080000;
645 int32_t operand = cpu->gprs[opcode & 0x0000000F];
646 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
647 if (mask & PSR_USER_MASK) {
648 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
649 }
650 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
651 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
652 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
653 })
654
655DEFINE_INSTRUCTION_ARM(MSRR,
656 int c = opcode & 0x00010000;
657 int f = opcode & 0x00080000;
658 int32_t operand = cpu->gprs[opcode & 0x0000000F];
659 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
660 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
661 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
662
663DEFINE_INSTRUCTION_ARM(MRS, \
664 int rd = (opcode >> 12) & 0xF; \
665 cpu->gprs[rd] = cpu->cpsr.packed;)
666
667DEFINE_INSTRUCTION_ARM(MRSR, \
668 int rd = (opcode >> 12) & 0xF; \
669 cpu->gprs[rd] = cpu->spsr.packed;)
670
671DEFINE_INSTRUCTION_ARM(MSRI,
672 int c = opcode & 0x00010000;
673 int f = opcode & 0x00080000;
674 int rotate = (opcode & 0x00000F00) >> 8;
675 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
676 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
677 if (mask & PSR_USER_MASK) {
678 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
679 }
680 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
681 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
682 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
683 })
684
685DEFINE_INSTRUCTION_ARM(MSRRI,
686 int c = opcode & 0x00010000;
687 int f = opcode & 0x00080000;
688 int rotate = (opcode & 0x00000F00) >> 8;
689 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
690 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
691 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
692 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
693
694DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
695
696#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
697 EMITTER ## NAME
698
699#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
700 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
701 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
702
703#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
704 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
705 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
706 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
707 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
708 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
709 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
710 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
711 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
712 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
713 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
714 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
715 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
716 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
717 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
718 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
719 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
720
721#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
722 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
723 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
724
725#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
726 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
727 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
728 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
729 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
730 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
731 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
732 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
733 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
734 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
735 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
736 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
737 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
738 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
739 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
740 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
741 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
742
743#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
744 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
745 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
746
747#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
748 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
749
750// TODO: Support coprocessors
751#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
752 DO_8(0), \
753 DO_8(0)
754
755#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
756 DO_8(DO_8(DO_INTERLACE(0, 0))), \
757 DO_8(DO_8(DO_INTERLACE(0, 0)))
758
759#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
760 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
761
762#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
763 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
764 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
765 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
766 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
767 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
768 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
769 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
770 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
771 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
772 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
773 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
774 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
775 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
776 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
777 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
778 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
779 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
780 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
781 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
782 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
783 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
784 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
785 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
786 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
787 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
788 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
789 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
790 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
791 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
792 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
793 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
794 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
795 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
796 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
797 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
798 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
799 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
800 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
801 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
802 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
803 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
804 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
805 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
806 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
807 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
808 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
809 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
812 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
822 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
823 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
829 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
831 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
832 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
833 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
834 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
846 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
847 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
848 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
849 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
850 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
851 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
852 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
853 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
854 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
855 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
856 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
857 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
858 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
859 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
860 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
861 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
862 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
863 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
864 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
865 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
866 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
867 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
868 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
869 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
870 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
871 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
872 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
873 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
874 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
875 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
876 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
877 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
878 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
879 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
880 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
881 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
882 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
883 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
884 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
885 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
886 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
887 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
888 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
889 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
890 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
891 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
892 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
893 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
894 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
895 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
896 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
897 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
898 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
899 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
900 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
901 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
902 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
903 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
904 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
905 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
906 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
907 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
908 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
909 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
910 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
911 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
912 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
913 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
914 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
915 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
916 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
917 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
918 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
919 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
920 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
921 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
922 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
923 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
924 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
925 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
926 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
927 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
928 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
929 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
930 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
931 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
932 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
933 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
934 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
935 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
936 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
937 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
938 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
939 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
940 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
941 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
942 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
943 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
944 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
945 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
946 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
947 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
948 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
949 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
950 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
951 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
952 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
953 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
954 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
955 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
956 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
957 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
958 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
959 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
960 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
961 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
962 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
963 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
964 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
965 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
966 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
967 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
968 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
969 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
970 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
971 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
972 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
973 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
974 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
975 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
976 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
977 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
978 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
979 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
980 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
981 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
982 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
983 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
984 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
985 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
986 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
987 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
988 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
989 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
990 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
991 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
992 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
993 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
994 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
995 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
996 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
997 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
998 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
999 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1000 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1001 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1002 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1003 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1004 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1005 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1006 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1007 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1008 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1009 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1010 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1011 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1012 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1013 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1014 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1015 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1016 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1017 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1018 DECLARE_ARM_SWI_BLOCK(EMITTER)
1019
1020static const ARMInstruction _armTable[0x1000] = {
1021 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1022};