src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.hw.p = gba;
54
55 int i;
56 for (i = 0; i < 16; ++i) {
57 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
60 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
61 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
64 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
65 }
66 for (; i < 256; ++i) {
67 gba->memory.waitstatesNonseq16[i] = 0;
68 gba->memory.waitstatesSeq16[i] = 0;
69 gba->memory.waitstatesNonseq32[i] = 0;
70 gba->memory.waitstatesSeq32[i] = 0;
71 }
72
73 gba->memory.activeRegion = -1;
74 cpu->memory.activeRegion = 0;
75 cpu->memory.activeMask = 0;
76 cpu->memory.setActiveRegion = GBASetActiveRegion;
77 cpu->memory.activeSeqCycles32 = 0;
78 cpu->memory.activeSeqCycles16 = 0;
79 cpu->memory.activeNonseqCycles32 = 0;
80 cpu->memory.activeNonseqCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 if (!gba->memory.wram || !gba->memory.iwram) {
117 GBAMemoryDeinit(gba);
118 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
119 }
120}
121
122static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
123 struct ARMInstructionInfo info;
124 uint32_t nextAddress = address;
125 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
126 if (cpu->executionMode == MODE_THUMB) {
127 while (true) {
128 uint16_t opcode;
129 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
130 ARMDecodeThumb(opcode, &info);
131 switch (info.branchType) {
132 case ARM_BRANCH_NONE:
133 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
134 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
135 gba->idleDetectionStep = -1;
136 return;
137 }
138 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
139 uint32_t offset = 0;
140 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
141 offset = info.memory.offset.immediate;
142 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
143 int reg = info.memory.offset.reg;
144 if (gba->cachedRegisters[reg]) {
145 gba->idleDetectionStep = -1;
146 return;
147 }
148 offset = gba->cachedRegisters[reg];
149 }
150 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
151 loadAddress -= offset;
152 } else {
153 loadAddress += offset;
154 }
155 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
156 gba->idleDetectionStep = -1;
157 return;
158 }
159 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
160 gba->taintedRegisters[info.op1.reg] = true;
161 } else {
162 switch (info.memory.width) {
163 case 1:
164 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
165 break;
166 case 2:
167 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
168 break;
169 case 4:
170 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
171 break;
172 }
173 }
174 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
175 gba->taintedRegisters[info.op1.reg] = true;
176 }
177 nextAddress += WORD_SIZE_THUMB;
178 break;
179 case ARM_BRANCH:
180 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
181 gba->idleLoop = address;
182 gba->idleOptimization = IDLE_LOOP_REMOVE;
183 }
184 gba->idleDetectionStep = -1;
185 return;
186 default:
187 gba->idleDetectionStep = -1;
188 return;
189 }
190 }
191 } else {
192 gba->idleDetectionStep = -1;
193 }
194}
195
196static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
197 struct GBA* gba = (struct GBA*) cpu->master;
198 struct GBAMemory* memory = &gba->memory;
199
200 int newRegion = address >> BASE_OFFSET;
201 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
202 if (address == gba->idleLoop) {
203 if (gba->haltPending) {
204 gba->haltPending = false;
205 GBAHalt(gba);
206 } else {
207 gba->haltPending = true;
208 }
209 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
210 if (address == gba->lastJump) {
211 switch (gba->idleDetectionStep) {
212 case 0:
213 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
214 ++gba->idleDetectionStep;
215 break;
216 case 1:
217 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
218 gba->idleDetectionStep = -1;
219 ++gba->idleDetectionFailures;
220 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
221 gba->idleOptimization = IDLE_LOOP_IGNORE;
222 }
223 break;
224 }
225 _analyzeForIdleLoop(gba, cpu, address);
226 break;
227 }
228 } else {
229 gba->idleDetectionStep = 0;
230 }
231 }
232 }
233
234 gba->lastJump = address;
235 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
236 return;
237 }
238
239 if (memory->activeRegion == REGION_BIOS) {
240 memory->biosPrefetch = cpu->prefetch[1];
241 }
242 memory->activeRegion = newRegion;
243 switch (newRegion) {
244 case REGION_BIOS:
245 cpu->memory.activeRegion = memory->bios;
246 cpu->memory.activeMask = SIZE_BIOS - 1;
247 break;
248 case REGION_WORKING_RAM:
249 cpu->memory.activeRegion = memory->wram;
250 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
251 break;
252 case REGION_WORKING_IRAM:
253 cpu->memory.activeRegion = memory->iwram;
254 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
255 break;
256 case REGION_VRAM:
257 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
258 cpu->memory.activeMask = 0x0000FFFF;
259 break;
260 case REGION_CART0:
261 case REGION_CART0_EX:
262 case REGION_CART1:
263 case REGION_CART1_EX:
264 case REGION_CART2:
265 case REGION_CART2_EX:
266 cpu->memory.activeRegion = memory->rom;
267 cpu->memory.activeMask = SIZE_CART0 - 1;
268 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
269 break;
270 }
271 // Fall through
272 default:
273 memory->activeRegion = -1;
274 cpu->memory.activeRegion = _deadbeef;
275 cpu->memory.activeMask = 0;
276 if (!gba->yankedRomSize) {
277 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
278 }
279 return;
280 }
281 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
282 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
283 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
284 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
285}
286
287#define LOAD_BAD \
288 if (gba->performingDMA) { \
289 value = gba->bus; \
290 } else { \
291 value = cpu->prefetch[1]; \
292 if (cpu->executionMode == MODE_THUMB) { \
293 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
294 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
295 case REGION_BIOS: \
296 case REGION_OAM: \
297 /* This isn't right half the time, but we don't have $+6 handy */ \
298 value <<= 16; \
299 value |= cpu->prefetch[0]; \
300 break; \
301 case REGION_WORKING_IRAM: \
302 /* This doesn't handle prefetch clobbering */ \
303 if (cpu->gprs[ARM_PC] & 2) { \
304 value |= cpu->prefetch[0] << 16; \
305 } else { \
306 value <<= 16; \
307 value |= cpu->prefetch[0]; \
308 } \
309 default: \
310 value |= value << 16; \
311 } \
312 } \
313 }
314
315#define LOAD_BIOS \
316 if (address < SIZE_BIOS) { \
317 if (memory->activeRegion == REGION_BIOS) { \
318 LOAD_32(value, address, memory->bios); \
319 } else { \
320 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
321 value = memory->biosPrefetch; \
322 } \
323 } else { \
324 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
325 LOAD_BAD; \
326 }
327
328#define LOAD_WORKING_RAM \
329 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
330 wait += waitstatesRegion[REGION_WORKING_RAM];
331
332#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
333#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
334
335#define LOAD_PALETTE_RAM \
336 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
337 wait += waitstatesRegion[REGION_PALETTE_RAM];
338
339#define LOAD_VRAM \
340 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
341 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
342 } else { \
343 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
344 } \
345 wait += waitstatesRegion[REGION_VRAM];
346
347#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
348
349#define LOAD_CART \
350 wait += waitstatesRegion[address >> BASE_OFFSET]; \
351 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
352 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
353 } else { \
354 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
355 value = (address >> 1) & 0xFFFF; \
356 value |= ((address + 2) >> 1) << 16; \
357 }
358
359#define LOAD_SRAM \
360 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
361 value = GBALoad8(cpu, address, 0); \
362 value |= value << 8; \
363 value |= value << 16;
364
365uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
366 struct GBA* gba = (struct GBA*) cpu->master;
367 struct GBAMemory* memory = &gba->memory;
368 uint32_t value = 0;
369 int wait = 0;
370 char* waitstatesRegion = memory->waitstatesNonseq32;
371
372 switch (address >> BASE_OFFSET) {
373 case REGION_BIOS:
374 LOAD_BIOS;
375 break;
376 case REGION_WORKING_RAM:
377 LOAD_WORKING_RAM;
378 break;
379 case REGION_WORKING_IRAM:
380 LOAD_WORKING_IRAM;
381 break;
382 case REGION_IO:
383 LOAD_IO;
384 break;
385 case REGION_PALETTE_RAM:
386 LOAD_PALETTE_RAM;
387 break;
388 case REGION_VRAM:
389 LOAD_VRAM;
390 break;
391 case REGION_OAM:
392 LOAD_OAM;
393 break;
394 case REGION_CART0:
395 case REGION_CART0_EX:
396 case REGION_CART1:
397 case REGION_CART1_EX:
398 case REGION_CART2:
399 case REGION_CART2_EX:
400 LOAD_CART;
401 break;
402 case REGION_CART_SRAM:
403 case REGION_CART_SRAM_MIRROR:
404 LOAD_SRAM;
405 break;
406 default:
407 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
408 LOAD_BAD;
409 break;
410 }
411
412 if (cycleCounter) {
413 wait += 2;
414 if (address >> BASE_OFFSET < REGION_CART0) {
415 wait = GBAMemoryStall(cpu, wait);
416 }
417 *cycleCounter += wait;
418 }
419 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
420 int rotate = (address & 3) << 3;
421 return ROR(value, rotate);
422}
423
424uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
425 struct GBA* gba = (struct GBA*) cpu->master;
426 struct GBAMemory* memory = &gba->memory;
427 uint32_t value = 0;
428 int wait = 0;
429
430 switch (address >> BASE_OFFSET) {
431 case REGION_BIOS:
432 if (address < SIZE_BIOS) {
433 if (memory->activeRegion == REGION_BIOS) {
434 LOAD_16(value, address, memory->bios);
435 } else {
436 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
437 LOAD_16(value, address & 2, &memory->biosPrefetch);
438 }
439 } else {
440 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
441 LOAD_BAD;
442 uint32_t v2 = value;
443 LOAD_16(value, address & 2, &v2);
444 }
445 break;
446 case REGION_WORKING_RAM:
447 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
448 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
449 break;
450 case REGION_WORKING_IRAM:
451 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
452 break;
453 case REGION_IO:
454 value = GBAIORead(gba, address & (SIZE_IO - 2));
455 break;
456 case REGION_PALETTE_RAM:
457 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
458 break;
459 case REGION_VRAM:
460 if ((address & 0x0001FFFF) < SIZE_VRAM) {
461 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
462 } else {
463 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
464 }
465 break;
466 case REGION_OAM:
467 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
468 break;
469 case REGION_CART0:
470 case REGION_CART0_EX:
471 case REGION_CART1:
472 case REGION_CART1_EX:
473 case REGION_CART2:
474 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
475 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
476 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
477 } else {
478 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
479 value = (address >> 1) & 0xFFFF; \
480 }
481 break;
482 case REGION_CART2_EX:
483 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
484 if (memory->savedata.type == SAVEDATA_EEPROM) {
485 value = GBASavedataReadEEPROM(&memory->savedata);
486 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
487 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
488 } else {
489 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
490 value = (address >> 1) & 0xFFFF; \
491 }
492 break;
493 case REGION_CART_SRAM:
494 case REGION_CART_SRAM_MIRROR:
495 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
496 value = GBALoad8(cpu, address, 0);
497 value |= value << 8;
498 break;
499 default:
500 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
501 LOAD_BAD;
502 uint32_t v2 = value;
503 LOAD_16(value, address & 2, &v2);
504 break;
505 }
506
507 if (cycleCounter) {
508 wait += 2;
509 if (address >> BASE_OFFSET < REGION_CART0) {
510 wait = GBAMemoryStall(cpu, wait);
511 }
512 *cycleCounter += wait;
513 }
514 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
515 int rotate = (address & 1) << 3;
516 return ROR(value, rotate);
517}
518
519uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
520 struct GBA* gba = (struct GBA*) cpu->master;
521 struct GBAMemory* memory = &gba->memory;
522 uint32_t value = 0;
523 int wait = 0;
524
525 switch (address >> BASE_OFFSET) {
526 case REGION_BIOS:
527 if (address < SIZE_BIOS) {
528 if (memory->activeRegion == REGION_BIOS) {
529 value = ((uint8_t*) memory->bios)[address];
530 } else {
531 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
532 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
533 }
534 } else {
535 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
536 LOAD_BAD;
537 value = ((uint8_t*) &value)[address & 3];
538 }
539 break;
540 case REGION_WORKING_RAM:
541 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
542 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
543 break;
544 case REGION_WORKING_IRAM:
545 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
546 break;
547 case REGION_IO:
548 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
549 break;
550 case REGION_PALETTE_RAM:
551 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
552 break;
553 case REGION_VRAM:
554 if ((address & 0x0001FFFF) < SIZE_VRAM) {
555 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
556 } else {
557 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
558 }
559 break;
560 case REGION_OAM:
561 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
562 break;
563 case REGION_CART0:
564 case REGION_CART0_EX:
565 case REGION_CART1:
566 case REGION_CART1_EX:
567 case REGION_CART2:
568 case REGION_CART2_EX:
569 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
570 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
571 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
572 } else {
573 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
574 value = (address >> 1) & 0xFF; \
575 }
576 break;
577 case REGION_CART_SRAM:
578 case REGION_CART_SRAM_MIRROR:
579 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
580 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
581 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
582 GBASavedataInitSRAM(&memory->savedata);
583 }
584 if (memory->savedata.type == SAVEDATA_SRAM) {
585 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
586 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
587 value = GBASavedataReadFlash(&memory->savedata, address);
588 } else if (memory->hw.devices & HW_TILT) {
589 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
590 } else {
591 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
592 value = 0xFF;
593 }
594 value &= 0xFF;
595 break;
596 default:
597 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
598 LOAD_BAD;
599 value = ((uint8_t*) &value)[address & 3];
600 break;
601 }
602
603 if (cycleCounter) {
604 wait += 2;
605 if (address >> BASE_OFFSET < REGION_CART0) {
606 wait = GBAMemoryStall(cpu, wait);
607 }
608 *cycleCounter += wait;
609 }
610 return value;
611}
612
613#define STORE_WORKING_RAM \
614 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
615 wait += waitstatesRegion[REGION_WORKING_RAM];
616
617#define STORE_WORKING_IRAM \
618 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
619
620#define STORE_IO \
621 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
622
623#define STORE_PALETTE_RAM \
624 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
625 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
626 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
627 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
628
629#define STORE_VRAM \
630 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
631 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
632 } else { \
633 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
634 } \
635 wait += waitstatesRegion[REGION_VRAM];
636
637#define STORE_OAM \
638 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
639 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
640 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
641
642#define STORE_CART \
643 wait += waitstatesRegion[address >> BASE_OFFSET]; \
644 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
645
646#define STORE_SRAM \
647 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
648
649#define STORE_BAD \
650 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
651
652void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
653 struct GBA* gba = (struct GBA*) cpu->master;
654 struct GBAMemory* memory = &gba->memory;
655 int wait = 0;
656 char* waitstatesRegion = memory->waitstatesNonseq32;
657
658 switch (address >> BASE_OFFSET) {
659 case REGION_WORKING_RAM:
660 STORE_WORKING_RAM;
661 break;
662 case REGION_WORKING_IRAM:
663 STORE_WORKING_IRAM
664 break;
665 case REGION_IO:
666 STORE_IO;
667 break;
668 case REGION_PALETTE_RAM:
669 STORE_PALETTE_RAM;
670 break;
671 case REGION_VRAM:
672 STORE_VRAM;
673 break;
674 case REGION_OAM:
675 STORE_OAM;
676 break;
677 case REGION_CART0:
678 case REGION_CART0_EX:
679 case REGION_CART1:
680 case REGION_CART1_EX:
681 case REGION_CART2:
682 case REGION_CART2_EX:
683 STORE_CART;
684 break;
685 case REGION_CART_SRAM:
686 case REGION_CART_SRAM_MIRROR:
687 STORE_SRAM;
688 break;
689 default:
690 STORE_BAD;
691 break;
692 }
693
694 if (cycleCounter) {
695 ++wait;
696 if (address >> BASE_OFFSET < REGION_CART0) {
697 wait = GBAMemoryStall(cpu, wait);
698 }
699 *cycleCounter += wait;
700 }
701}
702
703void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
704 struct GBA* gba = (struct GBA*) cpu->master;
705 struct GBAMemory* memory = &gba->memory;
706 int wait = 0;
707
708 switch (address >> BASE_OFFSET) {
709 case REGION_WORKING_RAM:
710 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
711 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
712 break;
713 case REGION_WORKING_IRAM:
714 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
715 break;
716 case REGION_IO:
717 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
718 break;
719 case REGION_PALETTE_RAM:
720 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
721 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
722 break;
723 case REGION_VRAM:
724 if ((address & 0x0001FFFF) < SIZE_VRAM) {
725 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
726 } else {
727 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
728 }
729 break;
730 case REGION_OAM:
731 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
732 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
733 break;
734 case REGION_CART0:
735 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
736 uint32_t reg = address & 0xFFFFFE;
737 GBAHardwareGPIOWrite(&memory->hw, reg, value);
738 } else {
739 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
740 }
741 break;
742 case REGION_CART2_EX:
743 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
744 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
745 GBASavedataInitEEPROM(&memory->savedata);
746 }
747 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
748 break;
749 case REGION_CART_SRAM:
750 case REGION_CART_SRAM_MIRROR:
751 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
752 break;
753 default:
754 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
755 break;
756 }
757
758 if (cycleCounter) {
759 ++wait;
760 if (address >> BASE_OFFSET < REGION_CART0) {
761 wait = GBAMemoryStall(cpu, wait);
762 }
763 *cycleCounter += wait;
764 }
765}
766
767void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
768 struct GBA* gba = (struct GBA*) cpu->master;
769 struct GBAMemory* memory = &gba->memory;
770 int wait = 0;
771
772 switch (address >> BASE_OFFSET) {
773 case REGION_WORKING_RAM:
774 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
775 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
776 break;
777 case REGION_WORKING_IRAM:
778 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
779 break;
780 case REGION_IO:
781 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
782 break;
783 case REGION_PALETTE_RAM:
784 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
785 break;
786 case REGION_VRAM:
787 if (address >= 0x06018000) {
788 // TODO: check BG mode
789 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
790 break;
791 }
792 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
793 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
794 break;
795 case REGION_OAM:
796 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
797 break;
798 case REGION_CART0:
799 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
800 break;
801 case REGION_CART_SRAM:
802 case REGION_CART_SRAM_MIRROR:
803 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
804 if (address == SAVEDATA_FLASH_BASE) {
805 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
806 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
807 } else {
808 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
809 GBASavedataInitSRAM(&memory->savedata);
810 }
811 }
812 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
813 GBASavedataWriteFlash(&memory->savedata, address, value);
814 } else if (memory->savedata.type == SAVEDATA_SRAM) {
815 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
816 } else if (memory->hw.devices & HW_TILT) {
817 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
818 } else {
819 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
820 }
821 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
822 break;
823 default:
824 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
825 break;
826 }
827
828 if (cycleCounter) {
829 ++wait;
830 if (address >> BASE_OFFSET < REGION_CART0) {
831 wait = GBAMemoryStall(cpu, wait);
832 }
833 *cycleCounter += wait;
834 }
835}
836
837void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
838 struct GBA* gba = (struct GBA*) cpu->master;
839 struct GBAMemory* memory = &gba->memory;
840 int32_t oldValue = -1;
841
842 switch (address >> BASE_OFFSET) {
843 case REGION_WORKING_RAM:
844 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
845 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
846 break;
847 case REGION_WORKING_IRAM:
848 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
849 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
850 break;
851 case REGION_IO:
852 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
853 break;
854 case REGION_PALETTE_RAM:
855 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
856 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
857 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
858 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
859 break;
860 case REGION_VRAM:
861 if ((address & 0x0001FFFF) < SIZE_VRAM) {
862 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
863 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
864 } else {
865 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
866 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
867 }
868 break;
869 case REGION_OAM:
870 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
871 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
872 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
873 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
874 break;
875 case REGION_CART0:
876 case REGION_CART0_EX:
877 case REGION_CART1:
878 case REGION_CART1_EX:
879 case REGION_CART2:
880 case REGION_CART2_EX:
881 _pristineCow(gba);
882 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
883 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
884 }
885 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
886 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
887 break;
888 case REGION_CART_SRAM:
889 case REGION_CART_SRAM_MIRROR:
890 if (memory->savedata.type == SAVEDATA_SRAM) {
891 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
892 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
893 } else {
894 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
895 }
896 break;
897 default:
898 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
899 break;
900 }
901 if (old) {
902 *old = oldValue;
903 }
904}
905
906void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
907 struct GBA* gba = (struct GBA*) cpu->master;
908 struct GBAMemory* memory = &gba->memory;
909 int16_t oldValue = -1;
910
911 switch (address >> BASE_OFFSET) {
912 case REGION_WORKING_RAM:
913 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
914 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
915 break;
916 case REGION_WORKING_IRAM:
917 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
918 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
919 break;
920 case REGION_IO:
921 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
922 break;
923 case REGION_PALETTE_RAM:
924 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
925 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
926 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
927 break;
928 case REGION_VRAM:
929 if ((address & 0x0001FFFF) < SIZE_VRAM) {
930 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
931 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
932 } else {
933 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
934 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
935 }
936 break;
937 case REGION_OAM:
938 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
939 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
940 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
941 break;
942 case REGION_CART0:
943 case REGION_CART0_EX:
944 case REGION_CART1:
945 case REGION_CART1_EX:
946 case REGION_CART2:
947 case REGION_CART2_EX:
948 _pristineCow(gba);
949 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
950 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
951 }
952 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
953 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
954 break;
955 case REGION_CART_SRAM:
956 case REGION_CART_SRAM_MIRROR:
957 if (memory->savedata.type == SAVEDATA_SRAM) {
958 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
959 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
960 } else {
961 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
962 }
963 break;
964 default:
965 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
966 break;
967 }
968 if (old) {
969 *old = oldValue;
970 }
971}
972
973void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
974 struct GBA* gba = (struct GBA*) cpu->master;
975 struct GBAMemory* memory = &gba->memory;
976 int8_t oldValue = -1;
977
978 switch (address >> BASE_OFFSET) {
979 case REGION_WORKING_RAM:
980 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
981 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
982 break;
983 case REGION_WORKING_IRAM:
984 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
985 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
986 break;
987 case REGION_IO:
988 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
989 break;
990 case REGION_PALETTE_RAM:
991 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
992 break;
993 case REGION_VRAM:
994 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
995 break;
996 case REGION_OAM:
997 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
998 break;
999 case REGION_CART0:
1000 case REGION_CART0_EX:
1001 case REGION_CART1:
1002 case REGION_CART1_EX:
1003 case REGION_CART2:
1004 case REGION_CART2_EX:
1005 _pristineCow(gba);
1006 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1007 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1008 }
1009 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1010 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1011 break;
1012 case REGION_CART_SRAM:
1013 case REGION_CART_SRAM_MIRROR:
1014 if (memory->savedata.type == SAVEDATA_SRAM) {
1015 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1016 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1017 } else {
1018 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1019 }
1020 break;
1021 default:
1022 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1023 break;
1024 }
1025 if (old) {
1026 *old = oldValue;
1027 }
1028}
1029
1030#define LDM_LOOP(LDM) \
1031 for (i = 0; i < 16; i += 4) { \
1032 if (UNLIKELY(mask & (1 << i))) { \
1033 LDM; \
1034 waitstatesRegion = memory->waitstatesSeq32; \
1035 cpu->gprs[i] = value; \
1036 ++wait; \
1037 address += 4; \
1038 } \
1039 if (UNLIKELY(mask & (2 << i))) { \
1040 LDM; \
1041 waitstatesRegion = memory->waitstatesSeq32; \
1042 cpu->gprs[i + 1] = value; \
1043 ++wait; \
1044 address += 4; \
1045 } \
1046 if (UNLIKELY(mask & (4 << i))) { \
1047 LDM; \
1048 waitstatesRegion = memory->waitstatesSeq32; \
1049 cpu->gprs[i + 2] = value; \
1050 ++wait; \
1051 address += 4; \
1052 } \
1053 if (UNLIKELY(mask & (8 << i))) { \
1054 LDM; \
1055 waitstatesRegion = memory->waitstatesSeq32; \
1056 cpu->gprs[i + 3] = value; \
1057 ++wait; \
1058 address += 4; \
1059 } \
1060 }
1061
1062uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1063 struct GBA* gba = (struct GBA*) cpu->master;
1064 struct GBAMemory* memory = &gba->memory;
1065 uint32_t value;
1066 int wait = 0;
1067 char* waitstatesRegion = memory->waitstatesNonseq32;
1068
1069 int i;
1070 int offset = 4;
1071 int popcount = 0;
1072 if (direction & LSM_D) {
1073 offset = -4;
1074 popcount = _popcount32(mask);
1075 address -= (popcount << 2) - 4;
1076 }
1077
1078 if (direction & LSM_B) {
1079 address += offset;
1080 }
1081
1082 uint32_t addressMisalign = address & 0x3;
1083 address &= 0xFFFFFFFC;
1084
1085 switch (address >> BASE_OFFSET) {
1086 case REGION_BIOS:
1087 LDM_LOOP(LOAD_BIOS);
1088 break;
1089 case REGION_WORKING_RAM:
1090 LDM_LOOP(LOAD_WORKING_RAM);
1091 break;
1092 case REGION_WORKING_IRAM:
1093 LDM_LOOP(LOAD_WORKING_IRAM);
1094 break;
1095 case REGION_IO:
1096 LDM_LOOP(LOAD_IO);
1097 break;
1098 case REGION_PALETTE_RAM:
1099 LDM_LOOP(LOAD_PALETTE_RAM);
1100 break;
1101 case REGION_VRAM:
1102 LDM_LOOP(LOAD_VRAM);
1103 break;
1104 case REGION_OAM:
1105 LDM_LOOP(LOAD_OAM);
1106 break;
1107 case REGION_CART0:
1108 case REGION_CART0_EX:
1109 case REGION_CART1:
1110 case REGION_CART1_EX:
1111 case REGION_CART2:
1112 case REGION_CART2_EX:
1113 LDM_LOOP(LOAD_CART);
1114 break;
1115 case REGION_CART_SRAM:
1116 case REGION_CART_SRAM_MIRROR:
1117 LDM_LOOP(LOAD_SRAM);
1118 break;
1119 default:
1120 LDM_LOOP(LOAD_BAD);
1121 break;
1122 }
1123
1124 if (cycleCounter) {
1125 ++wait;
1126 if (address >> BASE_OFFSET < REGION_CART0) {
1127 wait = GBAMemoryStall(cpu, wait);
1128 }
1129 *cycleCounter += wait;
1130 }
1131
1132 if (direction & LSM_B) {
1133 address -= offset;
1134 }
1135
1136 if (direction & LSM_D) {
1137 address -= (popcount << 2) + 4;
1138 }
1139
1140 return address | addressMisalign;
1141}
1142
1143#define STM_LOOP(STM) \
1144 for (i = 0; i < 16; i += 4) { \
1145 if (UNLIKELY(mask & (1 << i))) { \
1146 value = cpu->gprs[i]; \
1147 STM; \
1148 waitstatesRegion = memory->waitstatesSeq32; \
1149 ++wait; \
1150 address += 4; \
1151 } \
1152 if (UNLIKELY(mask & (2 << i))) { \
1153 value = cpu->gprs[i + 1]; \
1154 STM; \
1155 waitstatesRegion = memory->waitstatesSeq32; \
1156 ++wait; \
1157 address += 4; \
1158 } \
1159 if (UNLIKELY(mask & (4 << i))) { \
1160 value = cpu->gprs[i + 2]; \
1161 STM; \
1162 waitstatesRegion = memory->waitstatesSeq32; \
1163 ++wait; \
1164 address += 4; \
1165 } \
1166 if (UNLIKELY(mask & (8 << i))) { \
1167 value = cpu->gprs[i + 3]; \
1168 STM; \
1169 waitstatesRegion = memory->waitstatesSeq32; \
1170 ++wait; \
1171 address += 4; \
1172 } \
1173 }
1174
1175uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1176 struct GBA* gba = (struct GBA*) cpu->master;
1177 struct GBAMemory* memory = &gba->memory;
1178 uint32_t value;
1179 int wait = 0;
1180 char* waitstatesRegion = memory->waitstatesNonseq32;
1181
1182 int i;
1183 int offset = 4;
1184 int popcount = 0;
1185 if (direction & LSM_D) {
1186 offset = -4;
1187 popcount = _popcount32(mask);
1188 address -= (popcount << 2) - 4;
1189 }
1190
1191 if (direction & LSM_B) {
1192 address += offset;
1193 }
1194
1195 uint32_t addressMisalign = address & 0x3;
1196 address &= 0xFFFFFFFC;
1197
1198 switch (address >> BASE_OFFSET) {
1199 case REGION_WORKING_RAM:
1200 STM_LOOP(STORE_WORKING_RAM);
1201 break;
1202 case REGION_WORKING_IRAM:
1203 STM_LOOP(STORE_WORKING_IRAM);
1204 break;
1205 case REGION_IO:
1206 STM_LOOP(STORE_IO);
1207 break;
1208 case REGION_PALETTE_RAM:
1209 STM_LOOP(STORE_PALETTE_RAM);
1210 break;
1211 case REGION_VRAM:
1212 STM_LOOP(STORE_VRAM);
1213 break;
1214 case REGION_OAM:
1215 STM_LOOP(STORE_OAM);
1216 break;
1217 case REGION_CART0:
1218 case REGION_CART0_EX:
1219 case REGION_CART1:
1220 case REGION_CART1_EX:
1221 case REGION_CART2:
1222 case REGION_CART2_EX:
1223 STM_LOOP(STORE_CART);
1224 break;
1225 case REGION_CART_SRAM:
1226 case REGION_CART_SRAM_MIRROR:
1227 STM_LOOP(STORE_SRAM);
1228 break;
1229 default:
1230 STM_LOOP(STORE_BAD);
1231 break;
1232 }
1233
1234 if (cycleCounter) {
1235 if (address >> BASE_OFFSET < REGION_CART0) {
1236 wait = GBAMemoryStall(cpu, wait);
1237 }
1238 *cycleCounter += wait;
1239 }
1240
1241 if (direction & LSM_B) {
1242 address -= offset;
1243 }
1244
1245 if (direction & LSM_D) {
1246 address -= (popcount << 2) + 4;
1247 }
1248
1249 return address | addressMisalign;
1250}
1251
1252void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1253 struct GBAMemory* memory = &gba->memory;
1254 struct ARMCore* cpu = gba->cpu;
1255 int sram = parameters & 0x0003;
1256 int ws0 = (parameters & 0x000C) >> 2;
1257 int ws0seq = (parameters & 0x0010) >> 4;
1258 int ws1 = (parameters & 0x0060) >> 5;
1259 int ws1seq = (parameters & 0x0080) >> 7;
1260 int ws2 = (parameters & 0x0300) >> 8;
1261 int ws2seq = (parameters & 0x0400) >> 10;
1262 int prefetch = parameters & 0x4000;
1263
1264 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1265 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1266 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1267 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1268
1269 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1270 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1271 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1272
1273 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1274 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1275 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1276
1277 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1278 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1279 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1280
1281 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1282 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1283 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1284
1285 memory->prefetch = prefetch;
1286
1287 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1288 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1289
1290 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1291 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1292}
1293
1294void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1295 struct GBAMemory* memory = &gba->memory;
1296 memory->dma[dma].source = address & 0x0FFFFFFE;
1297}
1298
1299void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1300 struct GBAMemory* memory = &gba->memory;
1301 memory->dma[dma].dest = address & 0x0FFFFFFE;
1302}
1303
1304void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1305 struct GBAMemory* memory = &gba->memory;
1306 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1307}
1308
1309uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1310 struct GBAMemory* memory = &gba->memory;
1311 struct GBADMA* currentDma = &memory->dma[dma];
1312 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1313 currentDma->reg = control;
1314
1315 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1316 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1317 }
1318
1319 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1320 currentDma->nextSource = currentDma->source;
1321 currentDma->nextDest = currentDma->dest;
1322 currentDma->nextCount = currentDma->count;
1323 GBAMemoryScheduleDMA(gba, dma, currentDma);
1324 }
1325 // If the DMA has already occurred, this value might have changed since the function started
1326 return currentDma->reg;
1327};
1328
1329void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1330 struct ARMCore* cpu = gba->cpu;
1331 switch (GBADMARegisterGetTiming(info->reg)) {
1332 case DMA_TIMING_NOW:
1333 info->nextEvent = cpu->cycles;
1334 GBAMemoryUpdateDMAs(gba, 0);
1335 break;
1336 case DMA_TIMING_HBLANK:
1337 // Handled implicitly
1338 info->nextEvent = INT_MAX;
1339 break;
1340 case DMA_TIMING_VBLANK:
1341 // Handled implicitly
1342 info->nextEvent = INT_MAX;
1343 break;
1344 case DMA_TIMING_CUSTOM:
1345 info->nextEvent = INT_MAX;
1346 switch (number) {
1347 case 0:
1348 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1349 break;
1350 case 1:
1351 case 2:
1352 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1353 break;
1354 case 3:
1355 // GBAVideoScheduleVCaptureDma(dma, info);
1356 break;
1357 }
1358 }
1359}
1360
1361void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1362 struct GBAMemory* memory = &gba->memory;
1363 struct GBADMA* dma;
1364 int i;
1365 for (i = 0; i < 4; ++i) {
1366 dma = &memory->dma[i];
1367 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1368 dma->nextEvent = cycles;
1369 }
1370 }
1371 GBAMemoryUpdateDMAs(gba, 0);
1372}
1373
1374void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1375 struct GBAMemory* memory = &gba->memory;
1376 struct GBADMA* dma;
1377 int i;
1378 for (i = 0; i < 4; ++i) {
1379 dma = &memory->dma[i];
1380 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1381 dma->nextEvent = cycles;
1382 }
1383 }
1384 GBAMemoryUpdateDMAs(gba, 0);
1385}
1386
1387int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1388 struct GBAMemory* memory = &gba->memory;
1389 if (memory->nextDMA == INT_MAX) {
1390 return INT_MAX;
1391 }
1392 memory->nextDMA -= cycles;
1393 memory->eventDiff += cycles;
1394 if (memory->nextDMA <= 0) {
1395 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1396 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1397 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1398 memory->eventDiff = 0;
1399 }
1400 return memory->nextDMA;
1401}
1402
1403void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1404 int i;
1405 struct GBAMemory* memory = &gba->memory;
1406 struct ARMCore* cpu = gba->cpu;
1407 memory->activeDMA = -1;
1408 memory->nextDMA = INT_MAX;
1409 for (i = 3; i >= 0; --i) {
1410 struct GBADMA* dma = &memory->dma[i];
1411 if (dma->nextEvent != INT_MAX) {
1412 dma->nextEvent -= cycles;
1413 if (GBADMARegisterIsEnable(dma->reg)) {
1414 memory->activeDMA = i;
1415 memory->nextDMA = dma->nextEvent;
1416 }
1417 }
1418 }
1419 if (memory->nextDMA < cpu->nextEvent) {
1420 cpu->nextEvent = memory->nextDMA;
1421 }
1422}
1423
1424void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1425 struct GBAMemory* memory = &gba->memory;
1426 struct ARMCore* cpu = gba->cpu;
1427 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1428 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1429 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1430 int32_t wordsRemaining = info->nextCount;
1431 uint32_t source = info->nextSource;
1432 uint32_t dest = info->nextDest;
1433 uint32_t sourceRegion = source >> BASE_OFFSET;
1434 uint32_t destRegion = dest >> BASE_OFFSET;
1435 int32_t cycles = 2;
1436
1437 if (source == info->source) {
1438 // TODO: support 4 cycles for ROM access
1439 cycles += 2;
1440 if (width == 4) {
1441 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1442 source &= 0xFFFFFFFC;
1443 dest &= 0xFFFFFFFC;
1444 } else {
1445 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1446 }
1447 } else {
1448 if (width == 4) {
1449 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1450 } else {
1451 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1452 }
1453 }
1454
1455 gba->performingDMA = true;
1456 int32_t word;
1457 if (width == 4) {
1458 word = cpu->memory.load32(cpu, source, 0);
1459 gba->bus = word;
1460 cpu->memory.store32(cpu, dest, word, 0);
1461 source += sourceOffset;
1462 dest += destOffset;
1463 --wordsRemaining;
1464 } else {
1465 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1466 word = GBASavedataReadEEPROM(&memory->savedata);
1467 gba->bus = word | (word << 16);
1468 cpu->memory.store16(cpu, dest, word, 0);
1469 source += sourceOffset;
1470 dest += destOffset;
1471 --wordsRemaining;
1472 } else if (destRegion == REGION_CART2_EX) {
1473 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1474 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1475 GBASavedataInitEEPROM(&memory->savedata);
1476 }
1477 word = cpu->memory.load16(cpu, source, 0);
1478 gba->bus = word | (word << 16);
1479 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1480 source += sourceOffset;
1481 dest += destOffset;
1482 --wordsRemaining;
1483 } else {
1484 word = cpu->memory.load16(cpu, source, 0);
1485 gba->bus = word | (word << 16);
1486 cpu->memory.store16(cpu, dest, word, 0);
1487 source += sourceOffset;
1488 dest += destOffset;
1489 --wordsRemaining;
1490 }
1491 }
1492 gba->performingDMA = false;
1493
1494 if (!wordsRemaining) {
1495 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1496 info->reg = GBADMARegisterClearEnable(info->reg);
1497 info->nextEvent = INT_MAX;
1498
1499 // Clear the enable bit in memory
1500 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1501 } else {
1502 info->nextCount = info->count;
1503 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1504 info->nextDest = info->dest;
1505 }
1506 GBAMemoryScheduleDMA(gba, number, info);
1507 }
1508 if (GBADMARegisterIsDoIRQ(info->reg)) {
1509 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1510 }
1511 } else {
1512 info->nextDest = dest;
1513 info->nextCount = wordsRemaining;
1514 }
1515 info->nextSource = source;
1516
1517 if (info->nextEvent != INT_MAX) {
1518 info->nextEvent += cycles;
1519 }
1520 cpu->cycles += cycles;
1521}
1522
1523int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1524 struct GBA* gba = (struct GBA*) cpu->master;
1525 struct GBAMemory* memory = &gba->memory;
1526
1527 if (!memory->prefetch || memory->activeRegion < REGION_CART0) {
1528 return wait;
1529 }
1530
1531 int32_t stall = memory->waitstatesNonseq16[memory->activeRegion] - memory->waitstatesSeq16[memory->activeRegion] + 1;
1532
1533 // Base number of cycles for this insn is N
1534 int32_t base = memory->waitstatesSeq16[memory->activeRegion] + 1;
1535 if (cpu->executionMode == MODE_ARM) {
1536 base <<= 1;
1537 }
1538 if (base <= wait) {
1539 --base;
1540 } else {
1541 base = wait;
1542 }
1543
1544 cpu->cycles -= stall + base - 1;
1545 return wait;
1546}
1547
1548void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1549 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1550 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1551}
1552
1553void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1554 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1555 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1556}
1557
1558uint32_t _popcount32(unsigned bits) {
1559 bits = bits - ((bits >> 1) & 0x55555555);
1560 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1561 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1562}
1563
1564void _pristineCow(struct GBA* gba) {
1565 if (gba->memory.rom != gba->pristineRom) {
1566 return;
1567 }
1568 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1569 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1570 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1571}