src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/memory.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/gb/gb.h>
10#include <mgba/internal/gb/io.h>
11#include <mgba/internal/gb/mbc.h>
12#include <mgba/internal/gb/serialize.h>
13#include <mgba/internal/lr35902/lr35902.h>
14
15#include <mgba-util/memory.h>
16
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory", "gb.memory");
18
19struct OAMBlock {
20 uint16_t low;
21 uint16_t high;
22};
23
24static const struct OAMBlock _oamBlockDMG[] = {
25 { 0xA000, 0xFE00 },
26 { 0xA000, 0xFE00 },
27 { 0xA000, 0xFE00 },
28 { 0xA000, 0xFE00 },
29 { 0x8000, 0xA000 },
30 { 0xA000, 0xFE00 },
31 { 0xA000, 0xFE00 },
32 { 0xA000, 0xFE00 },
33};
34
35static const struct OAMBlock _oamBlockCGB[] = {
36 { 0xA000, 0xC000 },
37 { 0xA000, 0xC000 },
38 { 0xA000, 0xC000 },
39 { 0xA000, 0xC000 },
40 { 0x8000, 0xA000 },
41 { 0xA000, 0xC000 },
42 { 0xC000, 0xFE00 },
43 { 0xA000, 0xC000 },
44};
45
46static void _pristineCow(struct GB* gba);
47
48static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
49 if (UNLIKELY(address >= cpu->memory.activeRegionEnd)) {
50 cpu->memory.setActiveRegion(cpu, address);
51 return cpu->memory.cpuLoad8(cpu, address);
52 }
53 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
54}
55
56static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
57 struct GB* gb = (struct GB*) cpu->master;
58 struct GBMemory* memory = &gb->memory;
59 switch (address >> 12) {
60 case GB_REGION_CART_BANK0:
61 case GB_REGION_CART_BANK0 + 1:
62 case GB_REGION_CART_BANK0 + 2:
63 case GB_REGION_CART_BANK0 + 3:
64 cpu->memory.cpuLoad8 = GBFastLoad8;
65 cpu->memory.activeRegion = memory->romBase;
66 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
67 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
68 break;
69 case GB_REGION_CART_BANK1:
70 case GB_REGION_CART_BANK1 + 1:
71 case GB_REGION_CART_BANK1 + 2:
72 case GB_REGION_CART_BANK1 + 3:
73 cpu->memory.cpuLoad8 = GBFastLoad8;
74 cpu->memory.activeRegion = memory->romBank;
75 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
76 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
77 break;
78 default:
79 cpu->memory.cpuLoad8 = GBLoad8;
80 break;
81 }
82}
83
84static void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
85static void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
86
87void GBMemoryInit(struct GB* gb) {
88 struct LR35902Core* cpu = gb->cpu;
89 cpu->memory.cpuLoad8 = GBLoad8;
90 cpu->memory.load8 = GBLoad8;
91 cpu->memory.store8 = GBStore8;
92 cpu->memory.currentSegment = GBCurrentSegment;
93 cpu->memory.setActiveRegion = GBSetActiveRegion;
94
95 gb->memory.wram = 0;
96 gb->memory.wramBank = 0;
97 gb->memory.rom = 0;
98 gb->memory.romBank = 0;
99 gb->memory.romSize = 0;
100 gb->memory.sram = 0;
101 gb->memory.mbcType = GB_MBC_AUTODETECT;
102 gb->memory.mbcRead = NULL;
103 gb->memory.mbcWrite = NULL;
104
105 gb->memory.rtc = NULL;
106 gb->memory.rotation = NULL;
107 gb->memory.rumble = NULL;
108 gb->memory.cam = NULL;
109
110 GBIOInit(gb);
111}
112
113void GBMemoryDeinit(struct GB* gb) {
114 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
115 if (gb->memory.rom) {
116 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
117 }
118}
119
120void GBMemoryReset(struct GB* gb) {
121 if (gb->memory.wram) {
122 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
123 }
124 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
125 if (gb->model >= GB_MODEL_CGB) {
126 uint32_t* base = (uint32_t*) gb->memory.wram;
127 size_t i;
128 uint32_t pattern = 0;
129 for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
130 if ((i & 0x1FF) == 0) {
131 pattern = ~pattern;
132 }
133 base[i + 0] = pattern;
134 base[i + 1] = pattern;
135 base[i + 2] = ~pattern;
136 base[i + 3] = ~pattern;
137 }
138 }
139 GBMemorySwitchWramBank(&gb->memory, 1);
140 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
141 gb->memory.currentBank = 1;
142 gb->memory.sramCurrentBank = 0;
143
144 gb->memory.ime = false;
145 gb->memory.ie = 0;
146
147 gb->memory.dmaRemaining = 0;
148 gb->memory.dmaSource = 0;
149 gb->memory.dmaDest = 0;
150 gb->memory.hdmaRemaining = 0;
151 gb->memory.hdmaSource = 0;
152 gb->memory.hdmaDest = 0;
153 gb->memory.isHdma = false;
154
155
156 gb->memory.dmaEvent.context = gb;
157 gb->memory.dmaEvent.name = "GB DMA";
158 gb->memory.dmaEvent.callback = _GBMemoryDMAService;
159 gb->memory.dmaEvent.priority = 0x40;
160 gb->memory.hdmaEvent.context = gb;
161 gb->memory.hdmaEvent.name = "GB HDMA";
162 gb->memory.hdmaEvent.callback = _GBMemoryHDMAService;
163 gb->memory.hdmaEvent.priority = 0x41;
164
165 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
166 switch (gb->memory.mbcType) {
167 case GB_MBC1:
168 gb->memory.mbcState.mbc1.mode = 0;
169 break;
170 default:
171 memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
172 }
173
174 GBMBCInit(gb);
175 gb->memory.sramBank = gb->memory.sram;
176
177 if (!gb->memory.wram) {
178 GBMemoryDeinit(gb);
179 }
180}
181
182void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
183 bank &= 7;
184 if (!bank) {
185 bank = 1;
186 }
187 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
188 memory->wramCurrentBank = bank;
189}
190
191uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
192 struct GB* gb = (struct GB*) cpu->master;
193 struct GBMemory* memory = &gb->memory;
194 if (gb->memory.dmaRemaining) {
195 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
196 block = &block[memory->dmaSource >> 13];
197 if (address >= block->low && address < block->high) {
198 return 0xFF;
199 }
200 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
201 return 0xFF;
202 }
203 }
204 switch (address >> 12) {
205 case GB_REGION_CART_BANK0:
206 case GB_REGION_CART_BANK0 + 1:
207 case GB_REGION_CART_BANK0 + 2:
208 case GB_REGION_CART_BANK0 + 3:
209 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
210 case GB_REGION_CART_BANK1 + 2:
211 case GB_REGION_CART_BANK1 + 3:
212 if (memory->mbcType == GB_MBC6) {
213 return memory->mbcState.mbc6.romBank1[address & (GB_SIZE_CART_HALFBANK - 1)];
214 }
215 // Fall through
216 case GB_REGION_CART_BANK1:
217 case GB_REGION_CART_BANK1 + 1:
218 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
219 case GB_REGION_VRAM:
220 case GB_REGION_VRAM + 1:
221 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
222 case GB_REGION_EXTERNAL_RAM:
223 case GB_REGION_EXTERNAL_RAM + 1:
224 if (memory->rtcAccess) {
225 return memory->rtcRegs[memory->activeRtcReg];
226 } else if (memory->mbcRead) {
227 return memory->mbcRead(memory, address);
228 } else if (memory->sramAccess && memory->sram) {
229 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
230 } else if (memory->mbcType == GB_HuC3) {
231 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
232 }
233 return 0xFF;
234 case GB_REGION_WORKING_RAM_BANK0:
235 case GB_REGION_WORKING_RAM_BANK0 + 2:
236 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
237 case GB_REGION_WORKING_RAM_BANK1:
238 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
239 default:
240 if (address < GB_BASE_OAM) {
241 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
242 }
243 if (address < GB_BASE_UNUSABLE) {
244 if (gb->video.mode < 2) {
245 return gb->video.oam.raw[address & 0xFF];
246 }
247 return 0xFF;
248 }
249 if (address < GB_BASE_IO) {
250 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
251 return 0xFF;
252 }
253 if (address < GB_BASE_HRAM) {
254 return GBIORead(gb, address & (GB_SIZE_IO - 1));
255 }
256 if (address < GB_BASE_IE) {
257 return memory->hram[address & GB_SIZE_HRAM];
258 }
259 return GBIORead(gb, REG_IE);
260 }
261}
262
263void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
264 struct GB* gb = (struct GB*) cpu->master;
265 struct GBMemory* memory = &gb->memory;
266 if (gb->memory.dmaRemaining) {
267 const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
268 block = &block[memory->dmaSource >> 13];
269 if (address >= block->low && address < block->high) {
270 return;
271 }
272 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
273 return;
274 }
275 }
276 switch (address >> 12) {
277 case GB_REGION_CART_BANK0:
278 case GB_REGION_CART_BANK0 + 1:
279 case GB_REGION_CART_BANK0 + 2:
280 case GB_REGION_CART_BANK0 + 3:
281 case GB_REGION_CART_BANK1:
282 case GB_REGION_CART_BANK1 + 1:
283 case GB_REGION_CART_BANK1 + 2:
284 case GB_REGION_CART_BANK1 + 3:
285 memory->mbcWrite(gb, address, value);
286 cpu->memory.setActiveRegion(cpu, cpu->pc);
287 return;
288 case GB_REGION_VRAM:
289 case GB_REGION_VRAM + 1:
290 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) | (GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank));
291 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
292 return;
293 case GB_REGION_EXTERNAL_RAM:
294 case GB_REGION_EXTERNAL_RAM + 1:
295 if (memory->rtcAccess) {
296 memory->rtcRegs[memory->activeRtcReg] = value;
297 } else if (memory->sramAccess && memory->sram && memory->mbcType != GB_MBC2) {
298 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
299 } else {
300 memory->mbcWrite(gb, address, value);
301 }
302 gb->sramDirty |= GB_SRAM_DIRT_NEW;
303 return;
304 case GB_REGION_WORKING_RAM_BANK0:
305 case GB_REGION_WORKING_RAM_BANK0 + 2:
306 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
307 return;
308 case GB_REGION_WORKING_RAM_BANK1:
309 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
310 return;
311 default:
312 if (address < GB_BASE_OAM) {
313 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
314 } else if (address < GB_BASE_UNUSABLE) {
315 if (gb->video.mode < 2) {
316 gb->video.oam.raw[address & 0xFF] = value;
317 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
318 }
319 } else if (address < GB_BASE_IO) {
320 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
321 } else if (address < GB_BASE_HRAM) {
322 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
323 } else if (address < GB_BASE_IE) {
324 memory->hram[address & GB_SIZE_HRAM] = value;
325 } else {
326 GBIOWrite(gb, REG_IE, value);
327 }
328 }
329}
330
331int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address) {
332 struct GB* gb = (struct GB*) cpu->master;
333 struct GBMemory* memory = &gb->memory;
334 switch (address >> 12) {
335 case GB_REGION_CART_BANK0:
336 case GB_REGION_CART_BANK0 + 1:
337 case GB_REGION_CART_BANK0 + 2:
338 case GB_REGION_CART_BANK0 + 3:
339 return 0;
340 case GB_REGION_CART_BANK1:
341 case GB_REGION_CART_BANK1 + 1:
342 case GB_REGION_CART_BANK1 + 2:
343 case GB_REGION_CART_BANK1 + 3:
344 return memory->currentBank;
345 case GB_REGION_VRAM:
346 case GB_REGION_VRAM + 1:
347 return gb->video.vramCurrentBank;
348 case GB_REGION_EXTERNAL_RAM:
349 case GB_REGION_EXTERNAL_RAM + 1:
350 return memory->sramCurrentBank;
351 case GB_REGION_WORKING_RAM_BANK0:
352 case GB_REGION_WORKING_RAM_BANK0 + 2:
353 return 0;
354 case GB_REGION_WORKING_RAM_BANK1:
355 return memory->wramCurrentBank;
356 default:
357 return 0;
358 }
359}
360
361uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) {
362 struct GB* gb = (struct GB*) cpu->master;
363 struct GBMemory* memory = &gb->memory;
364 switch (address >> 12) {
365 case GB_REGION_CART_BANK0:
366 case GB_REGION_CART_BANK0 + 1:
367 case GB_REGION_CART_BANK0 + 2:
368 case GB_REGION_CART_BANK0 + 3:
369 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
370 case GB_REGION_CART_BANK1:
371 case GB_REGION_CART_BANK1 + 1:
372 case GB_REGION_CART_BANK1 + 2:
373 case GB_REGION_CART_BANK1 + 3:
374 if (segment < 0) {
375 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
376 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
377 return memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
378 } else {
379 return 0xFF;
380 }
381 case GB_REGION_VRAM:
382 case GB_REGION_VRAM + 1:
383 if (segment < 0) {
384 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
385 } else if (segment < 2) {
386 return gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment *GB_SIZE_VRAM_BANK0];
387 } else {
388 return 0xFF;
389 }
390 case GB_REGION_EXTERNAL_RAM:
391 case GB_REGION_EXTERNAL_RAM + 1:
392 if (memory->rtcAccess) {
393 return memory->rtcRegs[memory->activeRtcReg];
394 } else if (memory->sramAccess) {
395 if (segment < 0 && memory->sram) {
396 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
397 } else if ((size_t) segment * GB_SIZE_EXTERNAL_RAM < gb->sramSize) {
398 return memory->sram[(address & (GB_SIZE_EXTERNAL_RAM - 1)) + segment *GB_SIZE_EXTERNAL_RAM];
399 } else {
400 return 0xFF;
401 }
402 } else if (memory->mbcRead) {
403 return memory->mbcRead(memory, address);
404 } else if (memory->mbcType == GB_HuC3) {
405 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
406 }
407 return 0xFF;
408 case GB_REGION_WORKING_RAM_BANK0:
409 case GB_REGION_WORKING_RAM_BANK0 + 2:
410 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
411 case GB_REGION_WORKING_RAM_BANK1:
412 if (segment < 0) {
413 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
414 } else if (segment < 8) {
415 return memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment *GB_SIZE_WORKING_RAM_BANK0];
416 } else {
417 return 0xFF;
418 }
419 default:
420 if (address < GB_BASE_OAM) {
421 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
422 }
423 if (address < GB_BASE_UNUSABLE) {
424 if (gb->video.mode < 2) {
425 return gb->video.oam.raw[address & 0xFF];
426 }
427 return 0xFF;
428 }
429 if (address < GB_BASE_IO) {
430 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
431 return 0xFF;
432 }
433 if (address < GB_BASE_HRAM) {
434 return GBIORead(gb, address & (GB_SIZE_IO - 1));
435 }
436 if (address < GB_BASE_IE) {
437 return memory->hram[address & GB_SIZE_HRAM];
438 }
439 return GBIORead(gb, REG_IE);
440 }
441}
442
443void GBMemoryDMA(struct GB* gb, uint16_t base) {
444 if (base > 0xF100) {
445 return;
446 }
447 mTimingDeschedule(&gb->timing, &gb->memory.dmaEvent);
448 mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8);
449 if (gb->cpu->cycles + 8 < gb->cpu->nextEvent) {
450 gb->cpu->nextEvent = gb->cpu->cycles + 8;
451 }
452 gb->memory.dmaSource = base;
453 gb->memory.dmaDest = 0;
454 gb->memory.dmaRemaining = 0xA0;
455}
456
457uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
458 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
459 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
460 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
461 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
462 gb->memory.hdmaSource &= 0xFFF0;
463 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
464 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
465 return value | 0x80;
466 }
467 gb->memory.hdmaDest &= 0x1FF0;
468 gb->memory.hdmaDest |= 0x8000;
469 bool wasHdma = gb->memory.isHdma;
470 gb->memory.isHdma = value & 0x80;
471 if ((!wasHdma && !gb->memory.isHdma) || gb->video.mode == 0) {
472 if (gb->memory.isHdma) {
473 gb->memory.hdmaRemaining = 0x10;
474 } else {
475 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
476 }
477 gb->cpuBlocked = true;
478 mTimingSchedule(&gb->timing, &gb->memory.hdmaEvent, 0);
479 } else if (gb->memory.isHdma && !GBRegisterLCDCIsEnable(gb->memory.io[REG_LCDC])) {
480 return 0x80 | ((value + 1) & 0x7F);
481 }
482 return value & 0x7F;
483}
484
485void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
486 struct GB* gb = context;
487 int dmaRemaining = gb->memory.dmaRemaining;
488 gb->memory.dmaRemaining = 0;
489 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
490 // TODO: Can DMA write OAM during modes 2-3?
491 gb->video.oam.raw[gb->memory.dmaDest] = b;
492 gb->video.renderer->writeOAM(gb->video.renderer, gb->memory.dmaDest);
493 ++gb->memory.dmaSource;
494 ++gb->memory.dmaDest;
495 gb->memory.dmaRemaining = dmaRemaining - 1;
496 if (gb->memory.dmaRemaining) {
497 mTimingSchedule(timing, &gb->memory.dmaEvent, 4 - cyclesLate);
498 }
499}
500
501void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
502 struct GB* gb = context;
503 gb->cpuBlocked = true;
504 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
505 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
506 ++gb->memory.hdmaSource;
507 ++gb->memory.hdmaDest;
508 --gb->memory.hdmaRemaining;
509 if (gb->memory.hdmaRemaining) {
510 mTimingDeschedule(timing, &gb->memory.hdmaEvent);
511 mTimingSchedule(timing, &gb->memory.hdmaEvent, 2 - cyclesLate);
512 } else {
513 gb->cpuBlocked = false;
514 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
515 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
516 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
517 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
518 if (gb->memory.isHdma) {
519 --gb->memory.io[REG_HDMA5];
520 if (gb->memory.io[REG_HDMA5] == 0xFF) {
521 gb->memory.isHdma = false;
522 }
523 } else {
524 gb->memory.io[REG_HDMA5] = 0xFF;
525 }
526 }
527}
528
529void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment) {
530 struct GB* gb = (struct GB*) cpu->master;
531 struct GBMemory* memory = &gb->memory;
532 int8_t oldValue = -1;
533
534 switch (address >> 12) {
535 case GB_REGION_CART_BANK0:
536 case GB_REGION_CART_BANK0 + 1:
537 case GB_REGION_CART_BANK0 + 2:
538 case GB_REGION_CART_BANK0 + 3:
539 _pristineCow(gb);
540 oldValue = memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
541 memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)] = value;
542 break;
543 case GB_REGION_CART_BANK1:
544 case GB_REGION_CART_BANK1 + 1:
545 case GB_REGION_CART_BANK1 + 2:
546 case GB_REGION_CART_BANK1 + 3:
547 _pristineCow(gb);
548 if (segment < 0) {
549 oldValue = memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
550 memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)] = value;
551 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
552 oldValue = memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
553 memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0] = value;
554 } else {
555 return;
556 }
557 break;
558 case GB_REGION_VRAM:
559 case GB_REGION_VRAM + 1:
560 if (segment < 0) {
561 oldValue = gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
562 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
563 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank);
564 } else if (segment < 2) {
565 oldValue = gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0];
566 gb->video.vramBank[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0] = value;
567 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0);
568 } else {
569 return;
570 }
571 break;
572 case GB_REGION_EXTERNAL_RAM:
573 case GB_REGION_EXTERNAL_RAM + 1:
574 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
575 return;
576 case GB_REGION_WORKING_RAM_BANK0:
577 case GB_REGION_WORKING_RAM_BANK0 + 2:
578 oldValue = memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
579 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
580 break;
581 case GB_REGION_WORKING_RAM_BANK1:
582 if (segment < 0) {
583 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
584 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
585 } else if (segment < 8) {
586 oldValue = memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0];
587 memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0] = value;
588 } else {
589 return;
590 }
591 break;
592 default:
593 if (address < GB_BASE_OAM) {
594 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
595 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
596 } else if (address < GB_BASE_UNUSABLE) {
597 oldValue = gb->video.oam.raw[address & 0xFF];
598 gb->video.oam.raw[address & 0xFF] = value;
599 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
600 } else if (address < GB_BASE_HRAM) {
601 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
602 return;
603 } else if (address < GB_BASE_IE) {
604 oldValue = memory->hram[address & GB_SIZE_HRAM];
605 memory->hram[address & GB_SIZE_HRAM] = value;
606 } else {
607 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
608 return;
609 }
610 }
611 if (old) {
612 *old = oldValue;
613 }
614}
615
616void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
617 const struct GBMemory* memory = &gb->memory;
618 memcpy(state->wram, memory->wram, GB_SIZE_WORKING_RAM);
619 memcpy(state->hram, memory->hram, GB_SIZE_HRAM);
620 STORE_16LE(memory->currentBank, 0, &state->memory.currentBank);
621 state->memory.wramCurrentBank = memory->wramCurrentBank;
622 state->memory.sramCurrentBank = memory->sramCurrentBank;
623
624 STORE_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
625 STORE_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
626
627 STORE_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
628 STORE_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
629
630 STORE_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
631 state->memory.dmaRemaining = memory->dmaRemaining;
632 memcpy(state->memory.rtcRegs, memory->rtcRegs, sizeof(state->memory.rtcRegs));
633
634 STORE_32LE(memory->dmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.dmaNext);
635 STORE_32LE(memory->hdmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.hdmaNext);
636
637 GBSerializedMemoryFlags flags = 0;
638 flags = GBSerializedMemoryFlagsSetSramAccess(flags, memory->sramAccess);
639 flags = GBSerializedMemoryFlagsSetRtcAccess(flags, memory->rtcAccess);
640 flags = GBSerializedMemoryFlagsSetRtcLatched(flags, memory->rtcLatched);
641 flags = GBSerializedMemoryFlagsSetIme(flags, memory->ime);
642 flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
643 flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
644 STORE_16LE(flags, 0, &state->memory.flags);
645
646 switch (memory->mbcType) {
647 case GB_MBC1:
648 state->memory.mbc1.mode = memory->mbcState.mbc1.mode;
649 state->memory.mbc1.multicartStride = memory->mbcState.mbc1.multicartStride;
650 break;
651 case GB_MBC3_RTC:
652 STORE_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
653 break;
654 case GB_MBC7:
655 state->memory.mbc7.state = memory->mbcState.mbc7.state;
656 state->memory.mbc7.eeprom = memory->mbcState.mbc7.eeprom;
657 state->memory.mbc7.address = memory->mbcState.mbc7.address;
658 state->memory.mbc7.access = memory->mbcState.mbc7.access;
659 state->memory.mbc7.latch = memory->mbcState.mbc7.latch;
660 state->memory.mbc7.srBits = memory->mbcState.mbc7.srBits;
661 STORE_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
662 STORE_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
663 break;
664 default:
665 break;
666 }
667}
668
669void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
670 struct GBMemory* memory = &gb->memory;
671 memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
672 memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
673 LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
674 memory->wramCurrentBank = state->memory.wramCurrentBank;
675 memory->sramCurrentBank = state->memory.sramCurrentBank;
676
677 GBMBCSwitchBank(gb, memory->currentBank);
678 GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
679 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
680
681 LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
682 LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
683
684 LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
685 LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
686
687 LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
688 memory->dmaRemaining = state->memory.dmaRemaining;
689 memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
690
691 uint32_t when;
692 LOAD_32LE(when, 0, &state->memory.dmaNext);
693 if (memory->dmaRemaining) {
694 mTimingSchedule(&gb->timing, &memory->dmaEvent, when);
695 }
696 LOAD_32LE(when, 0, &state->memory.hdmaNext);
697 if (memory->hdmaRemaining) {
698 mTimingSchedule(&gb->timing, &memory->hdmaEvent, when);
699 }
700
701 GBSerializedMemoryFlags flags;
702 LOAD_16LE(flags, 0, &state->memory.flags);
703 memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
704 memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
705 memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
706 memory->ime = GBSerializedMemoryFlagsGetIme(flags);
707 memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
708 memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
709
710 switch (memory->mbcType) {
711 case GB_MBC1:
712 memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
713 memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
714 if (memory->mbcState.mbc1.mode) {
715 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
716 }
717 break;
718 case GB_MBC3_RTC:
719 LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
720 break;
721 case GB_MBC7:
722 memory->mbcState.mbc7.state = state->memory.mbc7.state;
723 memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
724 memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
725 memory->mbcState.mbc7.access = state->memory.mbc7.access;
726 memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
727 memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
728 LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
729 LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
730 break;
731 default:
732 break;
733 }
734}
735
736void _pristineCow(struct GB* gb) {
737 if (!gb->isPristine) {
738 return;
739 }
740 void* newRom = anonymousMemoryMap(GB_SIZE_CART_MAX);
741 memcpy(newRom, gb->memory.rom, gb->memory.romSize);
742 memset(((uint8_t*) newRom) + gb->memory.romSize, 0xFF, GB_SIZE_CART_MAX - gb->memory.romSize);
743 if (gb->memory.rom == gb->memory.romBase) {
744 gb->memory.romBase = newRom;
745 }
746 gb->memory.rom = newRom;
747 GBMBCSwitchBank(gb, gb->memory.currentBank);
748 gb->isPristine = false;
749}