src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
188 cpu->cpsr.n = ARM_SIGN(d);
189 cpu->cpsr.z = !d;
190 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
191 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
192}
193
194ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
195 cpu->cpsr.n = ARM_SIGN(d);
196 cpu->cpsr.z = !d;
197 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
198 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
199}
200
201ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
202 cpu->cpsr.n = ARM_SIGN(d);
203 cpu->cpsr.z = !d; \
204 cpu->cpsr.c = cpu->shifterCarryOut; \
205}
206
207#define ARM_ADDITION_S(M, N, D) \
208 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
209 cpu->cpsr = cpu->spsr; \
210 _ARMReadCPSR(cpu); \
211 } else { \
212 _additionS(cpu, M, N, D); \
213 }
214
215#define ARM_SUBTRACTION_S(M, N, D) \
216 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
217 cpu->cpsr = cpu->spsr; \
218 _ARMReadCPSR(cpu); \
219 } else { \
220 _subtractionS(cpu, M, N, D); \
221 }
222
223#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
224 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
225 cpu->cpsr = cpu->spsr; \
226 _ARMReadCPSR(cpu); \
227 } else { \
228 cpu->cpsr.n = ARM_SIGN(D); \
229 cpu->cpsr.z = !(D); \
230 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
231 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
232 }
233
234#define ARM_NEUTRAL_S(M, N, D) \
235 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
236 cpu->cpsr = cpu->spsr; \
237 _ARMReadCPSR(cpu); \
238 } else { \
239 _neutralS(cpu, D); \
240 }
241
242#define ARM_NEUTRAL_HI_S(DLO, DHI) \
243 cpu->cpsr.n = ARM_SIGN(DHI); \
244 cpu->cpsr.z = !((DHI) | (DLO));
245
246#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
247#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
248#define ADDR_MODE_2_ADDRESS (address)
249#define ADDR_MODE_2_RN (cpu->gprs[rn])
250#define ADDR_MODE_2_RM (cpu->gprs[rm])
251#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
252#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
253#define ADDR_MODE_2_WRITEBACK(ADDR) \
254 cpu->gprs[rn] = ADDR; \
255 if (UNLIKELY(rn == ARM_PC)) { \
256 ARM_WRITE_PC; \
257 }
258
259#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
260#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
261#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
262#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
263
264#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
265#define ADDR_MODE_3_RN ADDR_MODE_2_RN
266#define ADDR_MODE_3_RM ADDR_MODE_2_RM
267#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
268#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
269#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
270
271#define ADDR_MODE_4_WRITEBACK_LDM \
272 if (!((1 << rn) & rs)) { \
273 cpu->gprs[rn] = address; \
274 }
275
276#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
277
278#define ARM_LOAD_POST_BODY \
279 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
280 if (rd == ARM_PC) { \
281 ARM_WRITE_PC; \
282 }
283
284#define ARM_STORE_POST_BODY \
285 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
286
287#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
288 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
289 int currentCycles = ARM_PREFETCH_CYCLES; \
290 BODY; \
291 cpu->cycles += currentCycles; \
292 }
293
294#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
295 DEFINE_INSTRUCTION_ARM(NAME, \
296 int rd = (opcode >> 12) & 0xF; \
297 int rn = (opcode >> 16) & 0xF; \
298 UNUSED(rn); \
299 SHIFTER(cpu, opcode); \
300 BODY; \
301 S_BODY; \
302 if (rd == ARM_PC) { \
303 if (cpu->executionMode == MODE_ARM) { \
304 ARM_WRITE_PC; \
305 } else { \
306 THUMB_WRITE_PC; \
307 } \
308 })
309
310#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
321
322#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
328
329#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
330 DEFINE_INSTRUCTION_ARM(NAME, \
331 int rd = (opcode >> 16) & 0xF; \
332 int rs = (opcode >> 8) & 0xF; \
333 int rm = opcode & 0xF; \
334 if (rd == ARM_PC) { \
335 return; \
336 } \
337 ARM_WAIT_MUL(cpu->gprs[rs]); \
338 BODY; \
339 S_BODY; \
340 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
341
342#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
343 DEFINE_INSTRUCTION_ARM(NAME, \
344 int rd = (opcode >> 12) & 0xF; \
345 int rdHi = (opcode >> 16) & 0xF; \
346 int rs = (opcode >> 8) & 0xF; \
347 int rm = opcode & 0xF; \
348 if (rdHi == ARM_PC || rd == ARM_PC) { \
349 return; \
350 } \
351 currentCycles += cpu->memory.stall(cpu, WAIT); \
352 BODY; \
353 S_BODY; \
354 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
355
356#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
357 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
358 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
359
360#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
361 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
362 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
363
364#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
365 DEFINE_INSTRUCTION_ARM(NAME, \
366 uint32_t address; \
367 int rn = (opcode >> 16) & 0xF; \
368 int rd = (opcode >> 12) & 0xF; \
369 int rm = opcode & 0xF; \
370 UNUSED(rm); \
371 address = ADDRESS; \
372 WRITEBACK; \
373 BODY;)
374
375#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
382
383#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
394
395#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
408
409#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
412
413#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
414 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
415 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
416 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
417 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
420
421#define ARM_MS_PRE \
422 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
423 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
424
425#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
426
427#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
428 DEFINE_INSTRUCTION_ARM(NAME, \
429 int rn = (opcode >> 16) & 0xF; \
430 int rs = opcode & 0x0000FFFF; \
431 uint32_t address = cpu->gprs[rn]; \
432 S_PRE; \
433 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
434 S_POST; \
435 POST_BODY; \
436 WRITEBACK;)
437
438
439#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
450 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
451 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
456
457// Begin ALU definitions
458
459DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
460 int32_t n = cpu->gprs[rn];
461 cpu->gprs[rd] = n + cpu->shifterOperand;)
462
463DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
464 int32_t n = cpu->gprs[rn];
465 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
466
467DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
468 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
469
470DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
471 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
472
473DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
474 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
475
476DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
477 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
478
479DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
480 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
481
482DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
483 cpu->gprs[rd] = cpu->shifterOperand;)
484
485DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
486 cpu->gprs[rd] = ~cpu->shifterOperand;)
487
488DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
489 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
490
491DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
492 int32_t n = cpu->gprs[rn];
493 cpu->gprs[rd] = cpu->shifterOperand - n;)
494
495DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
496 int32_t n = cpu->gprs[rn];
497 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
498
499DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
500 int32_t n = cpu->gprs[rn];
501 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
502
503DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
504 int32_t n = cpu->gprs[rn];
505 cpu->gprs[rd] = n - cpu->shifterOperand;)
506
507DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
508 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
509
510DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
511 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
512
513// End ALU definitions
514
515// Begin multiply definitions
516
517DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
518DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
519
520DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
521 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
522 int32_t dm = cpu->gprs[rd];
523 int32_t dn = d;
524 cpu->gprs[rd] = dm + dn;
525 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
526 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
527
528DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
529 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
530 cpu->gprs[rd] = d;
531 cpu->gprs[rdHi] = d >> 32;,
532 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
533
534DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
535 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
536 int32_t dm = cpu->gprs[rd];
537 int32_t dn = d;
538 cpu->gprs[rd] = dm + dn;
539 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
540 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
541
542DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
543 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
544 cpu->gprs[rd] = d;
545 cpu->gprs[rdHi] = d >> 32;,
546 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
547
548// End multiply definitions
549
550// Begin load/store definitions
551
552DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
553DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
554DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
555DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
556DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
557DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
558DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
559DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
560
561DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
562 enum PrivilegeMode priv = cpu->privilegeMode;
563 ARMSetPrivilegeMode(cpu, MODE_USER);
564 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
565 ARMSetPrivilegeMode(cpu, priv);
566 cpu->gprs[rd] = r;
567 ARM_LOAD_POST_BODY;)
568
569DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
570 enum PrivilegeMode priv = cpu->privilegeMode;
571 ARMSetPrivilegeMode(cpu, MODE_USER);
572 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
573 ARMSetPrivilegeMode(cpu, priv);
574 cpu->gprs[rd] = r;
575 ARM_LOAD_POST_BODY;)
576
577DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
578 enum PrivilegeMode priv = cpu->privilegeMode;
579 int32_t r = cpu->gprs[rd];
580 ARMSetPrivilegeMode(cpu, MODE_USER);
581 cpu->memory.store8(cpu, address, r, ¤tCycles);
582 ARMSetPrivilegeMode(cpu, priv);
583 ARM_STORE_POST_BODY;)
584
585DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
586 enum PrivilegeMode priv = cpu->privilegeMode;
587 int32_t r = cpu->gprs[rd];
588 ARMSetPrivilegeMode(cpu, MODE_USER);
589 cpu->memory.store32(cpu, address, r, ¤tCycles);
590 ARMSetPrivilegeMode(cpu, priv);
591 ARM_STORE_POST_BODY;)
592
593DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
594 load,
595 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
596 if (rs & 0x8000) {
597 ARM_WRITE_PC;
598 })
599
600DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
601 store,
602 ARM_STORE_POST_BODY;)
603
604DEFINE_INSTRUCTION_ARM(SWP,
605 int rm = opcode & 0xF;
606 int rd = (opcode >> 12) & 0xF;
607 int rn = (opcode >> 16) & 0xF;
608 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
609 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
610 cpu->gprs[rd] = d;)
611
612DEFINE_INSTRUCTION_ARM(SWPB,
613 int rm = opcode & 0xF;
614 int rd = (opcode >> 12) & 0xF;
615 int rn = (opcode >> 16) & 0xF;
616 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
617 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
618 cpu->gprs[rd] = d;)
619
620// End load/store definitions
621
622// Begin branch definitions
623
624DEFINE_INSTRUCTION_ARM(B,
625 int32_t offset = opcode << 8;
626 offset >>= 6;
627 cpu->gprs[ARM_PC] += offset;
628 ARM_WRITE_PC;)
629
630DEFINE_INSTRUCTION_ARM(BL,
631 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
632 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
633 cpu->gprs[ARM_PC] += immediate >> 6;
634 ARM_WRITE_PC;)
635
636DEFINE_INSTRUCTION_ARM(BX,
637 int rm = opcode & 0x0000000F;
638 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
639 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
640 if (cpu->executionMode == MODE_THUMB) {
641 THUMB_WRITE_PC;
642 } else {
643 ARM_WRITE_PC;
644 })
645
646// End branch definitions
647
648// Begin coprocessor definitions
649
650DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
651DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
652DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
653DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
654DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
655
656// Begin miscellaneous definitions
657
658DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
659DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
660
661DEFINE_INSTRUCTION_ARM(MSR,
662 int c = opcode & 0x00010000;
663 int f = opcode & 0x00080000;
664 int32_t operand = cpu->gprs[opcode & 0x0000000F];
665 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
666 if (mask & PSR_USER_MASK) {
667 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
668 }
669 if (mask & PSR_STATE_MASK) {
670 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
671 }
672 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
673 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
674 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
675 }
676 _ARMReadCPSR(cpu);
677 if (cpu->executionMode == MODE_THUMB) {
678 cpu->prefetch[0] = 0x46C0; // nop
679 cpu->prefetch[1] &= 0xFFFF;
680 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
681 } else {
682 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
683 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
684 })
685
686DEFINE_INSTRUCTION_ARM(MSRR,
687 int c = opcode & 0x00010000;
688 int f = opcode & 0x00080000;
689 int32_t operand = cpu->gprs[opcode & 0x0000000F];
690 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
691 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
692 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
693
694DEFINE_INSTRUCTION_ARM(MRS, \
695 int rd = (opcode >> 12) & 0xF; \
696 cpu->gprs[rd] = cpu->cpsr.packed;)
697
698DEFINE_INSTRUCTION_ARM(MRSR, \
699 int rd = (opcode >> 12) & 0xF; \
700 cpu->gprs[rd] = cpu->spsr.packed;)
701
702DEFINE_INSTRUCTION_ARM(MSRI,
703 int c = opcode & 0x00010000;
704 int f = opcode & 0x00080000;
705 int rotate = (opcode & 0x00000F00) >> 7;
706 int32_t operand = ROR(opcode & 0x000000FF, rotate);
707 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
708 if (mask & PSR_USER_MASK) {
709 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
710 }
711 if (mask & PSR_STATE_MASK) {
712 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
713 }
714 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
715 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
716 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
717 }
718 _ARMReadCPSR(cpu);
719 if (cpu->executionMode == MODE_THUMB) {
720 cpu->prefetch[0] = 0x46C0; // nop
721 cpu->prefetch[1] &= 0xFFFF;
722 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
723 } else {
724 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
725 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
726 })
727
728DEFINE_INSTRUCTION_ARM(MSRRI,
729 int c = opcode & 0x00010000;
730 int f = opcode & 0x00080000;
731 int rotate = (opcode & 0x00000F00) >> 7;
732 int32_t operand = ROR(opcode & 0x000000FF, rotate);
733 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
734 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
735 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
736
737DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
738
739const ARMInstruction _armTable[0x1000] = {
740 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
741};