src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
24
25#define THUMB_NEUTRAL_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D);
28
29#define APPLY(F, ...) F(__VA_ARGS__)
30
31#define COUNT_1(EMITTER, PREFIX, ...) \
32 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
33 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
34
35#define COUNT_2(EMITTER, PREFIX, ...) \
36 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
37 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
38 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
39
40#define COUNT_3(EMITTER, PREFIX, ...) \
41 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
42 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
43 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
44 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
45 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
46
47#define COUNT_4(EMITTER, PREFIX, ...) \
48 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
50 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
51 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
52 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
53 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
54 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
55 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
56 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
57
58#define COUNT_5(EMITTER, PREFIX, ...) \
59 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
60 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
61 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
62 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
63 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
64 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
65 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
66 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
67 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
68 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
69 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
70 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
71 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
72 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
73 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
74 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
75 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
76
77#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
78 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
79 BODY; \
80 }
81
82#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
83 DEFINE_INSTRUCTION_THUMB(NAME, \
84 int immediate = IMMEDIATE; \
85 int rd = opcode & 0x0007; \
86 int rm = (opcode >> 3) & 0x0007; \
87 BODY;)
88
89#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
90 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
91
92DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
93 if (!immediate) { \
94 cpu->gprs[rd] = cpu->gprs[rm]; \
95 } else { \
96 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
97 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
98 } \
99 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
100
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
102 if (!immediate) { \
103 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
104 cpu->gprs[rd] = 0; \
105 } else { \
106 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
107 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
108 } \
109 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
110
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
112
113DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
114DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
115DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
116DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
117DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
118DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
119
120#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
121 DEFINE_INSTRUCTION_THUMB(NAME, \
122 int rm = RM; \
123 BODY;)
124
125#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
126 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
127
128DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
129DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
130
131#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
132 DEFINE_INSTRUCTION_THUMB(NAME, \
133 int immediate = IMMEDIATE; \
134 int rd = opcode & 0x0007; \
135 int rn = (opcode >> 3) & 0x0007; \
136 BODY;)
137
138#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
139 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
140
141DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, \
142 int n = cpu->gprs[rn]; \
143 cpu->gprs[rd] = n + immediate; \
144 THUMB_ADDITION_S(n, immediate, cpu->gprs[rd]))
145
146DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
147
148#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
149 DEFINE_INSTRUCTION_THUMB(NAME, \
150 int rd = RD; \
151 int immediate = opcode & 0x00FF; \
152 BODY;)
153
154#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
155 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
156
157DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, \
158 int d = cpu->gprs[rd]; \
159 cpu->gprs[rd] = d + immediate; \
160 THUMB_ADDITION_S(d, immediate, cpu->gprs[rd]))
161
162DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
163DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
164DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
165
166#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
167 DEFINE_INSTRUCTION_THUMB(NAME, \
168 int rd = opcode & 0x0007; \
169 int rn = (opcode >> 3) & 0x0007; \
170 BODY;)
171
172DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
173DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
174DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
175DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
176DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
177DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
178DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
179DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
180DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
181DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
182DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
183DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
184DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
185DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
186DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
187DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
188
189#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
190 DEFINE_INSTRUCTION_THUMB(NAME, \
191 int rd = opcode & 0x0007 | H1; \
192 int rm = (opcode >> 3) & 0x0007 | H2; \
193 BODY;)
194
195#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
196 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
197 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
198 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
199 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
200
201DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
202DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
203DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
204
205#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
206 DEFINE_INSTRUCTION_THUMB(NAME, \
207 int rd = RD; \
208 int immediate = (opcode & 0x00FF) << 2; \
209 BODY;)
210
211#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
212 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
213
214DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
215DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
216DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
217
218DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
219DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
220
221#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
222 DEFINE_INSTRUCTION_THUMB(NAME, \
223 int rm = RM; \
224 BODY;)
225
226#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
227 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
228
229DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
230DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
231DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
232DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
233DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
234DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
235DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
236DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
237
238#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
239 DEFINE_INSTRUCTION_THUMB(NAME, \
240 int rn = (opcode >> 8) & 0x000F; \
241 int rs = RS; \
242 int32_t address = ADDRESS; \
243 int m; \
244 int i; \
245 PRE_BODY; \
246 for LOOP { \
247 if (rs & m) { \
248 BODY; \
249 address OP 4; \
250 } \
251 } \
252 POST_BODY; \
253 WRITEBACK;)
254
255#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
256 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
257
258DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
259 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
260 if (!((1 << rn) & rs)) { \
261 cpu->gprs[rn] = address; \
262 })
263
264DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
265 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
266 cpu->gprs[rn] = address)
267
268#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
269 DEFINE_INSTRUCTION_THUMB(B ## COND, \
270 if (ARM_COND_ ## COND) { \
271 ARM_STUB; \
272 })
273
274DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
275DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
276DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
277DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
278DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
279DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
280DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
281DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
282DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
283DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
284DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
285DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
286DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
287DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
288
289DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
290DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
291
292DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
293 opcode & 0x00FF, \
294 cpu->gprs[ARM_SP], \
295 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
296 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
297 +=, \
298 , , \
299 cpu->gprs[ARM_SP] = address)
300
301DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
302 opcode & 0x00FF, \
303 cpu->gprs[ARM_SP], \
304 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
305 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
306 +=, \
307 , \
308 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
309 address += 4;, \
310 cpu->gprs[ARM_SP] = address)
311
312DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
313 opcode & 0x00FF, \
314 cpu->gprs[ARM_SP] - 4, \
315 (m = 0x80, i = 7; m; m >>= 1, --i), \
316 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
317 -=, \
318 , , \
319 cpu->gprs[ARM_SP] = address + 4)
320
321DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
322 opcode & 0x00FF, \
323 cpu->gprs[ARM_SP] - 4, \
324 (m = 0x80, i = 7; m; m >>= 1, --i), \
325 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
326 -=, \
327 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
328 address -= 4;, \
329 , \
330 cpu->gprs[ARM_SP] = address + 4)
331
332DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
333DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
334DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
335DEFINE_INSTRUCTION_THUMB(BL1, \
336 int16_t immediate = (opcode & 0x07FF) << 7; \
337 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 5);)
338
339DEFINE_INSTRUCTION_THUMB(BL2, \
340 uint16_t immediate = (opcode & 0x07FF) << 1; \
341 uint32_t pc = cpu->gprs[ARM_PC]; \
342 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
343 cpu->gprs[ARM_LR] = pc - 1; \
344 THUMB_WRITE_PC;)
345
346DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
347DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
348
349#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
350 EMITTER ## NAME
351
352#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
353 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
354 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
355 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
356 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
357
358#define DUMMY(X, ...) X,
359#define DUMMY_4(...) \
360 DUMMY(__VA_ARGS__) \
361 DUMMY(__VA_ARGS__) \
362 DUMMY(__VA_ARGS__) \
363 DUMMY(__VA_ARGS__)
364
365#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
366 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
367 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
368 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
369 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
370 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
371 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
372 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
373 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
374 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
375 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
376 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
377 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
378 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
379 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
380 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
381 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
382 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
383 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
384 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
385 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
386 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
387 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
388 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
389 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
390 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
391 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
392 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
393 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
394 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
395 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
396 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
397 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
398 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
399 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
400 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
401 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
402 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
403 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
404 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
405 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
406 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
407 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
408 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
409 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
410 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
411 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
412 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
413 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
414 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
415 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
416 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
417 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
418 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
419 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
420 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
421 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
422 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
423 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
424 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
425 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
426 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
427 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
428 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
429 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
430 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
431 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
432 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
433 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
434 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
435 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
436 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
437 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
438 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
439 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
440 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
441 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
442 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
443 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
444 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
445 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
446 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
447 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
448 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
449 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
450 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
451 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
452 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
453 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
454 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
455 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
456 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
457
458static const ThumbInstruction _thumbTable[0x400] = {
459 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
460};