src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 ARMPSR cpsr = 0; \
194 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
195 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
196 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM(M, N, D)); \
197 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
198 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
199 }
200
201#define ARM_ADDITION_CARRY_S(M, N, D, C) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 ARMPSR cpsr = 0; \
207 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
208 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
209 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM_CARRY(M, N, D, C)); \
210 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
211 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
212 }
213
214#define ARM_SUBTRACTION_S(M, N, D) \
215 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
216 cpu->cpsr = cpu->spsr; \
217 _ARMReadCPSR(cpu); \
218 } else { \
219 ARMPSR cpsr = 0; \
220 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
221 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
222 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM(M, N, D)); \
223 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
224 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
225 }
226
227#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
228 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
229 cpu->cpsr = cpu->spsr; \
230 _ARMReadCPSR(cpu); \
231 } else { \
232 ARMPSR cpsr = 0; \
233 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
234 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
235 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM_CARRY(M, N, D, C)); \
236 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
237 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
238 }
239
240#define ARM_NEUTRAL_S(M, N, D) \
241 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
242 cpu->cpsr = cpu->spsr; \
243 _ARMReadCPSR(cpu); \
244 } else { \
245 ARMPSR cpsr = 0; \
246 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
247 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
248 cpsr = ARMPSROrUnsafeC(cpsr, cpu->shifterCarryOut); \
249 cpu->cpsr = (cpu->cpsr & (0x1FFFFFFF)) | cpsr; \
250 }
251
252#define ARM_NEUTRAL_HI_S(DLO, DHI) \
253 { \
254 ARMPSR cpsr = 0; \
255 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(DHI)); \
256 cpsr = ARMPSROrUnsafeZ(cpsr, !((DHI) | (DLO))); \
257 cpu->cpsr = (cpu->cpsr & (0x3FFFFFFF)) | cpsr; \
258 }
259
260#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
261#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
262#define ADDR_MODE_2_ADDRESS (address)
263#define ADDR_MODE_2_RN (cpu->gprs[rn])
264#define ADDR_MODE_2_RM (cpu->gprs[rm])
265#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
266#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
267#define ADDR_MODE_2_WRITEBACK(ADDR) \
268 cpu->gprs[rn] = ADDR; \
269 if (UNLIKELY(rn == ARM_PC)) { \
270 ARM_WRITE_PC; \
271 }
272
273#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
274#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
275#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
276#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
277
278#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
279#define ADDR_MODE_3_RN ADDR_MODE_2_RN
280#define ADDR_MODE_3_RM ADDR_MODE_2_RM
281#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
282#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
283#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
284
285#define ADDR_MODE_4_WRITEBACK_LDM \
286 if (!((1 << rn) & rs)) { \
287 cpu->gprs[rn] = address; \
288 }
289
290#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
291
292#define ARM_LOAD_POST_BODY \
293 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
294 if (rd == ARM_PC) { \
295 ARM_WRITE_PC; \
296 }
297
298#define ARM_STORE_POST_BODY \
299 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
300
301#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
302 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
303 int currentCycles = ARM_PREFETCH_CYCLES; \
304 BODY; \
305 cpu->cycles += currentCycles; \
306 }
307
308#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
309 DEFINE_INSTRUCTION_ARM(NAME, \
310 int rd = (opcode >> 12) & 0xF; \
311 int rn = (opcode >> 16) & 0xF; \
312 UNUSED(rn); \
313 SHIFTER(cpu, opcode); \
314 BODY; \
315 S_BODY; \
316 if (rd == ARM_PC) { \
317 if (cpu->executionMode == MODE_ARM) { \
318 ARM_WRITE_PC; \
319 } else { \
320 THUMB_WRITE_PC; \
321 } \
322 })
323
324#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
335
336#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
342
343#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
344 DEFINE_INSTRUCTION_ARM(NAME, \
345 int rd = (opcode >> 16) & 0xF; \
346 int rs = (opcode >> 8) & 0xF; \
347 int rm = opcode & 0xF; \
348 if (rd == ARM_PC) { \
349 return; \
350 } \
351 ARM_WAIT_MUL(cpu->gprs[rs]); \
352 BODY; \
353 S_BODY; \
354 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
355
356#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
357 DEFINE_INSTRUCTION_ARM(NAME, \
358 int rd = (opcode >> 12) & 0xF; \
359 int rdHi = (opcode >> 16) & 0xF; \
360 int rs = (opcode >> 8) & 0xF; \
361 int rm = opcode & 0xF; \
362 if (rdHi == ARM_PC || rd == ARM_PC) { \
363 return; \
364 } \
365 currentCycles += cpu->memory.stall(cpu, WAIT); \
366 BODY; \
367 S_BODY; \
368 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
369
370#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
371 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
372 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
373
374#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
375 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
376 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
377
378#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
379 DEFINE_INSTRUCTION_ARM(NAME, \
380 uint32_t address; \
381 int rn = (opcode >> 16) & 0xF; \
382 int rd = (opcode >> 12) & 0xF; \
383 int rm = opcode & 0xF; \
384 UNUSED(rm); \
385 address = ADDRESS; \
386 WRITEBACK; \
387 BODY;)
388
389#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
396
397#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
408
409#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
422
423#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
424 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
425 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
426
427#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
428 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
429 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
430 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
431 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
433 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
434
435#define ARM_MS_PRE \
436 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
437 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
438
439#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
440
441#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
442 DEFINE_INSTRUCTION_ARM(NAME, \
443 int rn = (opcode >> 16) & 0xF; \
444 int rs = opcode & 0x0000FFFF; \
445 uint32_t address = cpu->gprs[rn]; \
446 S_PRE; \
447 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
448 S_POST; \
449 POST_BODY; \
450 WRITEBACK;)
451
452
453#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
464 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
465 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
469 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
470
471// Begin ALU definitions
472
473DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
474 int32_t n = cpu->gprs[rn];
475 cpu->gprs[rd] = n + cpu->shifterOperand;)
476
477DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], ARMPSRGetC(cpu->cpsr)),
478 int32_t n = cpu->gprs[rn];
479 cpu->gprs[rd] = n + cpu->shifterOperand + ARMPSRGetC(cpu->cpsr);)
480
481DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
482 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
483
484DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
485 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
486
487DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
488 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
489
490DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
491 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
492
493DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
494 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
495
496DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
497 cpu->gprs[rd] = cpu->shifterOperand;)
498
499DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
500 cpu->gprs[rd] = ~cpu->shifterOperand;)
501
502DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
503 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
504
505DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
506 int32_t n = cpu->gprs[rn];
507 cpu->gprs[rd] = cpu->shifterOperand - n;)
508
509DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
510 int32_t n = cpu->gprs[rn];
511 cpu->gprs[rd] = cpu->shifterOperand - n - !ARMPSRIsC(cpu->cpsr);)
512
513DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
514 int32_t n = cpu->gprs[rn];
515 cpu->gprs[rd] = n - cpu->shifterOperand - !ARMPSRIsC(cpu->cpsr);)
516
517DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
518 int32_t n = cpu->gprs[rn];
519 cpu->gprs[rd] = n - cpu->shifterOperand;)
520
521DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
522 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
523
524DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
525 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
526
527// End ALU definitions
528
529// Begin multiply definitions
530
531DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
532DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
533
534DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
535 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
536 int32_t dm = cpu->gprs[rd];
537 int32_t dn = d;
538 cpu->gprs[rd] = dm + dn;
539 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
540 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
541
542DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
543 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
544 cpu->gprs[rd] = d;
545 cpu->gprs[rdHi] = d >> 32;,
546 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
547
548DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
549 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
550 int32_t dm = cpu->gprs[rd];
551 int32_t dn = d;
552 cpu->gprs[rd] = dm + dn;
553 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
554 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
555
556DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
557 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
558 cpu->gprs[rd] = d;
559 cpu->gprs[rdHi] = d >> 32;,
560 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
561
562// End multiply definitions
563
564// Begin load/store definitions
565
566DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
567DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
568DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
569DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
570DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
571DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
572DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
573DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
574
575DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
576 enum PrivilegeMode priv = cpu->privilegeMode;
577 ARMSetPrivilegeMode(cpu, MODE_USER);
578 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
579 ARMSetPrivilegeMode(cpu, priv);
580 cpu->gprs[rd] = r;
581 ARM_LOAD_POST_BODY;)
582
583DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
584 enum PrivilegeMode priv = cpu->privilegeMode;
585 ARMSetPrivilegeMode(cpu, MODE_USER);
586 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
587 ARMSetPrivilegeMode(cpu, priv);
588 cpu->gprs[rd] = r;
589 ARM_LOAD_POST_BODY;)
590
591DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
592 enum PrivilegeMode priv = cpu->privilegeMode;
593 int32_t r = cpu->gprs[rd];
594 ARMSetPrivilegeMode(cpu, MODE_USER);
595 cpu->memory.store8(cpu, address, r, ¤tCycles);
596 ARMSetPrivilegeMode(cpu, priv);
597 ARM_STORE_POST_BODY;)
598
599DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
600 enum PrivilegeMode priv = cpu->privilegeMode;
601 int32_t r = cpu->gprs[rd];
602 ARMSetPrivilegeMode(cpu, MODE_USER);
603 cpu->memory.store32(cpu, address, r, ¤tCycles);
604 ARMSetPrivilegeMode(cpu, priv);
605 ARM_STORE_POST_BODY;)
606
607DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
608 load,
609 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
610 if (rs & 0x8000) {
611 ARM_WRITE_PC;
612 })
613
614DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
615 store,
616 ARM_STORE_POST_BODY;)
617
618DEFINE_INSTRUCTION_ARM(SWP,
619 int rm = opcode & 0xF;
620 int rd = (opcode >> 12) & 0xF;
621 int rn = (opcode >> 16) & 0xF;
622 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
623 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
624 cpu->gprs[rd] = d;)
625
626DEFINE_INSTRUCTION_ARM(SWPB,
627 int rm = opcode & 0xF;
628 int rd = (opcode >> 12) & 0xF;
629 int rn = (opcode >> 16) & 0xF;
630 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
631 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
632 cpu->gprs[rd] = d;)
633
634// End load/store definitions
635
636// Begin branch definitions
637
638DEFINE_INSTRUCTION_ARM(B,
639 int32_t offset = opcode << 8;
640 offset >>= 6;
641 cpu->gprs[ARM_PC] += offset;
642 ARM_WRITE_PC;)
643
644DEFINE_INSTRUCTION_ARM(BL,
645 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
646 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
647 cpu->gprs[ARM_PC] += immediate >> 6;
648 ARM_WRITE_PC;)
649
650DEFINE_INSTRUCTION_ARM(BX,
651 int rm = opcode & 0x0000000F;
652 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
653 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
654 if (cpu->executionMode == MODE_THUMB) {
655 THUMB_WRITE_PC;
656 } else {
657 ARM_WRITE_PC;
658
659 })
660DEFINE_INSTRUCTION_ARM(BLX2,
661 int rm = opcode & 0x0000000F;
662 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
663 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
664 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
665 if (cpu->executionMode == MODE_THUMB) {
666 THUMB_WRITE_PC;
667 } else {
668 ARM_WRITE_PC;
669 })
670
671// End branch definitions
672
673// Begin coprocessor definitions
674
675#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
676 DEFINE_INSTRUCTION_ARM(NAME, \
677 int op1 = (opcode >> 21) & 7; \
678 int op2 = (opcode >> 5) & 7; \
679 int rd = (opcode >> 12) & 0xF; \
680 int cp = (opcode >> 8) & 0xF; \
681 int crn = (opcode >> 16) & 0xF; \
682 int crm = opcode & 0xF; \
683 UNUSED(op1); \
684 UNUSED(op2); \
685 UNUSED(rd); \
686 UNUSED(crn); \
687 UNUSED(crm); \
688 BODY;)
689
690DEFINE_COPROCESSOR_INSTRUCTION(MRC,
691 if (cp == 15 && cpu->irqh.readCP15) {
692 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
693 } else {
694 ARM_STUB;
695 })
696
697DEFINE_COPROCESSOR_INSTRUCTION(MCR,
698 if (cp == 15 && cpu->irqh.writeCP15) {
699 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
700 } else {
701 ARM_STUB;
702 })
703
704DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
705DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
706DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
707
708// Begin miscellaneous definitions
709
710DEFINE_INSTRUCTION_ARM(CLZ,
711 int rm = opcode & 0xF;
712 int rd = (opcode >> 12) & 0xF;
713 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
714
715DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
716DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
717
718DEFINE_INSTRUCTION_ARM(MSR,
719 int c = opcode & 0x00010000;
720 int f = opcode & 0x00080000;
721 int32_t operand = cpu->gprs[opcode & 0x0000000F];
722 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
723 if (mask & PSR_USER_MASK) {
724 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
725 }
726 if (mask & PSR_STATE_MASK) {
727 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
728 }
729 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
730 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
731 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
732 }
733 _ARMReadCPSR(cpu);
734 if (cpu->executionMode == MODE_THUMB) {
735 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
736 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
737 } else {
738 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
739 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
740 })
741
742DEFINE_INSTRUCTION_ARM(MSRR,
743 int c = opcode & 0x00010000;
744 int f = opcode & 0x00080000;
745 int32_t operand = cpu->gprs[opcode & 0x0000000F];
746 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
747 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
748 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
749
750DEFINE_INSTRUCTION_ARM(MRS, \
751 int rd = (opcode >> 12) & 0xF; \
752 cpu->gprs[rd] = cpu->cpsr;)
753
754DEFINE_INSTRUCTION_ARM(MRSR, \
755 int rd = (opcode >> 12) & 0xF; \
756 cpu->gprs[rd] = cpu->spsr;)
757
758DEFINE_INSTRUCTION_ARM(MSRI,
759 int c = opcode & 0x00010000;
760 int f = opcode & 0x00080000;
761 int rotate = (opcode & 0x00000F00) >> 7;
762 int32_t operand = ROR(opcode & 0x000000FF, rotate);
763 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
764 if (mask & PSR_USER_MASK) {
765 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
766 }
767 if (mask & PSR_STATE_MASK) {
768 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
769 }
770 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
771 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
772 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
773 }
774 _ARMReadCPSR(cpu);
775 if (cpu->executionMode == MODE_THUMB) {
776 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
777 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
778 } else {
779 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
780 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
781 })
782
783DEFINE_INSTRUCTION_ARM(MSRRI,
784 int c = opcode & 0x00010000;
785 int f = opcode & 0x00080000;
786 int rotate = (opcode & 0x00000F00) >> 7;
787 int32_t operand = ROR(opcode & 0x000000FF, rotate);
788 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
789 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
790 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
791
792DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
793
794const ARMInstruction _armv4Table[0x1000] = {
795 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
796};
797
798const ARMInstruction _armv5Table[0x1000] = {
799 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
800};