src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18#define SLICE_CYCLES 2048
19
20mLOG_DEFINE_CATEGORY(DS, "DS");
21
22const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
23const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
24const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
25
26static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
27static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
28
29enum {
30 DS7_SP_BASE = 0x380FD80,
31 DS7_SP_BASE_IRQ = 0x380FF80,
32 DS7_SP_BASE_SVC = 0x380FFC0,
33
34 DS9_SP_BASE = 0x3002F7C,
35 DS9_SP_BASE_IRQ = 0x3003F80,
36 DS9_SP_BASE_SVC = 0x3003FC0,
37};
38
39static void DSInit(void* cpu, struct mCPUComponent* component);
40
41static void DS7Reset(struct ARMCore* cpu);
42static void DS7TestIRQ(struct ARMCore* cpu);
43static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44static void DS7ProcessEvents(struct ARMCore* cpu);
45
46static void DS9Reset(struct ARMCore* cpu);
47static void DS9TestIRQ(struct ARMCore* cpu);
48static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
49static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
50static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
51static void DS9ProcessEvents(struct ARMCore* cpu);
52
53static void DSProcessEvents(struct DSCommon* dscore);
54static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
55static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
56static void DSBreakpoint(struct ARMCore* cpu, int immediate);
57
58static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
59 UNUSED(cyclesLate);
60 struct DS* ds = context;
61 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
62 if (ds->activeCpu == ds->ds9.cpu) {
63 ds->activeCpu = ds->ds7.cpu;
64 ds->cycleDrift += cycles;
65 cycles = ds->cycleDrift >> 1;
66 timing = &ds->ds7.timing;
67 } else {
68 ds->activeCpu = ds->ds9.cpu;
69 ds->cycleDrift -= cycles << 1;
70 cycles = ds->cycleDrift + SLICE_CYCLES;
71 timing = &ds->ds9.timing;
72 }
73 mTimingSchedule(timing, &ds->slice, cycles);
74 ds->sliceStart = mTimingCurrentTime(timing);
75}
76
77void DSCreate(struct DS* ds) {
78 ds->d.id = DS_COMPONENT_MAGIC;
79 ds->d.init = DSInit;
80 ds->d.deinit = NULL;
81 ds->ds7.p = ds;
82 ds->ds9.p = ds;
83 ds->ds7.cpu = NULL;
84 ds->ds9.cpu = NULL;
85 ds->ds7.ipc = &ds->ds9;
86 ds->ds9.ipc = &ds->ds7;
87}
88
89static void DSInit(void* cpu, struct mCPUComponent* component) {
90 struct DS* ds = (struct DS*) component;
91 struct ARMCore* core = cpu;
92 if (!ds->ds7.cpu) {
93 // The ARM7 must get initialized first
94 ds->ds7.cpu = core;
95 ds->debugger = 0;
96 ds->sync = 0;
97 return;
98 }
99 ds->ds9.cpu = cpu;
100 ds->activeCpu = NULL;
101
102 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
103
104 ds->slice.name = "DS CPU Time Slicing";
105 ds->slice.callback = _slice;
106 ds->slice.context = ds;
107 ds->slice.priority = UINT_MAX;
108
109 CircleBufferInit(&ds->ds7.fifo, 64);
110 CircleBufferInit(&ds->ds9.fifo, 64);
111
112 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
113 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
114 DSMemoryInit(ds);
115 DSDMAInit(ds);
116
117 ds->video.p = ds;
118
119 ds->ds7.springIRQ = 0;
120 ds->ds9.springIRQ = 0;
121 DSTimerInit(ds);
122 ds->keySource = NULL;
123 ds->rtcSource = NULL;
124 ds->rumble = NULL;
125
126 ds->romVf = NULL;
127
128 ds->keyCallback = NULL;
129
130 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
131 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
132}
133
134void DSUnloadROM(struct DS* ds) {
135 if (ds->romVf) {
136 ds->romVf->close(ds->romVf);
137 ds->romVf = NULL;
138 }
139}
140
141void DSDestroy(struct DS* ds) {
142 CircleBufferDeinit(&ds->ds7.fifo);
143 CircleBufferDeinit(&ds->ds9.fifo);
144 DSUnloadROM(ds);
145 DSMemoryDeinit(ds);
146 mTimingDeinit(&ds->ds7.timing);
147 mTimingDeinit(&ds->ds9.timing);
148}
149
150void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
151 irqh->reset = DS7Reset;
152 irqh->processEvents = DS7ProcessEvents;
153 irqh->swi16 = DS7Swi16;
154 irqh->swi32 = DS7Swi32;
155 irqh->hitIllegal = DSIllegal;
156 irqh->readCPSR = DS7TestIRQ;
157 irqh->writeCP15 = NULL;
158 irqh->readCP15 = NULL;
159 irqh->hitStub = DSHitStub;
160 irqh->bkpt16 = DSBreakpoint;
161 irqh->bkpt32 = DSBreakpoint;
162}
163
164void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
165 irqh->reset = DS9Reset;
166 irqh->processEvents = DS9ProcessEvents;
167 irqh->swi16 = NULL;
168 irqh->swi32 = NULL;
169 irqh->hitIllegal = DSIllegal;
170 irqh->readCPSR = DS9TestIRQ;
171 irqh->writeCP15 = DS9WriteCP15;
172 irqh->readCP15 = DS9ReadCP15;
173 irqh->hitStub = DSHitStub;
174 irqh->bkpt16 = DSBreakpoint;
175 irqh->bkpt32 = DSBreakpoint;
176}
177
178void DS7Reset(struct ARMCore* cpu) {
179 ARMSetPrivilegeMode(cpu, MODE_IRQ);
180 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
181 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
182 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
183 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
184 cpu->gprs[ARM_SP] = DS7_SP_BASE;
185
186 struct DS* ds = (struct DS*) cpu->master;
187 mTimingClear(&ds->ds7.timing);
188 CircleBufferInit(&ds->ds7.fifo, 64);
189 DSMemoryReset(ds);
190 DSDMAReset(&ds->ds7);
191 DS7IOInit(ds);
192
193 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
194 if (header) {
195 // TODO: Error check
196 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
197 uint32_t base = header->arm7Base - DS_BASE_RAM;
198 uint32_t* basePointer = &ds->memory.ram[base >> 2];
199 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
200 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
201 }
202 cpu->gprs[12] = header->arm7Entry;
203 cpu->gprs[ARM_LR] = header->arm7Entry;
204 cpu->gprs[ARM_PC] = header->arm7Entry;
205 int currentCycles = 0;
206 ARM_WRITE_PC;
207
208 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
209 }
210}
211
212void DS9Reset(struct ARMCore* cpu) {
213 ARMSetPrivilegeMode(cpu, MODE_IRQ);
214 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
215 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
216 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
217 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
218 cpu->gprs[ARM_SP] = DS9_SP_BASE;
219
220 struct DS* ds = (struct DS*) cpu->master;
221 mTimingClear(&ds->ds9.timing);
222 CircleBufferInit(&ds->ds9.fifo, 64);
223 DSDMAReset(&ds->ds9);
224 DS9IOInit(ds);
225
226 ds->activeCpu = cpu;
227 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
228 ds->cycleDrift = 0;
229 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
230
231 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
232 if (header) {
233 // TODO: Error check
234 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
235 uint32_t base = header->arm9Base - DS_BASE_RAM;
236 uint32_t* basePointer = &ds->memory.ram[base >> 2];
237 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
238 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
239 }
240 cpu->gprs[12] = header->arm9Entry;
241 cpu->gprs[ARM_LR] = header->arm9Entry;
242 cpu->gprs[ARM_PC] = header->arm9Entry;
243 int currentCycles = 0;
244 ARM_WRITE_PC;
245
246 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
247 }
248}
249
250static void DS7ProcessEvents(struct ARMCore* cpu) {
251 struct DS* ds = (struct DS*) cpu->master;
252 DSProcessEvents(&ds->ds7);
253}
254
255static void DS9ProcessEvents(struct ARMCore* cpu) {
256 struct DS* ds = (struct DS*) cpu->master;
257 DSProcessEvents(&ds->ds9);
258}
259
260static void DSProcessEvents(struct DSCommon* dscore) {
261 struct ARMCore* cpu = dscore->cpu;
262 struct DS* ds = dscore->p;
263 if (dscore->springIRQ && !ARMPSRGetI(cpu->cpsr)) {
264 ARMRaiseIRQ(cpu);
265 dscore->springIRQ = 0;
266 }
267
268 int32_t nextEvent = cpu->nextEvent;
269 while (cpu->cycles >= nextEvent) {
270 int32_t cycles = cpu->cycles;
271
272 cpu->cycles = 0;
273 cpu->nextEvent = INT_MAX;
274
275#ifndef NDEBUG
276 if (cycles < 0) {
277 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
278 }
279#endif
280 nextEvent = cycles;
281 do {
282 nextEvent = mTimingTick(&dscore->timing, nextEvent);
283 } while (ds->cpuBlocked);
284
285 cpu->nextEvent = nextEvent;
286
287 if (ds->earlyExit) {
288 ds->earlyExit = false;
289 break;
290 }
291 if (cpu->halted) {
292 cpu->cycles = nextEvent;
293 }
294#ifndef NDEBUG
295 else if (nextEvent < 0) {
296 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
297 }
298#endif
299 }
300}
301
302void DSRunLoop(struct DS* ds) {
303 if (ds->activeCpu == ds->ds9.cpu) {
304 ARMv5RunLoop(ds->ds9.cpu);
305 } else {
306 ARMv4RunLoop(ds->ds7.cpu);
307 }
308}
309
310void DS7Step(struct DS* ds) {
311 while (ds->activeCpu == ds->ds9.cpu) {
312 ARMv5RunLoop(ds->ds9.cpu);
313 }
314 ARMv4Run(ds->ds7.cpu);
315}
316
317void DS9Step(struct DS* ds) {
318 while (ds->activeCpu == ds->ds7.cpu) {
319 ARMv4RunLoop(ds->ds7.cpu);
320 }
321 ARMv5Run(ds->ds9.cpu);
322}
323
324void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
325 ds->debugger = (struct ARMDebugger*) debugger->platform;
326 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
327 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
328 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
329 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
330}
331
332void DSDetachDebugger(struct DS* ds) {
333 ds->debugger = NULL;
334 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
335 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
336 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
337 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
338}
339
340bool DSLoadROM(struct DS* ds, struct VFile* vf) {
341 DSUnloadROM(ds);
342 ds->romVf = vf;
343 // TODO: error check
344 return true;
345}
346
347bool DSIsROM(struct VFile* vf) {
348 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
349 return false;
350 }
351 uint8_t signature[sizeof(DS_ROM_MAGIC)];
352 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
353 return false;
354 }
355 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
356}
357
358bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
359 size_t size = vf->size(vf);
360 void* data = NULL;
361 uint32_t crc;
362 if (size == DS7_SIZE_BIOS) {
363 data = vf->map(vf, size, MAP_READ);
364 } else if (size == 0x1000) {
365 data = vf->map(vf, size, MAP_READ);
366 }
367 if (!data) {
368 return false;
369 }
370 crc = doCrc32(data, size);
371 if (crc == DS7_BIOS_CHECKSUM) {
372 ds->bios7Vf = vf;
373 ds->memory.bios7 = data;
374 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
375 } else if (crc == DS9_BIOS_CHECKSUM) {
376 ds->bios9Vf = vf;
377 ds->memory.bios9 = data;
378 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
379 } else {
380 mLOG(DS, WARN, "BIOS checksum incorrect");
381 vf->unmap(vf, data, size);
382 return false;
383 }
384 return true;
385}
386
387void DSGetGameCode(struct DS* ds, char* out) {
388 memset(out, 0, 8);
389 if (!ds->romVf) {
390 return;
391 }
392
393 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
394 memcpy(out, "NTR-", 4);
395 memcpy(&out[4], &cart->id, 4);
396 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
397}
398
399void DSGetGameTitle(struct DS* ds, char* out) {
400 memset(out, 0, 12);
401 if (!ds->romVf) {
402 return;
403 }
404
405 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
406 memcpy(out, &cart->title, 4);
407 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
408}
409
410void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
411 struct DS* ds = (struct DS*) cpu->master;
412 if (ds->debugger) {
413 struct mDebuggerEntryInfo info = {
414 .address = _ARMPCAddress(cpu),
415 .opcode = opcode
416 };
417 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
418 }
419 // TODO: More sensible category?
420 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
421}
422
423void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
424 struct DS* ds = (struct DS*) cpu->master;
425 if (ds->debugger) {
426 struct mDebuggerEntryInfo info = {
427 .address = _ARMPCAddress(cpu),
428 .opcode = opcode
429 };
430 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
431 } else {
432 ARMRaiseUndefined(cpu);
433 }
434}
435
436void DSBreakpoint(struct ARMCore* cpu, int immediate) {
437 struct DS* ds = (struct DS*) cpu->master;
438 if (immediate >= CPU_COMPONENT_MAX) {
439 return;
440 }
441 switch (immediate) {
442 case CPU_COMPONENT_DEBUGGER:
443 if (ds->debugger) {
444 struct mDebuggerEntryInfo info = {
445 .address = _ARMPCAddress(cpu)
446 };
447 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
448 }
449 break;
450 default:
451 break;
452 }
453}
454
455void DS7TestIRQ(struct ARMCore* cpu) {
456 struct DS* ds = (struct DS*) cpu->master;
457 if (0) {
458 ds->ds7.springIRQ = 1;
459 cpu->nextEvent = cpu->cycles;
460 }
461}
462
463void DS9TestIRQ(struct ARMCore* cpu) {
464 struct DS* ds = (struct DS*) cpu->master;
465 if (0) {
466 ds->ds9.springIRQ = 1;
467 cpu->nextEvent = cpu->cycles;
468 }
469}
470
471static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
472 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
473}
474
475static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
476 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
477 switch (opcode2) {
478 case 0:
479 cpu->cp15.r2.d = value;
480 break;
481 case 1:
482 cpu->cp15.r2.i = value;
483 break;
484 default:
485 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
486 break;
487 }
488}
489
490static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
491 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
492 switch (opcode2) {
493 case 0:
494 cpu->cp15.r3.d = value;
495 break;
496 default:
497 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
498 break;
499 }
500}
501
502static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
503 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
504}
505
506static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
507 cpu->cp15.r6.region[crm] = value;
508 uint32_t base = ARMProtectionGetBase(value) << 12;
509 uint32_t size = 2 << ARMProtectionGetSize(value);
510 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
511}
512
513static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
514 switch (crm) {
515 case 0:
516 if (opcode2 == 4) {
517 ARMHalt(cpu);
518 return;
519 }
520 break;
521 }
522 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
523}
524
525static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
526 uint32_t base = ARMTCMControlGetBase(value) << 12;
527 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
528 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
529 switch (opcode2) {
530 case 0:
531 cpu->cp15.r9.d = value;
532 break;
533 case 1:
534 cpu->cp15.r9.i = value;
535 break;
536 default:
537 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
538 break;
539 }
540}
541
542void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
543 switch (crn) {
544 default:
545 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
546 break;
547 case 0:
548 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
549 ARMRaiseUndefined(cpu);
550 break;
551 case 1:
552 _writeSysControl(cpu, crm, opcode2, value);
553 break;
554 case 2:
555 _writeCacheControl(cpu, crm, opcode2, value);
556 break;
557 case 3:
558 _writeWriteBufferControl(cpu, crm, opcode2, value);
559 break;
560 case 5:
561 _writeAccessControl(cpu, crm, opcode2, value);
562 break;
563 case 6:
564 _writeRegionConfiguration(cpu, crm, opcode2, value);
565 break;
566 case 7:
567 _writeCache(cpu, crm, opcode2, value);
568 break;
569 case 9:
570 _writeTCMControl(cpu, crm, opcode2, value);
571 break;
572 }
573}
574
575static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
576 switch (opcode2) {
577 case 0:
578 return cpu->cp15.r9.d;
579 case 1:
580 return cpu->cp15.r9.i;
581 default:
582 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
583 return 0;
584 }
585}
586
587uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
588 switch (crn) {
589 default:
590 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
591 return 0;
592 case 9:
593 return _readTCMControl(cpu, crm, opcode2);
594 }
595}
596
597void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
598 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
599 ARMRaiseIRQ(cpu);
600 }
601}
602void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
603 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
604 ARMRaiseIRQ(cpu);
605 }
606}
607
608void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
609 if (irq < 16) {
610 io[DS_REG_IF_LO >> 1] |= 1 << irq;
611 } else {
612 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
613 }
614
615 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
616 cpu->halted = 0;
617 if (io[DS_REG_IME >> 1]) {
618 ARMRaiseIRQ(cpu);
619 }
620 }
621}