1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm/arm.h"
 12#include "core/log.h"
 13#include "ds/io.h"
 14
 15enum DSMemoryRegion {
 16	DS7_REGION_BIOS = 0x0,
 17	DS9_REGION_ITCM = 0x0,
 18	DS9_REGION_ITCM_MIRROR = 0x1,
 19	DS_REGION_RAM = 0x2,
 20	DS_REGION_WORKING_RAM = 0x3,
 21	DS_REGION_IO = 0x4,
 22	DS9_REGION_PALETTE_RAM = 0x5,
 23	DS_REGION_VRAM = 0x6,
 24	DS9_REGION_OAM = 0x7,
 25	DS_REGION_SLOT2 = 0x8,
 26	DS_REGION_SLOT2_EX = 0x9,
 27	DS_REGION_SLOT2_SRAM = 0xA,
 28	DS9_REGION_BIOS = 0xFF,
 29};
 30
 31enum DSMemoryBase {
 32	DS7_BASE_BIOS = 0x00000000,
 33	DS9_BASE_ITCM = 0x00000000,
 34	DS_BASE_RAM = 0x02000000,
 35	DS_BASE_WORKING_RAM = 0x03000000,
 36	DS7_BASE_WORKING_RAM = 0x03800000,
 37	DS_BASE_IO = 0x04000000,
 38	DS9_BASE_PALETTE_RAM = 0x05000000,
 39	DS_BASE_VRAM = 0x06000000,
 40	DS9_BASE_OAM = 0x07000000,
 41	DS_BASE_SLOT2 = 0x08000000,
 42	DS_BASE_SLOT2_EX = 0x09000000,
 43	DS9_BASE_BIOS = 0xFFFF0000,
 44};
 45
 46enum {
 47	DS9_SIZE_ITCM = 0x00008000,
 48	DS9_SIZE_DTCM = 0x00004000,
 49	DS7_SIZE_BIOS = 0x00004000,
 50	DS9_SIZE_BIOS = 0x00008000,
 51	DS_SIZE_RAM = 0x00400000,
 52	DS_SIZE_WORKING_RAM = 0x00008000,
 53	DS7_SIZE_WORKING_RAM = 0x00010000,
 54	DS9_SIZE_PALETTE_RAM = 0x00000800,
 55	DS9_SIZE_OAM = 0x00000800,
 56	DS_SIZE_SLOT2 = 0x02000000,
 57	DS_SIZE_SLOT2_SRAM = 0x00010000,
 58};
 59
 60enum {
 61	DS_OFFSET_MASK = 0x00FFFFFF,
 62	DS_BASE_OFFSET = 24
 63};
 64
 65enum DSDMAControl {
 66	DS_DMA_INCREMENT = 0,
 67	DS_DMA_DECREMENT = 1,
 68	DS_DMA_FIXED = 2,
 69	DS_DMA_INCREMENT_RELOAD = 3
 70};
 71
 72enum DSDMATiming {
 73	DS_DMA_TIMING_NOW = 0,
 74	DS_DMA_TIMING_VBLANK = 1,
 75	DS_DMA_TIMING_HBLANK = 2,
 76	DS7_DMA_TIMING_SLOT1 = 2,
 77	DS_DMA_TIMING_DISPLAY_START = 3,
 78	DS7_DMA_TIMING_CUSTOM = 3,
 79	DS_DMA_TIMING_MEMORY_DISPLAY = 4,
 80	DS9_DMA_TIMING_SLOT1 = 5,
 81	DS_DMA_TIMING_SLOT2 = 6,
 82	DS_DMA_TIMING_GEOM_FIFO = 7,
 83};
 84
 85mLOG_DECLARE_CATEGORY(DS_MEM);
 86
 87DECL_BITFIELD(DSDMARegister, uint16_t);
 88DECL_BITS(DSDMARegister, DestControl, 5, 2);
 89DECL_BITS(DSDMARegister, SrcControl, 7, 2);
 90DECL_BIT(DSDMARegister, Repeat, 9);
 91DECL_BIT(DSDMARegister, Width, 10);
 92DECL_BITS(DSDMARegister, Timing7, 12, 2);
 93DECL_BITS(DSDMARegister, Timing9, 11, 3);
 94DECL_BIT(DSDMARegister, DoIRQ, 14);
 95DECL_BIT(DSDMARegister, Enable, 15);
 96
 97struct DSDMA {
 98	DSDMARegister reg;
 99
100	uint32_t source;
101	uint32_t dest;
102	int32_t count;
103	uint32_t nextSource;
104	uint32_t nextDest;
105	int32_t nextCount;
106	int32_t nextEvent;
107};
108
109struct DSMemory {
110	uint32_t* bios7;
111	uint32_t* bios9;
112	uint32_t* itcm;
113	uint32_t* dtcm;
114	uint32_t* ram;
115	uint32_t* wram;
116	uint32_t* wram7;
117	uint32_t* rom;
118	uint16_t io7[DS7_REG_MAX >> 1];
119	uint16_t io9[DS9_REG_MAX >> 1];
120
121	size_t romSize;
122	size_t wramSize7;
123	size_t wramSize9;
124
125	char waitstatesSeq32[256];
126	char waitstatesSeq16[256];
127	char waitstatesNonseq32[256];
128	char waitstatesNonseq16[256];
129	char waitstatesPrefetchSeq32[16];
130	char waitstatesPrefetchSeq16[16];
131	char waitstatesPrefetchNonseq32[16];
132	char waitstatesPrefetchNonseq16[16];
133	int activeRegion7;
134	int activeRegion9;
135
136	struct DSDMA dma7[4];
137	struct DSDMA dma9[4];
138	int activeDMA7;
139	int activeDMA9;
140	int32_t nextDMA;
141	int32_t eventDiff;
142};
143
144struct DS;
145void DSMemoryInit(struct DS* ds);
146void DSMemoryDeinit(struct DS* ds);
147
148void DSMemoryReset(struct DS* ds);
149
150uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
151uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
152uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
153
154void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
155void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
156void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
157
158uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
159                         int* cycleCounter);
160uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
161                          int* cycleCounter);
162
163uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
164uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
165uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
166
167void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
168void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
169void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
170
171uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
172                         int* cycleCounter);
173uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
174                          int* cycleCounter);
175
176#endif