src/gba/dma.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/dma.h>
7
8#include <mgba/internal/gba/gba.h>
9#include <mgba/internal/gba/io.h>
10
11static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
12
13static void GBADMAService(struct GBA* gba, int number, struct GBADMA* info);
14
15static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
16
17void GBADMAInit(struct GBA* gba) {
18 gba->memory.dmaEvent.name = "GBA DMA";
19 gba->memory.dmaEvent.callback = _dmaEvent;
20 gba->memory.dmaEvent.context = gba;
21 gba->memory.dmaEvent.priority = 0x40;
22}
23
24void GBADMAReset(struct GBA* gba) {
25 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
26 int i;
27 for (i = 0; i < 4; ++i) {
28 gba->memory.dma[i].count = 0x4000;
29 }
30 gba->memory.dma[3].count = 0x10000;
31 gba->memory.activeDMA = -1;
32}
33static bool _isValidDMASAD(int dma, uint32_t address) {
34 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
35 return false;
36 }
37 return address >= BASE_WORKING_RAM;
38}
39
40static bool _isValidDMADAD(int dma, uint32_t address) {
41 return dma == 3 || address < BASE_CART0;
42}
43
44uint32_t GBADMAWriteSAD(struct GBA* gba, int dma, uint32_t address) {
45 struct GBAMemory* memory = &gba->memory;
46 address &= 0x0FFFFFFE;
47 if (_isValidDMASAD(dma, address)) {
48 memory->dma[dma].source = address;
49 }
50 return memory->dma[dma].source;
51}
52
53uint32_t GBADMAWriteDAD(struct GBA* gba, int dma, uint32_t address) {
54 struct GBAMemory* memory = &gba->memory;
55 address &= 0x0FFFFFFE;
56 if (_isValidDMADAD(dma, address)) {
57 memory->dma[dma].dest = address;
58 }
59 return memory->dma[dma].dest;
60}
61
62void GBADMAWriteCNT_LO(struct GBA* gba, int dma, uint16_t count) {
63 struct GBAMemory* memory = &gba->memory;
64 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
65}
66
67uint16_t GBADMAWriteCNT_HI(struct GBA* gba, int dma, uint16_t control) {
68 struct GBAMemory* memory = &gba->memory;
69 struct GBADMA* currentDma = &memory->dma[dma];
70 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
71 if (dma < 3) {
72 control &= 0xF7E0;
73 } else {
74 control &= 0xFFE0;
75 }
76 currentDma->reg = control;
77
78 if (GBADMARegisterIsDRQ(currentDma->reg)) {
79 mLOG(GBA_MEM, STUB, "DRQ not implemented");
80 }
81
82 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
83 currentDma->nextSource = currentDma->source;
84 if (currentDma->nextSource >= BASE_CART0 && currentDma->nextSource < BASE_CART_SRAM && GBADMARegisterGetSrcControl(currentDma->reg) < 3) {
85 currentDma->reg = GBADMARegisterClearSrcControl(currentDma->reg);
86 }
87 currentDma->nextDest = currentDma->dest;
88
89 uint32_t width = 2 << GBADMARegisterGetWidth(currentDma->reg);
90 if (currentDma->nextSource & (width - 1)) {
91 mLOG(GBA_MEM, GAME_ERROR, "Misaligned DMA source address: 0x%08X", currentDma->nextSource);
92 }
93 if (currentDma->nextDest & (width - 1)) {
94 mLOG(GBA_MEM, GAME_ERROR, "Misaligned DMA destination address: 0x%08X", currentDma->nextDest);
95 }
96
97 GBADMASchedule(gba, dma, currentDma);
98 }
99 // If the DMA has already occurred, this value might have changed since the function started
100 return currentDma->reg;
101};
102
103void GBADMASchedule(struct GBA* gba, int number, struct GBADMA* info) {
104 switch (GBADMARegisterGetTiming(info->reg)) {
105 case DMA_TIMING_NOW:
106 info->when = mTimingCurrentTime(&gba->timing) + 3; // DMAs take 3 cycles to start
107 info->nextCount = info->count;
108 break;
109 case DMA_TIMING_HBLANK:
110 case DMA_TIMING_VBLANK:
111 // Handled implicitly
112 return;
113 case DMA_TIMING_CUSTOM:
114 switch (number) {
115 case 0:
116 mLOG(GBA_MEM, WARN, "Discarding invalid DMA0 scheduling");
117 return;
118 case 1:
119 case 2:
120 GBAAudioScheduleFifoDma(&gba->audio, number, info);
121 break;
122 case 3:
123 // GBAVideoScheduleVCaptureDma(dma, info);
124 break;
125 }
126 }
127 GBADMAUpdate(gba);
128}
129
130void GBADMARunHblank(struct GBA* gba, int32_t cycles) {
131 struct GBAMemory* memory = &gba->memory;
132 struct GBADMA* dma;
133 int i;
134 for (i = 0; i < 4; ++i) {
135 dma = &memory->dma[i];
136 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK && !dma->nextCount) {
137 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
138 dma->nextCount = dma->count;
139 }
140 }
141 GBADMAUpdate(gba);
142}
143
144void GBADMARunVblank(struct GBA* gba, int32_t cycles) {
145 struct GBAMemory* memory = &gba->memory;
146 struct GBADMA* dma;
147 int i;
148 for (i = 0; i < 4; ++i) {
149 dma = &memory->dma[i];
150 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK && !dma->nextCount) {
151 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
152 dma->nextCount = dma->count;
153 }
154 }
155 GBADMAUpdate(gba);
156}
157
158void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
159 UNUSED(timing);
160 UNUSED(cyclesLate);
161 struct GBA* gba = context;
162 struct GBAMemory* memory = &gba->memory;
163 struct GBADMA* dma = &memory->dma[memory->activeDMA];
164 if (dma->nextCount == dma->count) {
165 dma->when = mTimingCurrentTime(&gba->timing);
166 }
167 if (dma->nextCount & 0xFFFFF) {
168 GBADMAService(gba, memory->activeDMA, dma);
169 } else {
170 dma->nextCount = 0;
171 if (!GBADMARegisterIsRepeat(dma->reg) || GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_NOW) {
172 dma->reg = GBADMARegisterClearEnable(dma->reg);
173
174 // Clear the enable bit in memory
175 memory->io[(REG_DMA0CNT_HI + memory->activeDMA * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
176 }
177 if (GBADMARegisterGetDestControl(dma->reg) == DMA_INCREMENT_RELOAD) {
178 dma->nextDest = dma->dest;
179 }
180 if (GBADMARegisterIsDoIRQ(dma->reg)) {
181 GBARaiseIRQ(gba, IRQ_DMA0 + memory->activeDMA);
182 }
183 GBADMAUpdate(gba);
184 }
185}
186
187void GBADMAUpdate(struct GBA* gba) {
188 int i;
189 struct GBAMemory* memory = &gba->memory;
190 memory->activeDMA = -1;
191 uint32_t currentTime = mTimingCurrentTime(&gba->timing);
192 for (i = 0; i < 4; ++i) {
193 struct GBADMA* dma = &memory->dma[i];
194 if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
195 memory->activeDMA = i;
196 break;
197 }
198 }
199
200 if (memory->activeDMA >= 0) {
201 mTimingDeschedule(&gba->timing, &memory->dmaEvent);
202 mTimingSchedule(&gba->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
203 } else {
204 gba->cpuBlocked = false;
205 }
206}
207
208void GBADMAService(struct GBA* gba, int number, struct GBADMA* info) {
209 struct GBAMemory* memory = &gba->memory;
210 struct ARMCore* cpu = gba->cpu;
211 uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
212 int32_t wordsRemaining = info->nextCount;
213 uint32_t source = info->nextSource;
214 uint32_t dest = info->nextDest;
215 uint32_t sourceRegion = source >> BASE_OFFSET;
216 uint32_t destRegion = dest >> BASE_OFFSET;
217 int32_t cycles = 2;
218
219 gba->cpuBlocked = true;
220 if (info->count == info->nextCount) {
221 if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
222 cycles += 2;
223 }
224 if (width == 4) {
225 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
226 } else {
227 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
228 }
229 source &= -width;
230 dest &= -width;
231 } else {
232 if (width == 4) {
233 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
234 } else {
235 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
236 }
237 }
238 info->when += cycles;
239
240 gba->performingDMA = 1 | (number << 1);
241 uint32_t word;
242 if (width == 4) {
243 word = cpu->memory.load32(cpu, source, 0);
244 gba->bus = word;
245 cpu->memory.store32(cpu, dest, word, 0);
246 } else {
247 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
248 word = GBASavedataReadEEPROM(&memory->savedata);
249 cpu->memory.store16(cpu, dest, word, 0);
250 } else if (destRegion == REGION_CART2_EX) {
251 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
252 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
253 GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
254 }
255 word = cpu->memory.load16(cpu, source, 0);
256 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
257 } else {
258 word = cpu->memory.load16(cpu, source, 0);
259 cpu->memory.store16(cpu, dest, word, 0);
260 }
261 gba->bus = word | (word << 16);
262 }
263 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
264 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
265 source += sourceOffset;
266 dest += destOffset;
267 --wordsRemaining;
268 gba->performingDMA = 0;
269
270 info->nextCount = wordsRemaining;
271 info->nextSource = source;
272 info->nextDest = dest;
273 if (!wordsRemaining) {
274 info->nextCount |= 0x80000000;
275 }
276 GBADMAUpdate(gba);
277}