1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/cpu.h>
 14
 15enum {
 16	ARM_SP = 13,
 17	ARM_LR = 14,
 18	ARM_PC = 15
 19};
 20
 21enum ExecutionMode {
 22	MODE_ARM = 0,
 23	MODE_THUMB = 1
 24};
 25
 26enum PrivilegeMode {
 27	MODE_USER = 0x10,
 28	MODE_FIQ = 0x11,
 29	MODE_IRQ = 0x12,
 30	MODE_SUPERVISOR = 0x13,
 31	MODE_ABORT = 0x17,
 32	MODE_UNDEFINED = 0x1B,
 33	MODE_SYSTEM = 0x1F
 34};
 35
 36enum WordSize {
 37	WORD_SIZE_ARM = 4,
 38	WORD_SIZE_THUMB = 2
 39};
 40
 41enum ExecutionVector {
 42	BASE_RESET = 0x00000000,
 43	BASE_UNDEF = 0x00000004,
 44	BASE_SWI = 0x00000008,
 45	BASE_PABT = 0x0000000C,
 46	BASE_DABT = 0x00000010,
 47	BASE_IRQ = 0x00000018,
 48	BASE_FIQ = 0x0000001C
 49};
 50
 51enum RegisterBank {
 52	BANK_NONE = 0,
 53	BANK_FIQ = 1,
 54	BANK_IRQ = 2,
 55	BANK_SUPERVISOR = 3,
 56	BANK_ABORT = 4,
 57	BANK_UNDEFINED = 5
 58};
 59
 60enum LSMDirection {
 61	LSM_B = 1,
 62	LSM_D = 2,
 63	LSM_IA = 0,
 64	LSM_IB = 1,
 65	LSM_DA = 2,
 66	LSM_DB = 3
 67};
 68
 69struct ARMCore;
 70
 71DECL_BITFIELD(ARMPSR, uint32_t);
 72DECL_BITS(ARMPSR, Priv, 0, 5);
 73DECL_BIT(ARMPSR, T, 5);
 74DECL_BIT(ARMPSR, F, 6);
 75DECL_BIT(ARMPSR, I, 7);
 76DECL_BIT(ARMPSR, V, 28);
 77DECL_BIT(ARMPSR, C, 29);
 78DECL_BIT(ARMPSR, Z, 30);
 79DECL_BIT(ARMPSR, N, 31);
 80
 81struct ARMMemory {
 82	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 83	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 84	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 85
 86	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
 87	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
 88	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
 89
 90	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
 91	                         int* cycleCounter);
 92	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
 93	                          int* cycleCounter);
 94
 95	uint32_t* activeRegion;
 96	uint32_t activeMask;
 97	uint32_t activeSeqCycles32;
 98	uint32_t activeSeqCycles16;
 99	uint32_t activeNonseqCycles32;
100	uint32_t activeNonseqCycles16;
101	int32_t (*stall)(struct ARMCore*, int32_t wait);
102	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
103};
104
105struct ARMInterruptHandler {
106	void (*reset)(struct ARMCore* cpu);
107	void (*processEvents)(struct ARMCore* cpu);
108	void (*swi16)(struct ARMCore* cpu, int immediate);
109	void (*swi32)(struct ARMCore* cpu, int immediate);
110	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
111	void (*bkpt16)(struct ARMCore* cpu, int immediate);
112	void (*bkpt32)(struct ARMCore* cpu, int immediate);
113	void (*readCPSR)(struct ARMCore* cpu);
114	void (*writeCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2, uint32_t value);
115	uint32_t (*readCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2);
116
117	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
118};
119
120DECL_BITFIELD(ARMCPUID, uint32_t);
121DECL_BITFIELD(ARMCacheType, uint32_t);
122DECL_BITFIELD(ARMTCMType, uint32_t);
123DECL_BITFIELD(ARMTLBType, uint32_t);
124DECL_BITFIELD(ARMMPUType, uint32_t);
125
126DECL_BITFIELD(ARMControlReg, uint32_t);
127DECL_BIT(ARMControlReg, M, 0);
128DECL_BIT(ARMControlReg, A, 1);
129DECL_BIT(ARMControlReg, C, 2);
130DECL_BIT(ARMControlReg, W, 3);
131DECL_BIT(ARMControlReg, P, 4);
132DECL_BIT(ARMControlReg, D, 5);
133DECL_BIT(ARMControlReg, L, 6);
134DECL_BIT(ARMControlReg, B, 7);
135DECL_BIT(ARMControlReg, S, 8);
136DECL_BIT(ARMControlReg, R, 9);
137DECL_BIT(ARMControlReg, F, 10);
138DECL_BIT(ARMControlReg, Z, 11);
139DECL_BIT(ARMControlReg, I, 12);
140DECL_BIT(ARMControlReg, V, 13);
141DECL_BIT(ARMControlReg, RR, 14);
142DECL_BIT(ARMControlReg, L4, 15);
143DECL_BIT(ARMControlReg, FI, 21);
144DECL_BIT(ARMControlReg, U, 22);
145DECL_BIT(ARMControlReg, XP, 23);
146DECL_BIT(ARMControlReg, VE, 24);
147DECL_BIT(ARMControlReg, EE, 25);
148DECL_BIT(ARMControlReg, L2, 26);
149
150DECL_BITFIELD(ARMCoprocessorAccess, uint32_t);
151
152DECL_BITFIELD(ARMCacheability, uint32_t);
153DECL_BIT(ARMCacheability, 0, 0);
154DECL_BIT(ARMCacheability, 1, 1);
155DECL_BIT(ARMCacheability, 2, 2);
156DECL_BIT(ARMCacheability, 3, 3);
157DECL_BIT(ARMCacheability, 4, 4);
158DECL_BIT(ARMCacheability, 5, 5);
159DECL_BIT(ARMCacheability, 6, 6);
160DECL_BIT(ARMCacheability, 7, 7);
161
162DECL_BITFIELD(ARMProtection, uint32_t);
163DECL_BIT(ARMProtection, Enable, 0);
164DECL_BITS(ARMProtection, Size, 1, 5);
165DECL_BITS(ARMProtection, Base, 12, 20);
166
167DECL_BITFIELD(ARMTCMControl, uint32_t);
168DECL_BITS(ARMTCMControl, VirtualSize, 1, 5);
169DECL_BITS(ARMTCMControl, Base, 12, 20);
170
171struct ARMCP15 {
172	struct {
173		ARMCPUID cpuid;
174		ARMCacheType cachetype;
175		ARMTCMType tcmtype;
176		ARMTLBType tlbtype;
177		ARMMPUType mputype;
178	} r0;
179	struct {
180		ARMControlReg c0;
181		uint32_t c1;
182		ARMCoprocessorAccess cpAccess;
183	} r1;
184	struct {
185		ARMCacheability d;
186		ARMCacheability i;
187	} r2;
188	struct {
189		ARMCacheability d;
190	} r3;
191	struct {
192		ARMProtection region[8];
193	} r6;
194	struct {
195		ARMTCMControl d;
196		ARMTCMControl i;
197	} r9;
198};
199
200struct ARMCore {
201	int32_t gprs[16];
202	ARMPSR cpsr;
203	ARMPSR spsr;
204
205	int32_t cycles;
206	int32_t nextEvent;
207	int halted;
208
209	int32_t bankedRegisters[6][7];
210	int32_t bankedSPSRs[6];
211
212	int32_t shifterOperand;
213	int32_t shifterCarryOut;
214
215	uint32_t prefetch[2];
216	enum ExecutionMode executionMode;
217	enum PrivilegeMode privilegeMode;
218
219	struct ARMMemory memory;
220	struct ARMInterruptHandler irqh;
221	struct ARMCP15 cp15;
222
223	struct mCPUComponent* master;
224
225	size_t numComponents;
226	struct mCPUComponent** components;
227};
228
229void ARMInit(struct ARMCore* cpu);
230void ARMDeinit(struct ARMCore* cpu);
231void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
232void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
233void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
234
235void ARMReset(struct ARMCore* cpu);
236void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
237void ARMRaiseIRQ(struct ARMCore*);
238void ARMRaiseSWI(struct ARMCore*);
239void ARMRaiseUndefined(struct ARMCore*);
240void ARMHalt(struct ARMCore*);
241
242void ARMv4Run(struct ARMCore* cpu);
243void ARMv4RunLoop(struct ARMCore* cpu);
244int32_t ARMv4RunCycles(struct ARMCore* cpu, int32_t cycles);
245void ARMv5Run(struct ARMCore* cpu);
246void ARMv5RunLoop(struct ARMCore* cpu);
247int32_t ARMv5RunCycles(struct ARMCore* cpu, int32_t cycles);
248void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
249
250CXX_GUARD_END
251
252#endif