include/mgba/internal/ds/io.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef DS_IO_H
7#define DS_IO_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/log.h>
14
15enum DSIORegisters {
16 // DMA
17 DS_REG_DMA0SAD_LO = 0x0B0,
18 DS_REG_DMA0SAD_HI = 0x0B2,
19 DS_REG_DMA0DAD_LO = 0x0B4,
20 DS_REG_DMA0DAD_HI = 0x0B6,
21 DS_REG_DMA0CNT_LO = 0x0B8,
22 DS_REG_DMA0CNT_HI = 0x0BA,
23 DS_REG_DMA1SAD_LO = 0x0BC,
24 DS_REG_DMA1SAD_HI = 0x0BE,
25 DS_REG_DMA1DAD_LO = 0x0C0,
26 DS_REG_DMA1DAD_HI = 0x0C2,
27 DS_REG_DMA1CNT_LO = 0x0C4,
28 DS_REG_DMA1CNT_HI = 0x0C6,
29 DS_REG_DMA2SAD_LO = 0x0C8,
30 DS_REG_DMA2SAD_HI = 0x0CA,
31 DS_REG_DMA2DAD_LO = 0x0CC,
32 DS_REG_DMA2DAD_HI = 0x0CE,
33 DS_REG_DMA2CNT_LO = 0x0D0,
34 DS_REG_DMA2CNT_HI = 0x0D2,
35 DS_REG_DMA3SAD_LO = 0x0D4,
36 DS_REG_DMA3SAD_HI = 0x0D6,
37 DS_REG_DMA3DAD_LO = 0x0D8,
38 DS_REG_DMA3DAD_HI = 0x0DA,
39 DS_REG_DMA3CNT_LO = 0x0DC,
40 DS_REG_DMA3CNT_HI = 0x0DE,
41 DS_REG_DMA0FILL_LO = 0x0E0,
42 DS_REG_DMA0FILL_HI = 0x0E2,
43 DS_REG_DMA1FILL_LO = 0x0E4,
44 DS_REG_DMA1FILL_HI = 0x0E6,
45 DS_REG_DMA2FILL_LO = 0x0E8,
46 DS_REG_DMA2FILL_HI = 0x0EA,
47 DS_REG_DMA3FILL_LO = 0x0EC,
48 DS_REG_DMA3FILL_HI = 0x0EE,
49
50 // Timers
51 DS_REG_TM0CNT_LO = 0x100,
52 DS_REG_TM0CNT_HI = 0x102,
53 DS_REG_TM1CNT_LO = 0x104,
54 DS_REG_TM1CNT_HI = 0x106,
55 DS_REG_TM2CNT_LO = 0x108,
56 DS_REG_TM2CNT_HI = 0x10A,
57 DS_REG_TM3CNT_LO = 0x10C,
58 DS_REG_TM3CNT_HI = 0x10E,
59
60 // IPC
61 DS_REG_IPCSYNC = 0x180,
62 DS_REG_IPCFIFOCNT = 0x184,
63 DS_REG_IPCFIFOSEND_LO = 0x188,
64 DS_REG_IPCFIFOSEND_HI = 0x18A,
65 DS_REG_IPCFIFORECV_LO = 0x100000,
66 DS_REG_IPCFIFORECV_HI = 0x100002,
67
68 // Interrupts
69 DS_REG_IME = 0x208,
70 DS_REG_IE_LO = 0x210,
71 DS_REG_IE_HI = 0x212,
72 DS_REG_IF_LO = 0x214,
73 DS_REG_IF_HI = 0x216,
74};
75
76enum DS7IORegisters {
77 // Video
78 DS7_REG_DISPSTAT = 0x004,
79 DS7_REG_VCOUNT = 0x006,
80
81 // Keypad
82 DS7_REG_KEYINPUT = 0x130,
83 DS7_REG_KEYCNT = 0x132,
84 DS7_REG_EXTKEYIN = 0x136,
85 DS7_REG_RTC = 0x138,
86
87 // Game card
88 DS7_REG_AUXSPICNT = 0x1A0,
89 DS7_REG_AUXSPIDATA = 0x1A2,
90 DS7_REG_SLOT1CNT_LO = 0x1A4,
91 DS7_REG_SLOT1CNT_HI = 0x1A6,
92 DS7_REG_SLOT1CMD_0 = 0x1A8,
93 DS7_REG_SLOT1CMD_1 = 0x1A9,
94 DS7_REG_SLOT1CMD_2 = 0x1AA,
95 DS7_REG_SLOT1CMD_3 = 0x1AB,
96 DS7_REG_SLOT1CMD_4 = 0x1AC,
97 DS7_REG_SLOT1CMD_5 = 0x1AD,
98 DS7_REG_SLOT1CMD_6 = 0x1AE,
99 DS7_REG_SLOT1CMD_7 = 0x1AF,
100 DS7_REG_SLOT1DATA_0 = 0x100010,
101 DS7_REG_SLOT1DATA_1 = 0x100011,
102 DS7_REG_SLOT1DATA_2 = 0x100012,
103 DS7_REG_SLOT1DATA_3 = 0x100013,
104
105 // Etc
106 DS7_REG_EXMEMSTAT = 0x204,
107
108 // Memory control
109 DS7_REG_VRAMSTAT = 0x240,
110 DS7_REG_WRAMSTAT = 0x241,
111 DS7_REG_POSTFLG = 0x300,
112 DS7_REG_HALTCNT = 0x301,
113 DS7_REG_POWCNT2 = 0x304,
114 DS7_REG_BIOSPROT_LO = 0x308,
115 DS7_REG_BIOSPROT_HI = 0x30A,
116
117 DS7_REG_MAX = 0x51E,
118};
119
120enum DS9IORegisters {
121 // Video
122 DS9_REG_A_DISPCNT_LO = 0x000,
123 DS9_REG_A_DISPCNT_HI = 0x002,
124 DS9_REG_DISPSTAT = 0x004,
125 DS9_REG_VCOUNT = 0x006,
126 DS9_REG_A_BG0CNT = 0x008,
127 DS9_REG_A_BG1CNT = 0x00A,
128 DS9_REG_A_BG2CNT = 0x00C,
129 DS9_REG_A_BG3CNT = 0x00E,
130 DS9_REG_A_BG0HOFS = 0x010,
131 DS9_REG_A_BG0VOFS = 0x012,
132 DS9_REG_A_BG1HOFS = 0x014,
133 DS9_REG_A_BG1VOFS = 0x016,
134 DS9_REG_A_BG2HOFS = 0x018,
135 DS9_REG_A_BG2VOFS = 0x01A,
136 DS9_REG_A_BG3HOFS = 0x01C,
137 DS9_REG_A_BG3VOFS = 0x01E,
138 DS9_REG_A_BG2PA = 0x020,
139 DS9_REG_A_BG2PB = 0x022,
140 DS9_REG_A_BG2PC = 0x024,
141 DS9_REG_A_BG2PD = 0x026,
142 DS9_REG_A_BG2X_LO = 0x028,
143 DS9_REG_A_BG2X_HI = 0x02A,
144 DS9_REG_A_BG2Y_LO = 0x02C,
145 DS9_REG_A_BG2Y_HI = 0x02E,
146 DS9_REG_A_BG3PA = 0x030,
147 DS9_REG_A_BG3PB = 0x032,
148 DS9_REG_A_BG3PC = 0x034,
149 DS9_REG_A_BG3PD = 0x036,
150 DS9_REG_A_BG3X_LO = 0x038,
151 DS9_REG_A_BG3X_HI = 0x03A,
152 DS9_REG_A_BG3Y_LO = 0x03C,
153 DS9_REG_A_BG3Y_HI = 0x03E,
154 DS9_REG_A_WIN0H = 0x040,
155 DS9_REG_A_WIN1H = 0x042,
156 DS9_REG_A_WIN0V = 0x044,
157 DS9_REG_A_WIN1V = 0x046,
158 DS9_REG_A_WININ = 0x048,
159 DS9_REG_A_WINOUT = 0x04A,
160 DS9_REG_A_MOSAIC = 0x04C,
161 DS9_REG_A_BLDCNT = 0x050,
162 DS9_REG_A_BLDALPHA = 0x052,
163 DS9_REG_A_BLDY = 0x054,
164 DS9_REG_DISP3DCNT = 0x060,
165 DS9_REG_DISPCAPCNT_LO = 0x064,
166 DS9_REG_DISPCAPCNT_HI = 0x066,
167 DS9_REG_DISP_MMEM_FIFO_LO = 0x068,
168 DS9_REG_DISP_MMEM_FIFO_HI = 0x06A,
169 DS9_REG_A_MASTER_BRIGHT = 0x06C,
170
171 DS9_REG_B_DISPCNT_LO = 0x1000,
172 DS9_REG_B_DISPCNT_HI = 0x1002,
173 DS9_REG_B_BG0CNT = 0x1008,
174 DS9_REG_B_BG1CNT = 0x100A,
175 DS9_REG_B_BG2CNT = 0x100C,
176 DS9_REG_B_BG3CNT = 0x100E,
177 DS9_REG_B_BG0HOFS = 0x1010,
178 DS9_REG_B_BG0VOFS = 0x1012,
179 DS9_REG_B_BG1HOFS = 0x1014,
180 DS9_REG_B_BG1VOFS = 0x1016,
181 DS9_REG_B_BG2HOFS = 0x1018,
182 DS9_REG_B_BG2VOFS = 0x101A,
183 DS9_REG_B_BG3HOFS = 0x101C,
184 DS9_REG_B_BG3VOFS = 0x101E,
185 DS9_REG_B_BG2PA = 0x1020,
186 DS9_REG_B_BG2PB = 0x1022,
187 DS9_REG_B_BG2PC = 0x1024,
188 DS9_REG_B_BG2PD = 0x1026,
189 DS9_REG_B_BG2X_LO = 0x1028,
190 DS9_REG_B_BG2X_HI = 0x102A,
191 DS9_REG_B_BG2Y_LO = 0x102C,
192 DS9_REG_B_BG2Y_HI = 0x102E,
193 DS9_REG_B_BG3PA = 0x1030,
194 DS9_REG_B_BG3PB = 0x1032,
195 DS9_REG_B_BG3PC = 0x1034,
196 DS9_REG_B_BG3PD = 0x1036,
197 DS9_REG_B_BG3X_LO = 0x1038,
198 DS9_REG_B_BG3X_HI = 0x103A,
199 DS9_REG_B_BG3Y_LO = 0x103C,
200 DS9_REG_B_BG3Y_HI = 0x103E,
201 DS9_REG_B_WIN0H = 0x1040,
202 DS9_REG_B_WIN1H = 0x1042,
203 DS9_REG_B_WIN0V = 0x1044,
204 DS9_REG_B_WIN1V = 0x1046,
205 DS9_REG_B_WININ = 0x1048,
206 DS9_REG_B_WINOUT = 0x104A,
207 DS9_REG_B_MOSAIC = 0x104C,
208 DS9_REG_B_BLDCNT = 0x1050,
209 DS9_REG_B_BLDALPHA = 0x1052,
210 DS9_REG_B_BLDY = 0x1054,
211 DS9_REG_B_MASTER_BRIGHT = 0x106C,
212
213 // Keypad
214 DS9_REG_KEYINPUT = 0x130,
215 DS9_REG_KEYCNT = 0x132,
216
217 // Game card
218 DS9_REG_AUXSPICNT = 0x1A0,
219 DS9_REG_AUXSPIDATA = 0x1A2,
220 DS9_REG_SLOT1CNT_LO = 0x1A4,
221 DS9_REG_SLOT1CNT_HI = 0x1A6,
222 DS9_REG_SLOT1CMD_0 = 0x1A8,
223 DS9_REG_SLOT1CMD_1 = 0x1A9,
224 DS9_REG_SLOT1CMD_2 = 0x1AA,
225 DS9_REG_SLOT1CMD_3 = 0x1AB,
226 DS9_REG_SLOT1CMD_4 = 0x1AC,
227 DS9_REG_SLOT1CMD_5 = 0x1AD,
228 DS9_REG_SLOT1CMD_6 = 0x1AE,
229 DS9_REG_SLOT1CMD_7 = 0x1AF,
230 DS9_REG_SLOT1DATA_0 = 0x100010,
231 DS9_REG_SLOT1DATA_1 = 0x100011,
232 DS9_REG_SLOT1DATA_2 = 0x100012,
233 DS9_REG_SLOT1DATA_3 = 0x100013,
234
235 // Etc
236 DS9_REG_EXMEMCNT = 0x204,
237
238 // Memory control
239 DS9_REG_VRAMCNT_A = 0x240,
240 DS9_REG_VRAMCNT_B = 0x241,
241 DS9_REG_VRAMCNT_C = 0x242,
242 DS9_REG_VRAMCNT_D = 0x243,
243 DS9_REG_VRAMCNT_E = 0x244,
244 DS9_REG_VRAMCNT_F = 0x245,
245 DS9_REG_VRAMCNT_G = 0x246,
246 DS9_REG_WRAMCNT = 0x247,
247 DS9_REG_VRAMCNT_H = 0x248,
248 DS9_REG_VRAMCNT_I = 0x249,
249
250 // Math
251 DS9_REG_DIVCNT = 0x280,
252 DS9_REG_DIV_NUMER_0 = 0x290,
253 DS9_REG_DIV_NUMER_1 = 0x292,
254 DS9_REG_DIV_NUMER_2 = 0x294,
255 DS9_REG_DIV_NUMER_3 = 0x296,
256 DS9_REG_DIV_DENOM_0 = 0x298,
257 DS9_REG_DIV_DENOM_1 = 0x29A,
258 DS9_REG_DIV_DENOM_2 = 0x29C,
259 DS9_REG_DIV_DENOM_3 = 0x29E,
260 DS9_REG_DIV_RESULT_0 = 0x2A0,
261 DS9_REG_DIV_RESULT_1 = 0x2A2,
262 DS9_REG_DIV_RESULT_2 = 0x2A4,
263 DS9_REG_DIV_RESULT_3 = 0x2A6,
264 DS9_REG_DIVREM_RESULT_0 = 0x2A8,
265 DS9_REG_DIVREM_RESULT_1 = 0x2AA,
266 DS9_REG_DIVREM_RESULT_2 = 0x2AC,
267 DS9_REG_DIVREM_RESULT_3 = 0x2AE,
268 DS9_REG_SQRTCNT = 0x2B0,
269 DS9_REG_SQRT_RESULT_LO = 0x2B4,
270 DS9_REG_SQRT_RESULT_HI = 0x2B6,
271 DS9_REG_SQRT_PARAM_0 = 0x2B8,
272 DS9_REG_SQRT_PARAM_1 = 0x2BA,
273 DS9_REG_SQRT_PARAM_2 = 0x2BC,
274 DS9_REG_SQRT_PARAM_3 = 0x2BE,
275
276 DS9_REG_MAX = 0x106E,
277
278 DS9_REG_POSTFLG = 0x300,
279 DS9_REG_POWCNT1 = 0x304,
280};
281
282mLOG_DECLARE_CATEGORY(DS_IO);
283
284extern const char* const DS7IORegisterNames[];
285extern const char* const DS9IORegisterNames[];
286
287struct DS;
288void DS7IOInit(struct DS* ds);
289void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value);
290void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
291void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
292uint16_t DS7IORead(struct DS* ds, uint32_t address);
293uint32_t DS7IORead32(struct DS* ds, uint32_t address);
294
295void DS9IOInit(struct DS* ds);
296void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value);
297void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
298void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
299uint16_t DS9IORead(struct DS* ds, uint32_t address);
300uint32_t DS9IORead32(struct DS* ds, uint32_t address);
301
302CXX_GUARD_END
303
304#endif