1#ifndef ARM_DECODER_H
  2#define ARM_DECODER_H
  3
  4#include <stdint.h>
  5
  6// Bit 0: a register is involved with this operand
  7// Bit 1: an immediate is invovled with this operand
  8// Bit 2: a memory access is invovled with this operand
  9// Bit 3: the destination of this operand is affected by this opcode
 10// Bit 4: this operand is shifted by a register
 11// Bit 5: this operand is shifted by an immediate
 12// Bit 6: this operand is added or subtracted to the base register
 13enum ARMOperandFormat {
 14	ARM_OPERAND_NONE =               0x00000000,
 15	ARM_OPERAND_REGISTER_1 =         0x00000001,
 16	ARM_OPERAND_IMMEDIATE_1 =        0x00000002,
 17	ARM_OPERAND_MEMORY_1 =           0x00000004,
 18	ARM_OPERAND_AFFECTED_1 =         0x00000008,
 19	ARM_OPERAND_SHIFT_REGISTER_1 =   0x00000010,
 20	ARM_OPERAND_SHIFT_IMMEDIATE_1 =  0x00000020,
 21	ARM_OPERAND_1 =                  0x000000FF,
 22
 23	ARM_OPERAND_REGISTER_2 =         0x00000100,
 24	ARM_OPERAND_IMMEDIATE_2 =        0x00000200,
 25	ARM_OPERAND_MEMORY_2 =           0x00000400,
 26	ARM_OPERAND_AFFECTED_2 =         0x00000800,
 27	ARM_OPERAND_SHIFT_REGISTER_2 =   0x00001000,
 28	ARM_OPERAND_SHIFT_IMMEDIATE_2 =  0x00002000,
 29	ARM_OPERAND_2 =                  0x0000FF00,
 30
 31	ARM_OPERAND_REGISTER_3 =         0x00010000,
 32	ARM_OPERAND_IMMEDIATE_3 =        0x00020000,
 33	ARM_OPERAND_MEMORY_3 =           0x00040000,
 34	ARM_OPERAND_AFFECTED_3 =         0x00080000,
 35	ARM_OPERAND_SHIFT_REGISTER_3 =   0x00100000,
 36	ARM_OPERAND_SHIFT_IMMEDIATE_3 =  0x00200000,
 37	ARM_OPERAND_3 =                  0x00FF0000
 38};
 39
 40enum ARMMemoryFormat {
 41	ARM_MEMORY_REGISTER_BASE =    0x0001,
 42	ARM_MEMORY_IMMEDIATE_OFFSET = 0x0002,
 43	ARM_MEMORY_REGISTER_OFFSET  = 0x0004,
 44	ARM_MEMORY_SHIFTED_OFFSET =   0x0008,
 45	ARM_MEMORY_PRE_INCREMENT =    0x0010,
 46	ARM_MEMORY_POST_INCREMENT =   0x0020,
 47	ARM_MEMORY_OFFSET_SUBTRACT =  0x0040
 48};
 49
 50union ARMOperand {
 51	struct {
 52		uint8_t reg;
 53		uint8_t shifterOp;
 54		union {
 55			uint8_t shifterReg;
 56			uint8_t shifterImm;
 57		};
 58	};
 59	int32_t immediate;
 60};
 61
 62struct ARMMemoryAccess {
 63	uint8_t baseReg;
 64	uint16_t format;
 65	union ARMOperand offset;
 66};
 67
 68enum ThumbMnemonic {
 69	THUMB_MN_ILL = 0,
 70	THUMB_MN_ADC,
 71	THUMB_MN_ADD,
 72	THUMB_MN_AND,
 73	THUMB_MN_ASR,
 74	THUMB_MN_B,
 75	THUMB_MN_BIC,
 76	THUMB_MN_BKPT,
 77	THUMB_MN_BL,
 78	THUMB_MN_BLH,
 79	THUMB_MN_BX,
 80	THUMB_MN_CMN,
 81	THUMB_MN_CMP,
 82	THUMB_MN_EOR,
 83	THUMB_MN_LDMIA,
 84	THUMB_MN_LDR,
 85	THUMB_MN_LDRB,
 86	THUMB_MN_LDRH,
 87	THUMB_MN_LDRSB,
 88	THUMB_MN_LDRSH,
 89	THUMB_MN_LSL,
 90	THUMB_MN_LSR,
 91	THUMB_MN_MOV,
 92	THUMB_MN_MUL,
 93	THUMB_MN_MVN,
 94	THUMB_MN_NEG,
 95	THUMB_MN_ORR,
 96	THUMB_MN_POP,
 97	THUMB_MN_PUSH,
 98	THUMB_MN_ROR,
 99	THUMB_MN_SBC,
100	THUMB_MN_STMIA,
101	THUMB_MN_STR,
102	THUMB_MN_STRB,
103	THUMB_MN_STRH,
104	THUMB_MN_SUB,
105	THUMB_MN_SWI,
106	THUMB_MN_TST,
107
108	THUMB_MN_MAX
109};
110
111struct ThumbInstructionInfo {
112	uint16_t opcode;
113	enum ThumbMnemonic mnemonic;
114	union ARMOperand op1;
115	union ARMOperand op2;
116	union ARMOperand op3;
117	struct ARMMemoryAccess memory;
118	int operandFormat;
119	int branches;
120	int traps;
121	int accessesSpecialRegisters;
122	int affectsCPSR;
123};
124
125void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);
126int ARMDisassembleThumb(uint16_t opcode, char* buffer, int blen);
127
128#endif