src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.hw.p = gba;
54
55 int i;
56 for (i = 0; i < 16; ++i) {
57 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
60 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
61 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
64 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
65 }
66 for (; i < 256; ++i) {
67 gba->memory.waitstatesNonseq16[i] = 0;
68 gba->memory.waitstatesSeq16[i] = 0;
69 gba->memory.waitstatesNonseq32[i] = 0;
70 gba->memory.waitstatesSeq32[i] = 0;
71 }
72
73 gba->memory.activeRegion = -1;
74 cpu->memory.activeRegion = 0;
75 cpu->memory.activeMask = 0;
76 cpu->memory.setActiveRegion = GBASetActiveRegion;
77 cpu->memory.activeSeqCycles32 = 0;
78 cpu->memory.activeSeqCycles16 = 0;
79 cpu->memory.activeNonseqCycles32 = 0;
80 cpu->memory.activeNonseqCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 gba->memory.prefetch = false;
117 gba->memory.lastPrefetchedPc = 0;
118
119 if (!gba->memory.wram || !gba->memory.iwram) {
120 GBAMemoryDeinit(gba);
121 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
122 }
123}
124
125static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
126 struct ARMInstructionInfo info;
127 uint32_t nextAddress = address;
128 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
129 if (cpu->executionMode == MODE_THUMB) {
130 while (true) {
131 uint16_t opcode;
132 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
133 ARMDecodeThumb(opcode, &info);
134 switch (info.branchType) {
135 case ARM_BRANCH_NONE:
136 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
137 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
138 gba->idleDetectionStep = -1;
139 return;
140 }
141 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
142 uint32_t offset = 0;
143 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
144 offset = info.memory.offset.immediate;
145 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
146 int reg = info.memory.offset.reg;
147 if (gba->cachedRegisters[reg]) {
148 gba->idleDetectionStep = -1;
149 return;
150 }
151 offset = gba->cachedRegisters[reg];
152 }
153 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
154 loadAddress -= offset;
155 } else {
156 loadAddress += offset;
157 }
158 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
159 gba->idleDetectionStep = -1;
160 return;
161 }
162 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
163 gba->taintedRegisters[info.op1.reg] = true;
164 } else {
165 switch (info.memory.width) {
166 case 1:
167 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
168 break;
169 case 2:
170 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
171 break;
172 case 4:
173 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
174 break;
175 }
176 }
177 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
178 gba->taintedRegisters[info.op1.reg] = true;
179 }
180 nextAddress += WORD_SIZE_THUMB;
181 break;
182 case ARM_BRANCH:
183 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
184 gba->idleLoop = address;
185 gba->idleOptimization = IDLE_LOOP_REMOVE;
186 }
187 gba->idleDetectionStep = -1;
188 return;
189 default:
190 gba->idleDetectionStep = -1;
191 return;
192 }
193 }
194 } else {
195 gba->idleDetectionStep = -1;
196 }
197}
198
199static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
200 struct GBA* gba = (struct GBA*) cpu->master;
201 struct GBAMemory* memory = &gba->memory;
202
203 int newRegion = address >> BASE_OFFSET;
204 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
205 if (address == gba->idleLoop) {
206 if (gba->haltPending) {
207 gba->haltPending = false;
208 GBAHalt(gba);
209 } else {
210 gba->haltPending = true;
211 }
212 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
213 if (address == gba->lastJump) {
214 switch (gba->idleDetectionStep) {
215 case 0:
216 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
217 ++gba->idleDetectionStep;
218 break;
219 case 1:
220 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
221 gba->idleDetectionStep = -1;
222 ++gba->idleDetectionFailures;
223 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
224 gba->idleOptimization = IDLE_LOOP_IGNORE;
225 }
226 break;
227 }
228 _analyzeForIdleLoop(gba, cpu, address);
229 break;
230 }
231 } else {
232 gba->idleDetectionStep = 0;
233 }
234 }
235 }
236
237 gba->lastJump = address;
238 memory->lastPrefetchedPc = 0;
239 memory->lastPrefetchedLoads = 0;
240 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
241 return;
242 }
243
244 if (memory->activeRegion == REGION_BIOS) {
245 memory->biosPrefetch = cpu->prefetch[1];
246 }
247 memory->activeRegion = newRegion;
248 switch (newRegion) {
249 case REGION_BIOS:
250 cpu->memory.activeRegion = memory->bios;
251 cpu->memory.activeMask = SIZE_BIOS - 1;
252 break;
253 case REGION_WORKING_RAM:
254 cpu->memory.activeRegion = memory->wram;
255 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
256 break;
257 case REGION_WORKING_IRAM:
258 cpu->memory.activeRegion = memory->iwram;
259 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
260 break;
261 case REGION_VRAM:
262 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
263 cpu->memory.activeMask = 0x0000FFFF;
264 break;
265 case REGION_CART0:
266 case REGION_CART0_EX:
267 case REGION_CART1:
268 case REGION_CART1_EX:
269 case REGION_CART2:
270 case REGION_CART2_EX:
271 cpu->memory.activeRegion = memory->rom;
272 cpu->memory.activeMask = SIZE_CART0 - 1;
273 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
274 break;
275 }
276 // Fall through
277 default:
278 memory->activeRegion = -1;
279 cpu->memory.activeRegion = _deadbeef;
280 cpu->memory.activeMask = 0;
281 enum GBALogLevel errorLevel = GBA_LOG_FATAL;
282 if (gba->yankedRomSize || !gba->hardCrash) {
283 errorLevel = GBA_LOG_GAME_ERROR;
284 }
285 GBALog(gba, errorLevel, "Jumped to invalid address: %08X", address);
286 return;
287 }
288 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
289 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
290 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
291 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
292}
293
294#define LOAD_BAD \
295 if (gba->performingDMA) { \
296 value = gba->bus; \
297 } else { \
298 value = cpu->prefetch[1]; \
299 if (cpu->executionMode == MODE_THUMB) { \
300 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
301 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
302 case REGION_BIOS: \
303 case REGION_OAM: \
304 /* This isn't right half the time, but we don't have $+6 handy */ \
305 value <<= 16; \
306 value |= cpu->prefetch[0]; \
307 break; \
308 case REGION_WORKING_IRAM: \
309 /* This doesn't handle prefetch clobbering */ \
310 if (cpu->gprs[ARM_PC] & 2) { \
311 value |= cpu->prefetch[0] << 16; \
312 } else { \
313 value <<= 16; \
314 value |= cpu->prefetch[0]; \
315 } \
316 default: \
317 value |= value << 16; \
318 } \
319 } \
320 }
321
322#define LOAD_BIOS \
323 if (address < SIZE_BIOS) { \
324 if (memory->activeRegion == REGION_BIOS) { \
325 LOAD_32(value, address, memory->bios); \
326 } else { \
327 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
328 value = memory->biosPrefetch; \
329 } \
330 } else { \
331 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
332 LOAD_BAD; \
333 }
334
335#define LOAD_WORKING_RAM \
336 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
337 wait += waitstatesRegion[REGION_WORKING_RAM];
338
339#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
340#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
341
342#define LOAD_PALETTE_RAM \
343 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
344 wait += waitstatesRegion[REGION_PALETTE_RAM];
345
346#define LOAD_VRAM \
347 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
348 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
349 } else { \
350 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
351 } \
352 wait += waitstatesRegion[REGION_VRAM];
353
354#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
355
356#define LOAD_CART \
357 wait += waitstatesRegion[address >> BASE_OFFSET]; \
358 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
359 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
360 } else { \
361 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
362 value = ((address & ~3) >> 1) & 0xFFFF; \
363 value |= (((address & ~3) + 2) >> 1) << 16; \
364 }
365
366#define LOAD_SRAM \
367 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
368 value = GBALoad8(cpu, address, 0); \
369 value |= value << 8; \
370 value |= value << 16;
371
372uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
373 struct GBA* gba = (struct GBA*) cpu->master;
374 struct GBAMemory* memory = &gba->memory;
375 uint32_t value = 0;
376 int wait = 0;
377 char* waitstatesRegion = memory->waitstatesNonseq32;
378
379 switch (address >> BASE_OFFSET) {
380 case REGION_BIOS:
381 LOAD_BIOS;
382 break;
383 case REGION_WORKING_RAM:
384 LOAD_WORKING_RAM;
385 break;
386 case REGION_WORKING_IRAM:
387 LOAD_WORKING_IRAM;
388 break;
389 case REGION_IO:
390 LOAD_IO;
391 break;
392 case REGION_PALETTE_RAM:
393 LOAD_PALETTE_RAM;
394 break;
395 case REGION_VRAM:
396 LOAD_VRAM;
397 break;
398 case REGION_OAM:
399 LOAD_OAM;
400 break;
401 case REGION_CART0:
402 case REGION_CART0_EX:
403 case REGION_CART1:
404 case REGION_CART1_EX:
405 case REGION_CART2:
406 case REGION_CART2_EX:
407 LOAD_CART;
408 break;
409 case REGION_CART_SRAM:
410 case REGION_CART_SRAM_MIRROR:
411 LOAD_SRAM;
412 break;
413 default:
414 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
415 LOAD_BAD;
416 break;
417 }
418
419 if (cycleCounter) {
420 wait += 2;
421 if (address >> BASE_OFFSET < REGION_CART0) {
422 wait = GBAMemoryStall(cpu, wait);
423 }
424 *cycleCounter += wait;
425 }
426 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
427 int rotate = (address & 3) << 3;
428 return ROR(value, rotate);
429}
430
431uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
432 struct GBA* gba = (struct GBA*) cpu->master;
433 struct GBAMemory* memory = &gba->memory;
434 uint32_t value = 0;
435 int wait = 0;
436
437 switch (address >> BASE_OFFSET) {
438 case REGION_BIOS:
439 if (address < SIZE_BIOS) {
440 if (memory->activeRegion == REGION_BIOS) {
441 LOAD_16(value, address, memory->bios);
442 } else {
443 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
444 value = (memory->biosPrefetch >> ((address & 2) * 8)) & 0xFFFF;
445 }
446 } else {
447 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
448 LOAD_BAD;
449 value = (value >> ((address & 2) * 8)) & 0xFFFF;
450 }
451 break;
452 case REGION_WORKING_RAM:
453 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
454 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
455 break;
456 case REGION_WORKING_IRAM:
457 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
458 break;
459 case REGION_IO:
460 value = GBAIORead(gba, address & (SIZE_IO - 2));
461 break;
462 case REGION_PALETTE_RAM:
463 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
464 break;
465 case REGION_VRAM:
466 if ((address & 0x0001FFFF) < SIZE_VRAM) {
467 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
468 } else {
469 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
470 }
471 break;
472 case REGION_OAM:
473 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
474 break;
475 case REGION_CART0:
476 case REGION_CART0_EX:
477 case REGION_CART1:
478 case REGION_CART1_EX:
479 case REGION_CART2:
480 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
481 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
482 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
483 } else {
484 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
485 value = (address >> 1) & 0xFFFF;
486 }
487 break;
488 case REGION_CART2_EX:
489 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
490 if (memory->savedata.type == SAVEDATA_EEPROM) {
491 value = GBASavedataReadEEPROM(&memory->savedata);
492 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
493 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
494 } else {
495 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
496 value = (address >> 1) & 0xFFFF;
497 }
498 break;
499 case REGION_CART_SRAM:
500 case REGION_CART_SRAM_MIRROR:
501 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
502 value = GBALoad8(cpu, address, 0);
503 value |= value << 8;
504 break;
505 default:
506 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
507 LOAD_BAD;
508 value = (value >> ((address & 2) * 8)) & 0xFFFF;
509 break;
510 }
511
512 if (cycleCounter) {
513 wait += 2;
514 if (address >> BASE_OFFSET < REGION_CART0) {
515 wait = GBAMemoryStall(cpu, wait);
516 }
517 *cycleCounter += wait;
518 }
519 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
520 int rotate = (address & 1) << 3;
521 return ROR(value, rotate);
522}
523
524uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
525 struct GBA* gba = (struct GBA*) cpu->master;
526 struct GBAMemory* memory = &gba->memory;
527 uint32_t value = 0;
528 int wait = 0;
529
530 switch (address >> BASE_OFFSET) {
531 case REGION_BIOS:
532 if (address < SIZE_BIOS) {
533 if (memory->activeRegion == REGION_BIOS) {
534 value = ((uint8_t*) memory->bios)[address];
535 } else {
536 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
537 value = (memory->biosPrefetch >> ((address & 3) * 8)) & 0xFF;
538 }
539 } else {
540 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
541 LOAD_BAD;
542 value = (value >> ((address & 3) * 8)) & 0xFF;
543 }
544 break;
545 case REGION_WORKING_RAM:
546 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
547 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
548 break;
549 case REGION_WORKING_IRAM:
550 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
551 break;
552 case REGION_IO:
553 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
554 break;
555 case REGION_PALETTE_RAM:
556 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
557 break;
558 case REGION_VRAM:
559 if ((address & 0x0001FFFF) < SIZE_VRAM) {
560 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
561 } else {
562 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
563 }
564 break;
565 case REGION_OAM:
566 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
567 break;
568 case REGION_CART0:
569 case REGION_CART0_EX:
570 case REGION_CART1:
571 case REGION_CART1_EX:
572 case REGION_CART2:
573 case REGION_CART2_EX:
574 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
575 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
576 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
577 } else {
578 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
579 value = (address >> 1) & 0xFF;
580 }
581 break;
582 case REGION_CART_SRAM:
583 case REGION_CART_SRAM_MIRROR:
584 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
585 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
586 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
587 GBASavedataInitSRAM(&memory->savedata);
588 }
589 if (gba->performingDMA == 1) {
590 break;
591 }
592 if (memory->savedata.type == SAVEDATA_SRAM) {
593 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
594 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
595 value = GBASavedataReadFlash(&memory->savedata, address);
596 } else if (memory->hw.devices & HW_TILT) {
597 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
598 } else {
599 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
600 value = 0xFF;
601 }
602 value &= 0xFF;
603 break;
604 default:
605 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
606 LOAD_BAD;
607 value = (value >> ((address & 3) * 8)) & 0xFF;
608 break;
609 }
610
611 if (cycleCounter) {
612 wait += 2;
613 if (address >> BASE_OFFSET < REGION_CART0) {
614 wait = GBAMemoryStall(cpu, wait);
615 }
616 *cycleCounter += wait;
617 }
618 return value;
619}
620
621#define STORE_WORKING_RAM \
622 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
623 wait += waitstatesRegion[REGION_WORKING_RAM];
624
625#define STORE_WORKING_IRAM \
626 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
627
628#define STORE_IO \
629 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
630
631#define STORE_PALETTE_RAM \
632 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
633 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
634 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
635 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
636
637#define STORE_VRAM \
638 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
639 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
640 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC) + 2); \
641 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC)); \
642 } else { \
643 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
644 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC) + 2); \
645 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC)); \
646 } \
647 wait += waitstatesRegion[REGION_VRAM];
648
649#define STORE_OAM \
650 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
651 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
652 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
653
654#define STORE_CART \
655 wait += waitstatesRegion[address >> BASE_OFFSET]; \
656 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
657
658#define STORE_SRAM \
659 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
660
661#define STORE_BAD \
662 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
663
664void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
665 struct GBA* gba = (struct GBA*) cpu->master;
666 struct GBAMemory* memory = &gba->memory;
667 int wait = 0;
668 char* waitstatesRegion = memory->waitstatesNonseq32;
669
670 switch (address >> BASE_OFFSET) {
671 case REGION_WORKING_RAM:
672 STORE_WORKING_RAM;
673 break;
674 case REGION_WORKING_IRAM:
675 STORE_WORKING_IRAM
676 break;
677 case REGION_IO:
678 STORE_IO;
679 break;
680 case REGION_PALETTE_RAM:
681 STORE_PALETTE_RAM;
682 break;
683 case REGION_VRAM:
684 STORE_VRAM;
685 break;
686 case REGION_OAM:
687 STORE_OAM;
688 break;
689 case REGION_CART0:
690 case REGION_CART0_EX:
691 case REGION_CART1:
692 case REGION_CART1_EX:
693 case REGION_CART2:
694 case REGION_CART2_EX:
695 STORE_CART;
696 break;
697 case REGION_CART_SRAM:
698 case REGION_CART_SRAM_MIRROR:
699 STORE_SRAM;
700 break;
701 default:
702 STORE_BAD;
703 break;
704 }
705
706 if (cycleCounter) {
707 ++wait;
708 if (address >> BASE_OFFSET < REGION_CART0) {
709 wait = GBAMemoryStall(cpu, wait);
710 }
711 *cycleCounter += wait;
712 }
713}
714
715void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
716 struct GBA* gba = (struct GBA*) cpu->master;
717 struct GBAMemory* memory = &gba->memory;
718 int wait = 0;
719
720 switch (address >> BASE_OFFSET) {
721 case REGION_WORKING_RAM:
722 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
723 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
724 break;
725 case REGION_WORKING_IRAM:
726 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
727 break;
728 case REGION_IO:
729 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
730 break;
731 case REGION_PALETTE_RAM:
732 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
733 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
734 break;
735 case REGION_VRAM:
736 if ((address & 0x0001FFFF) < SIZE_VRAM) {
737 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
738 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
739 } else {
740 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
741 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x00017FFE);
742 }
743 break;
744 case REGION_OAM:
745 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
746 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
747 break;
748 case REGION_CART0:
749 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
750 uint32_t reg = address & 0xFFFFFE;
751 GBAHardwareGPIOWrite(&memory->hw, reg, value);
752 } else {
753 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
754 }
755 break;
756 case REGION_CART2_EX:
757 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
758 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
759 GBASavedataInitEEPROM(&memory->savedata);
760 }
761 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
762 break;
763 case REGION_CART_SRAM:
764 case REGION_CART_SRAM_MIRROR:
765 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
766 break;
767 default:
768 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
769 break;
770 }
771
772 if (cycleCounter) {
773 ++wait;
774 if (address >> BASE_OFFSET < REGION_CART0) {
775 wait = GBAMemoryStall(cpu, wait);
776 }
777 *cycleCounter += wait;
778 }
779}
780
781void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
782 struct GBA* gba = (struct GBA*) cpu->master;
783 struct GBAMemory* memory = &gba->memory;
784 int wait = 0;
785
786 switch (address >> BASE_OFFSET) {
787 case REGION_WORKING_RAM:
788 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
789 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
790 break;
791 case REGION_WORKING_IRAM:
792 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
793 break;
794 case REGION_IO:
795 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
796 break;
797 case REGION_PALETTE_RAM:
798 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
799 break;
800 case REGION_VRAM:
801 if ((address & 0x0001FFFF) >= ((GBARegisterDISPCNTGetMode(gba->memory.io[REG_DISPCNT >> 1]) == 4) ? 0x00014000 : 0x00010000)) {
802 // TODO: check BG mode
803 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
804 break;
805 }
806 gba->video.renderer->vram[(address & 0x1FFFE) >> 1] = ((uint8_t) value) | (value << 8);
807 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
808 break;
809 case REGION_OAM:
810 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
811 break;
812 case REGION_CART0:
813 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
814 break;
815 case REGION_CART_SRAM:
816 case REGION_CART_SRAM_MIRROR:
817 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
818 if (address == SAVEDATA_FLASH_BASE) {
819 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
820 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
821 } else {
822 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
823 GBASavedataInitSRAM(&memory->savedata);
824 }
825 }
826 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
827 GBASavedataWriteFlash(&memory->savedata, address, value);
828 } else if (memory->savedata.type == SAVEDATA_SRAM) {
829 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
830 memory->savedata.dirty |= SAVEDATA_DIRT_NEW;
831 } else if (memory->hw.devices & HW_TILT) {
832 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
833 } else {
834 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
835 }
836 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
837 break;
838 default:
839 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
840 break;
841 }
842
843 if (cycleCounter) {
844 ++wait;
845 if (address >> BASE_OFFSET < REGION_CART0) {
846 wait = GBAMemoryStall(cpu, wait);
847 }
848 *cycleCounter += wait;
849 }
850}
851
852void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
853 struct GBA* gba = (struct GBA*) cpu->master;
854 struct GBAMemory* memory = &gba->memory;
855 int32_t oldValue = -1;
856
857 switch (address >> BASE_OFFSET) {
858 case REGION_WORKING_RAM:
859 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
860 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
861 break;
862 case REGION_WORKING_IRAM:
863 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
864 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
865 break;
866 case REGION_IO:
867 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
868 break;
869 case REGION_PALETTE_RAM:
870 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
871 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
872 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
873 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
874 break;
875 case REGION_VRAM:
876 if ((address & 0x0001FFFF) < SIZE_VRAM) {
877 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
878 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
879 } else {
880 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
881 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
882 }
883 break;
884 case REGION_OAM:
885 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
886 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
887 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
888 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
889 break;
890 case REGION_CART0:
891 case REGION_CART0_EX:
892 case REGION_CART1:
893 case REGION_CART1_EX:
894 case REGION_CART2:
895 case REGION_CART2_EX:
896 _pristineCow(gba);
897 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
898 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
899 }
900 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
901 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
902 break;
903 case REGION_CART_SRAM:
904 case REGION_CART_SRAM_MIRROR:
905 if (memory->savedata.type == SAVEDATA_SRAM) {
906 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
907 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
908 } else {
909 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
910 }
911 break;
912 default:
913 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
914 break;
915 }
916 if (old) {
917 *old = oldValue;
918 }
919}
920
921void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
922 struct GBA* gba = (struct GBA*) cpu->master;
923 struct GBAMemory* memory = &gba->memory;
924 int16_t oldValue = -1;
925
926 switch (address >> BASE_OFFSET) {
927 case REGION_WORKING_RAM:
928 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
929 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
930 break;
931 case REGION_WORKING_IRAM:
932 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
933 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
934 break;
935 case REGION_IO:
936 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
937 break;
938 case REGION_PALETTE_RAM:
939 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
940 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
941 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
942 break;
943 case REGION_VRAM:
944 if ((address & 0x0001FFFF) < SIZE_VRAM) {
945 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
946 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
947 } else {
948 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
949 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
950 }
951 break;
952 case REGION_OAM:
953 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
954 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
955 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
956 break;
957 case REGION_CART0:
958 case REGION_CART0_EX:
959 case REGION_CART1:
960 case REGION_CART1_EX:
961 case REGION_CART2:
962 case REGION_CART2_EX:
963 _pristineCow(gba);
964 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
965 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
966 }
967 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
968 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
969 break;
970 case REGION_CART_SRAM:
971 case REGION_CART_SRAM_MIRROR:
972 if (memory->savedata.type == SAVEDATA_SRAM) {
973 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
974 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
975 } else {
976 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
977 }
978 break;
979 default:
980 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
981 break;
982 }
983 if (old) {
984 *old = oldValue;
985 }
986}
987
988void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
989 struct GBA* gba = (struct GBA*) cpu->master;
990 struct GBAMemory* memory = &gba->memory;
991 int8_t oldValue = -1;
992
993 switch (address >> BASE_OFFSET) {
994 case REGION_WORKING_RAM:
995 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
996 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
997 break;
998 case REGION_WORKING_IRAM:
999 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
1000 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
1001 break;
1002 case REGION_IO:
1003 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1004 break;
1005 case REGION_PALETTE_RAM:
1006 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1007 break;
1008 case REGION_VRAM:
1009 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1010 break;
1011 case REGION_OAM:
1012 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1013 break;
1014 case REGION_CART0:
1015 case REGION_CART0_EX:
1016 case REGION_CART1:
1017 case REGION_CART1_EX:
1018 case REGION_CART2:
1019 case REGION_CART2_EX:
1020 _pristineCow(gba);
1021 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1022 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1023 }
1024 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1025 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1026 break;
1027 case REGION_CART_SRAM:
1028 case REGION_CART_SRAM_MIRROR:
1029 if (memory->savedata.type == SAVEDATA_SRAM) {
1030 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1031 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1032 } else {
1033 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1034 }
1035 break;
1036 default:
1037 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1038 break;
1039 }
1040 if (old) {
1041 *old = oldValue;
1042 }
1043}
1044
1045#define LDM_LOOP(LDM) \
1046 for (i = 0; i < 16; i += 4) { \
1047 if (UNLIKELY(mask & (1 << i))) { \
1048 LDM; \
1049 waitstatesRegion = memory->waitstatesSeq32; \
1050 cpu->gprs[i] = value; \
1051 ++wait; \
1052 address += 4; \
1053 } \
1054 if (UNLIKELY(mask & (2 << i))) { \
1055 LDM; \
1056 waitstatesRegion = memory->waitstatesSeq32; \
1057 cpu->gprs[i + 1] = value; \
1058 ++wait; \
1059 address += 4; \
1060 } \
1061 if (UNLIKELY(mask & (4 << i))) { \
1062 LDM; \
1063 waitstatesRegion = memory->waitstatesSeq32; \
1064 cpu->gprs[i + 2] = value; \
1065 ++wait; \
1066 address += 4; \
1067 } \
1068 if (UNLIKELY(mask & (8 << i))) { \
1069 LDM; \
1070 waitstatesRegion = memory->waitstatesSeq32; \
1071 cpu->gprs[i + 3] = value; \
1072 ++wait; \
1073 address += 4; \
1074 } \
1075 }
1076
1077uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1078 struct GBA* gba = (struct GBA*) cpu->master;
1079 struct GBAMemory* memory = &gba->memory;
1080 uint32_t value;
1081 int wait = 0;
1082 char* waitstatesRegion = memory->waitstatesNonseq32;
1083
1084 int i;
1085 int offset = 4;
1086 int popcount = 0;
1087 if (direction & LSM_D) {
1088 offset = -4;
1089 popcount = _popcount32(mask);
1090 address -= (popcount << 2) - 4;
1091 }
1092
1093 if (direction & LSM_B) {
1094 address += offset;
1095 }
1096
1097 uint32_t addressMisalign = address & 0x3;
1098 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1099 address &= 0xFFFFFFFC;
1100 }
1101
1102 switch (address >> BASE_OFFSET) {
1103 case REGION_BIOS:
1104 LDM_LOOP(LOAD_BIOS);
1105 break;
1106 case REGION_WORKING_RAM:
1107 LDM_LOOP(LOAD_WORKING_RAM);
1108 break;
1109 case REGION_WORKING_IRAM:
1110 LDM_LOOP(LOAD_WORKING_IRAM);
1111 break;
1112 case REGION_IO:
1113 LDM_LOOP(LOAD_IO);
1114 break;
1115 case REGION_PALETTE_RAM:
1116 LDM_LOOP(LOAD_PALETTE_RAM);
1117 break;
1118 case REGION_VRAM:
1119 LDM_LOOP(LOAD_VRAM);
1120 break;
1121 case REGION_OAM:
1122 LDM_LOOP(LOAD_OAM);
1123 break;
1124 case REGION_CART0:
1125 case REGION_CART0_EX:
1126 case REGION_CART1:
1127 case REGION_CART1_EX:
1128 case REGION_CART2:
1129 case REGION_CART2_EX:
1130 LDM_LOOP(LOAD_CART);
1131 break;
1132 case REGION_CART_SRAM:
1133 case REGION_CART_SRAM_MIRROR:
1134 LDM_LOOP(LOAD_SRAM);
1135 break;
1136 default:
1137 LDM_LOOP(LOAD_BAD);
1138 break;
1139 }
1140
1141 if (cycleCounter) {
1142 ++wait;
1143 if (address >> BASE_OFFSET < REGION_CART0) {
1144 wait = GBAMemoryStall(cpu, wait);
1145 }
1146 *cycleCounter += wait;
1147 }
1148
1149 if (direction & LSM_B) {
1150 address -= offset;
1151 }
1152
1153 if (direction & LSM_D) {
1154 address -= (popcount << 2) + 4;
1155 }
1156
1157 return address | addressMisalign;
1158}
1159
1160#define STM_LOOP(STM) \
1161 for (i = 0; i < 16; i += 4) { \
1162 if (UNLIKELY(mask & (1 << i))) { \
1163 value = cpu->gprs[i]; \
1164 STM; \
1165 waitstatesRegion = memory->waitstatesSeq32; \
1166 ++wait; \
1167 address += 4; \
1168 } \
1169 if (UNLIKELY(mask & (2 << i))) { \
1170 value = cpu->gprs[i + 1]; \
1171 STM; \
1172 waitstatesRegion = memory->waitstatesSeq32; \
1173 ++wait; \
1174 address += 4; \
1175 } \
1176 if (UNLIKELY(mask & (4 << i))) { \
1177 value = cpu->gprs[i + 2]; \
1178 STM; \
1179 waitstatesRegion = memory->waitstatesSeq32; \
1180 ++wait; \
1181 address += 4; \
1182 } \
1183 if (UNLIKELY(mask & (8 << i))) { \
1184 value = cpu->gprs[i + 3]; \
1185 STM; \
1186 waitstatesRegion = memory->waitstatesSeq32; \
1187 ++wait; \
1188 address += 4; \
1189 } \
1190 }
1191
1192uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1193 struct GBA* gba = (struct GBA*) cpu->master;
1194 struct GBAMemory* memory = &gba->memory;
1195 uint32_t value;
1196 int wait = 0;
1197 char* waitstatesRegion = memory->waitstatesNonseq32;
1198
1199 int i;
1200 int offset = 4;
1201 int popcount = 0;
1202 if (direction & LSM_D) {
1203 offset = -4;
1204 popcount = _popcount32(mask);
1205 address -= (popcount << 2) - 4;
1206 }
1207
1208 if (direction & LSM_B) {
1209 address += offset;
1210 }
1211
1212 uint32_t addressMisalign = address & 0x3;
1213 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1214 address &= 0xFFFFFFFC;
1215 }
1216
1217 switch (address >> BASE_OFFSET) {
1218 case REGION_WORKING_RAM:
1219 STM_LOOP(STORE_WORKING_RAM);
1220 break;
1221 case REGION_WORKING_IRAM:
1222 STM_LOOP(STORE_WORKING_IRAM);
1223 break;
1224 case REGION_IO:
1225 STM_LOOP(STORE_IO);
1226 break;
1227 case REGION_PALETTE_RAM:
1228 STM_LOOP(STORE_PALETTE_RAM);
1229 break;
1230 case REGION_VRAM:
1231 STM_LOOP(STORE_VRAM);
1232 break;
1233 case REGION_OAM:
1234 STM_LOOP(STORE_OAM);
1235 break;
1236 case REGION_CART0:
1237 case REGION_CART0_EX:
1238 case REGION_CART1:
1239 case REGION_CART1_EX:
1240 case REGION_CART2:
1241 case REGION_CART2_EX:
1242 STM_LOOP(STORE_CART);
1243 break;
1244 case REGION_CART_SRAM:
1245 case REGION_CART_SRAM_MIRROR:
1246 STM_LOOP(STORE_SRAM);
1247 break;
1248 default:
1249 STM_LOOP(STORE_BAD);
1250 break;
1251 }
1252
1253 if (cycleCounter) {
1254 if (address >> BASE_OFFSET < REGION_CART0) {
1255 wait = GBAMemoryStall(cpu, wait);
1256 }
1257 *cycleCounter += wait;
1258 }
1259
1260 if (direction & LSM_B) {
1261 address -= offset;
1262 }
1263
1264 if (direction & LSM_D) {
1265 address -= (popcount << 2) + 4;
1266 }
1267
1268 return address | addressMisalign;
1269}
1270
1271void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1272 struct GBAMemory* memory = &gba->memory;
1273 struct ARMCore* cpu = gba->cpu;
1274 int sram = parameters & 0x0003;
1275 int ws0 = (parameters & 0x000C) >> 2;
1276 int ws0seq = (parameters & 0x0010) >> 4;
1277 int ws1 = (parameters & 0x0060) >> 5;
1278 int ws1seq = (parameters & 0x0080) >> 7;
1279 int ws2 = (parameters & 0x0300) >> 8;
1280 int ws2seq = (parameters & 0x0400) >> 10;
1281 int prefetch = parameters & 0x4000;
1282
1283 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1284 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1285 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1286 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1287
1288 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1289 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1290 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1291
1292 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1293 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1294 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1295
1296 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1297 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1298 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1299
1300 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1301 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1302 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1303
1304 memory->prefetch = prefetch;
1305
1306 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1307 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1308
1309 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1310 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1311}
1312
1313void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1314 struct GBAMemory* memory = &gba->memory;
1315 memory->dma[dma].source = address & 0x0FFFFFFE;
1316}
1317
1318void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1319 struct GBAMemory* memory = &gba->memory;
1320 memory->dma[dma].dest = address & 0x0FFFFFFE;
1321}
1322
1323void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1324 struct GBAMemory* memory = &gba->memory;
1325 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1326}
1327
1328uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1329 struct GBAMemory* memory = &gba->memory;
1330 struct GBADMA* currentDma = &memory->dma[dma];
1331 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1332 currentDma->reg = control;
1333
1334 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1335 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1336 }
1337
1338 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1339 currentDma->nextSource = currentDma->source;
1340 currentDma->nextDest = currentDma->dest;
1341 currentDma->nextCount = currentDma->count;
1342 GBAMemoryScheduleDMA(gba, dma, currentDma);
1343 }
1344 // If the DMA has already occurred, this value might have changed since the function started
1345 return currentDma->reg;
1346};
1347
1348void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1349 struct ARMCore* cpu = gba->cpu;
1350 switch (GBADMARegisterGetTiming(info->reg)) {
1351 case DMA_TIMING_NOW:
1352 info->nextEvent = cpu->cycles;
1353 GBAMemoryUpdateDMAs(gba, 0);
1354 break;
1355 case DMA_TIMING_HBLANK:
1356 // Handled implicitly
1357 info->nextEvent = INT_MAX;
1358 break;
1359 case DMA_TIMING_VBLANK:
1360 // Handled implicitly
1361 info->nextEvent = INT_MAX;
1362 break;
1363 case DMA_TIMING_CUSTOM:
1364 info->nextEvent = INT_MAX;
1365 switch (number) {
1366 case 0:
1367 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1368 break;
1369 case 1:
1370 case 2:
1371 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1372 break;
1373 case 3:
1374 // GBAVideoScheduleVCaptureDma(dma, info);
1375 break;
1376 }
1377 }
1378}
1379
1380void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1381 struct GBAMemory* memory = &gba->memory;
1382 struct GBADMA* dma;
1383 int i;
1384 for (i = 0; i < 4; ++i) {
1385 dma = &memory->dma[i];
1386 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1387 dma->nextEvent = cycles;
1388 }
1389 }
1390 GBAMemoryUpdateDMAs(gba, 0);
1391}
1392
1393void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1394 struct GBAMemory* memory = &gba->memory;
1395 struct GBADMA* dma;
1396 int i;
1397 for (i = 0; i < 4; ++i) {
1398 dma = &memory->dma[i];
1399 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1400 dma->nextEvent = cycles;
1401 }
1402 }
1403 GBAMemoryUpdateDMAs(gba, 0);
1404}
1405
1406int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1407 struct GBAMemory* memory = &gba->memory;
1408 if (memory->nextDMA == INT_MAX) {
1409 return INT_MAX;
1410 }
1411 memory->nextDMA -= cycles;
1412 memory->eventDiff += cycles;
1413 while (memory->nextDMA <= 0) {
1414 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1415 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1416 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1417 memory->eventDiff = 0;
1418 }
1419 return memory->nextDMA;
1420}
1421
1422void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1423 int i;
1424 struct GBAMemory* memory = &gba->memory;
1425 struct ARMCore* cpu = gba->cpu;
1426 memory->activeDMA = -1;
1427 memory->nextDMA = INT_MAX;
1428 for (i = 3; i >= 0; --i) {
1429 struct GBADMA* dma = &memory->dma[i];
1430 if (dma->nextEvent != INT_MAX) {
1431 dma->nextEvent -= cycles;
1432 if (GBADMARegisterIsEnable(dma->reg)) {
1433 memory->activeDMA = i;
1434 memory->nextDMA = dma->nextEvent;
1435 }
1436 }
1437 }
1438 if (memory->nextDMA < cpu->nextEvent) {
1439 cpu->nextEvent = memory->nextDMA;
1440 }
1441}
1442
1443void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1444 struct GBAMemory* memory = &gba->memory;
1445 struct ARMCore* cpu = gba->cpu;
1446 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1447 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1448 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1449 int32_t wordsRemaining = info->nextCount;
1450 uint32_t source = info->nextSource;
1451 uint32_t dest = info->nextDest;
1452 uint32_t sourceRegion = source >> BASE_OFFSET;
1453 uint32_t destRegion = dest >> BASE_OFFSET;
1454 int32_t cycles = 2;
1455
1456 if (source == info->source) {
1457 // TODO: support 4 cycles for ROM access
1458 cycles += 2;
1459 if (width == 4) {
1460 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1461 source &= 0xFFFFFFFC;
1462 dest &= 0xFFFFFFFC;
1463 } else {
1464 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1465 }
1466 } else {
1467 if (width == 4) {
1468 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1469 } else {
1470 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1471 }
1472 }
1473
1474 gba->performingDMA = 1 | (number << 1);
1475 int32_t word;
1476 if (width == 4) {
1477 word = cpu->memory.load32(cpu, source, 0);
1478 gba->bus = word;
1479 cpu->memory.store32(cpu, dest, word, 0);
1480 source += sourceOffset;
1481 dest += destOffset;
1482 --wordsRemaining;
1483 } else {
1484 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1485 word = GBASavedataReadEEPROM(&memory->savedata);
1486 gba->bus = word | (word << 16);
1487 cpu->memory.store16(cpu, dest, word, 0);
1488 source += sourceOffset;
1489 dest += destOffset;
1490 --wordsRemaining;
1491 } else if (destRegion == REGION_CART2_EX) {
1492 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1493 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1494 GBASavedataInitEEPROM(&memory->savedata);
1495 }
1496 word = cpu->memory.load16(cpu, source, 0);
1497 gba->bus = word | (word << 16);
1498 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1499 source += sourceOffset;
1500 dest += destOffset;
1501 --wordsRemaining;
1502 } else {
1503 word = cpu->memory.load16(cpu, source, 0);
1504 gba->bus = word | (word << 16);
1505 cpu->memory.store16(cpu, dest, word, 0);
1506 source += sourceOffset;
1507 dest += destOffset;
1508 --wordsRemaining;
1509 }
1510 }
1511 gba->performingDMA = 0;
1512
1513 if (!wordsRemaining) {
1514 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1515 info->reg = GBADMARegisterClearEnable(info->reg);
1516 info->nextEvent = INT_MAX;
1517
1518 // Clear the enable bit in memory
1519 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1520 } else {
1521 info->nextCount = info->count;
1522 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1523 info->nextDest = info->dest;
1524 }
1525 GBAMemoryScheduleDMA(gba, number, info);
1526 }
1527 if (GBADMARegisterIsDoIRQ(info->reg)) {
1528 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1529 }
1530 } else {
1531 info->nextDest = dest;
1532 info->nextCount = wordsRemaining;
1533 }
1534 info->nextSource = source;
1535
1536 if (info->nextEvent != INT_MAX) {
1537 info->nextEvent += cycles;
1538 }
1539 cpu->cycles += cycles;
1540}
1541
1542int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1543 struct GBA* gba = (struct GBA*) cpu->master;
1544 struct GBAMemory* memory = &gba->memory;
1545
1546 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1547 // The wait is the stall
1548 return wait;
1549 }
1550
1551 int32_t s = cpu->memory.activeSeqCycles16 + 1;
1552 int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
1553
1554 // Figure out how many sequential loads we can jam in
1555 int32_t stall = s;
1556 int32_t loads = 1;
1557 int32_t previousLoads = 0;
1558
1559 // Don't prefetch too much if we're overlapping with a previous prefetch
1560 uint32_t dist = (memory->lastPrefetchedPc - cpu->gprs[ARM_PC]) >> 1;
1561 if (dist < memory->lastPrefetchedLoads) {
1562 previousLoads = dist;
1563 }
1564 while (stall < wait) {
1565 stall += s;
1566 ++loads;
1567 }
1568 if (loads + previousLoads > 8) {
1569 int diff = (loads + previousLoads) - 8;
1570 loads -= diff;
1571 stall -= s * diff;
1572 } else if (stall > wait && loads == 1) {
1573 // We might need to stall a bit extra if we haven't finished the first S cycle
1574 wait = stall;
1575 }
1576 // This instruction used to have an N, convert it to an S.
1577 wait -= n2s;
1578
1579 // TODO: Invalidate prefetch on branch
1580 memory->lastPrefetchedLoads = loads;
1581 memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * loads;
1582
1583 // The next |loads|S waitstates disappear entirely, so long as they're all in a row
1584 cpu->cycles -= (s - 1) * loads;
1585 return wait;
1586}
1587
1588void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1589 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1590 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1591}
1592
1593void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1594 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1595 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1596}
1597
1598uint32_t _popcount32(unsigned bits) {
1599 bits = bits - ((bits >> 1) & 0x55555555);
1600 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1601 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1602}
1603
1604void _pristineCow(struct GBA* gba) {
1605 if (gba->memory.rom != gba->pristineRom) {
1606 return;
1607 }
1608 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1609 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1610 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1611}