src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
41
42static void DS9Reset(struct ARMCore* cpu);
43static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44
45static void DSProcessEvents(struct ARMCore* cpu);
46static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
47static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
48static void DSBreakpoint(struct ARMCore* cpu, int immediate);
49
50void DSCreate(struct DS* ds) {
51 ds->d.id = DS_COMPONENT_MAGIC;
52 ds->d.init = DSInit;
53 ds->d.deinit = NULL;
54 ds->arm7 = NULL;
55 ds->arm9 = NULL;
56}
57
58static void DSInit(void* cpu, struct mCPUComponent* component) {
59 struct DS* ds = (struct DS*) component;
60 struct ARMCore* core = cpu;
61 if (!ds->arm7) {
62 // The ARM7 must get initialized first
63 ds->arm7 = core;
64 ds->debugger = 0;
65 ds->sync = 0;
66 return;
67 }
68 ds->arm9 = cpu;
69
70 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
71
72 DS7InterruptHandlerInit(&ds->arm7->irqh);
73 DS9InterruptHandlerInit(&ds->arm9->irqh);
74 DSMemoryInit(ds);
75
76 ds->video.p = ds;
77
78 ds->springIRQ7 = 0;
79 ds->springIRQ9 = 0;
80 ds->keySource = NULL;
81 ds->rtcSource = NULL;
82 ds->rumble = NULL;
83
84 ds->romVf = NULL;
85
86 ds->keyCallback = NULL;
87}
88
89void DSUnloadROM(struct DS* ds) {
90 if (ds->romVf) {
91 ds->romVf->close(ds->romVf);
92 ds->romVf = NULL;
93 }
94}
95
96void DSDestroy(struct DS* ds) {
97 DSUnloadROM(ds);
98 DSMemoryDeinit(ds);
99}
100
101void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
102 irqh->reset = DS7Reset;
103 irqh->processEvents = DSProcessEvents;
104 irqh->swi16 = NULL;
105 irqh->swi32 = NULL;
106 irqh->hitIllegal = DSIllegal;
107 irqh->readCPSR = NULL;
108 irqh->hitStub = DSHitStub;
109 irqh->bkpt16 = DSBreakpoint;
110 irqh->bkpt32 = DSBreakpoint;
111}
112
113void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
114 irqh->reset = DS9Reset;
115 irqh->processEvents = DSProcessEvents;
116 irqh->swi16 = NULL;
117 irqh->swi32 = NULL;
118 irqh->hitIllegal = DSIllegal;
119 irqh->readCPSR = NULL;
120 irqh->hitStub = DSHitStub;
121 irqh->bkpt16 = DSBreakpoint;
122 irqh->bkpt32 = DSBreakpoint;
123}
124
125void DS7Reset(struct ARMCore* cpu) {
126 ARMSetPrivilegeMode(cpu, MODE_IRQ);
127 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
128 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
129 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
130 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
131 cpu->gprs[ARM_SP] = DS7_SP_BASE;
132}
133
134void DS9Reset(struct ARMCore* cpu) {
135 ARMSetPrivilegeMode(cpu, MODE_IRQ);
136 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
137 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
138 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
139 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
140 cpu->gprs[ARM_SP] = DS9_SP_BASE;
141
142 struct DS* ds = (struct DS*) cpu->master;
143 DSMemoryReset(ds);
144}
145
146static void DSProcessEvents(struct ARMCore* cpu) {
147 struct DS* ds = (struct DS*) cpu->master;
148
149 if (ds->springIRQ7) {
150 ARMRaiseIRQ(cpu);
151 ds->springIRQ7 = 0;
152 }
153
154 do {
155 int32_t cycles = cpu->nextEvent;
156 int32_t nextEvent = INT_MAX;
157#ifndef NDEBUG
158 if (cycles < 0) {
159 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
160 }
161#endif
162
163 cpu->cycles -= cycles;
164 cpu->nextEvent = nextEvent;
165
166 if (cpu->halted) {
167 cpu->cycles = cpu->nextEvent;
168 }
169 } while (cpu->cycles >= cpu->nextEvent);
170}
171
172void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
173 ds->debugger = (struct ARMDebugger*) debugger->platform;
174 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
175 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
176 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
177 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
178}
179
180
181void DSDetachDebugger(struct DS* ds) {
182 ds->debugger = NULL;
183 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
184 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
185 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
186 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
187}
188
189bool DSLoadROM(struct DS* ds, struct VFile* vf) {
190 DSUnloadROM(ds);
191 ds->romVf = vf;
192 // TODO: Checksum?
193 // TODO: error check
194 return true;
195}
196
197bool DSIsROM(struct VFile* vf) {
198 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
199 return false;
200 }
201 uint8_t signature[sizeof(DS_ROM_MAGIC)];
202 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
203 return false;
204 }
205 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
206}
207
208bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
209 size_t size = vf->size(vf);
210 void* data = NULL;
211 uint32_t crc;
212 if (size == DS7_SIZE_BIOS) {
213 data = vf->map(vf, size, MAP_READ);
214 } else if (size == 0x1000) {
215 data = vf->map(vf, size, MAP_READ);
216 }
217 if (!data) {
218 return false;
219 }
220 crc = doCrc32(data, size);
221 if (crc == DS7_BIOS_CHECKSUM) {
222 ds->bios7Vf = vf;
223 ds->memory.bios7 = data;
224 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
225 } else if (crc == DS9_BIOS_CHECKSUM) {
226 ds->bios9Vf = vf;
227 ds->memory.bios9 = data;
228 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
229 } else {
230 mLOG(DS, WARN, "BIOS checksum incorrect");
231 vf->unmap(vf, data, size);
232 return false;
233 }
234 return true;
235}
236
237void DSGetGameCode(struct DS* ds, char* out) {
238 memset(out, 0, 8);
239 if (!ds->romVf) {
240 return;
241 }
242
243 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
244 memcpy(out, "NTR-", 4);
245 memcpy(&out[4], &cart->id, 4);
246 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
247}
248
249void DSGetGameTitle(struct DS* ds, char* out) {
250 memset(out, 0, 12);
251 if (!ds->romVf) {
252 return;
253 }
254
255 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
256 memcpy(out, &cart->title, 4);
257 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
258}
259
260void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
261 struct DS* ds = (struct DS*) cpu->master;
262 if (ds->debugger) {
263 struct mDebuggerEntryInfo info = {
264 .address = _ARMPCAddress(cpu),
265 .opcode = opcode
266 };
267 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
268 }
269 // TODO: More sensible category?
270 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
271}
272
273void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
274 struct DS* ds = (struct DS*) cpu->master;
275 if (ds->debugger) {
276 struct mDebuggerEntryInfo info = {
277 .address = _ARMPCAddress(cpu),
278 .opcode = opcode
279 };
280 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
281 } else {
282 ARMRaiseUndefined(cpu);
283 }
284}
285
286void DSBreakpoint(struct ARMCore* cpu, int immediate) {
287 struct DS* ds = (struct DS*) cpu->master;
288 if (immediate >= CPU_COMPONENT_MAX) {
289 return;
290 }
291 switch (immediate) {
292 case CPU_COMPONENT_DEBUGGER:
293 if (ds->debugger) {
294 struct mDebuggerEntryInfo info = {
295 .address = _ARMPCAddress(cpu)
296 };
297 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
298 }
299 break;
300 default:
301 break;
302 }
303}