1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm/arm.h"
 12#include "core/log.h"
 13
 14enum DSMemoryRegion {
 15	DS7_REGION_BIOS = 0x0,
 16	DS9_REGION_ITCM = 0x0,
 17	DS_REGION_RAM = 0x2,
 18	DS_REGION_WORKING_RAM = 0x3,
 19	DS_REGION_IO = 0x4,
 20	DS9_REGION_PALETTE_RAM = 0x5,
 21	DS_REGION_VRAM = 0x6,
 22	DS9_REGION_OAM = 0x7,
 23	DS_REGION_SLOT2 = 0x8,
 24	DS_REGION_SLOT2_EX = 0x9,
 25	DS_REGION_SLOT2_SRAM = 0xA,
 26	DS9_REGION_BIOS = 0xFF,
 27};
 28
 29enum DSMemoryBase {
 30	DS7_BASE_BIOS = 0x00000000,
 31	DS9_BASE_ITCM = 0x00000000,
 32	DS_BASE_RAM = 0x02000000,
 33	DS_BASE_WORKING_RAM = 0x03000000,
 34	DS_BASE_IO = 0x04000000,
 35	DS9_BASE_PALETTE_RAM = 0x05000000,
 36	DS_BASE_VRAM = 0x06000000,
 37	DS9_BASE_OAM = 0x07000000,
 38	DS_BASE_SLOT2 = 0x08000000,
 39	DS_BASE_SLOT2_EX = 0x09000000,
 40	DS9_BASE_BIOS = 0xFFFF0000,
 41};
 42
 43enum {
 44	DS7_SIZE_BIOS = 0x00004000,
 45	DS9_SIZE_BIOS = 0x00008000,
 46	DS_SIZE_RAM = 0x00400000,
 47	DS_SIZE_WORKING_RAM = 0x00008000,
 48	DS9_SIZE_PALETTE_RAM = 0x00000800,
 49	DS9_SIZE_OAM = 0x00000800,
 50	DS_SIZE_SLOT2 = 0x02000000,
 51	DS_SIZE_SLOT2_SRAM = 0x00010000,
 52};
 53
 54enum {
 55	DS_OFFSET_MASK = 0x00FFFFFF,
 56	DS_BASE_OFFSET = 24
 57};
 58
 59enum DSDMAControl {
 60	DS_DMA_INCREMENT = 0,
 61	DS_DMA_DECREMENT = 1,
 62	DS_DMA_FIXED = 2,
 63	DS_DMA_INCREMENT_RELOAD = 3
 64};
 65
 66enum DSDMATiming {
 67	DS_DMA_TIMING_NOW = 0,
 68	DS_DMA_TIMING_VBLANK = 1,
 69	DS_DMA_TIMING_HBLANK = 2,
 70	DS7_DMA_TIMING_SLOT1 = 2,
 71	DS_DMA_TIMING_DISPLAY_START = 3,
 72	DS7_DMA_TIMING_CUSTOM = 3,
 73	DS_DMA_TIMING_MEMORY_DISPLAY = 4,
 74	DS9_DMA_TIMING_SLOT1 = 5,
 75	DS_DMA_TIMING_SLOT2 = 6,
 76	DS_DMA_TIMING_GEOM_FIFO = 7,
 77};
 78
 79mLOG_DECLARE_CATEGORY(DS_MEM);
 80
 81DECL_BITFIELD(DSDMARegister, uint16_t);
 82DECL_BITS(DSDMARegister, DestControl, 5, 2);
 83DECL_BITS(DSDMARegister, SrcControl, 7, 2);
 84DECL_BIT(DSDMARegister, Repeat, 9);
 85DECL_BIT(DSDMARegister, Width, 10);
 86DECL_BITS(DSDMARegister, Timing7, 12, 2);
 87DECL_BITS(DSDMARegister, Timing9, 11, 3);
 88DECL_BIT(DSDMARegister, DoIRQ, 14);
 89DECL_BIT(DSDMARegister, Enable, 15);
 90
 91struct DSDMA {
 92	DSDMARegister reg;
 93
 94	uint32_t source;
 95	uint32_t dest;
 96	int32_t count;
 97	uint32_t nextSource;
 98	uint32_t nextDest;
 99	int32_t nextCount;
100	int32_t nextEvent;
101};
102
103struct DSMemory {
104	uint32_t* bios7;
105	uint32_t* bios9;
106	uint32_t* ram;
107	uint32_t* wram;
108	uint32_t* rom;
109
110	size_t romSize;
111
112	char waitstatesSeq32[256];
113	char waitstatesSeq16[256];
114	char waitstatesNonseq32[256];
115	char waitstatesNonseq16[256];
116	char waitstatesPrefetchSeq32[16];
117	char waitstatesPrefetchSeq16[16];
118	char waitstatesPrefetchNonseq32[16];
119	char waitstatesPrefetchNonseq16[16];
120	int activeRegion7;
121	int activeRegion9;
122
123	struct DSDMA dma7[4];
124	struct DSDMA dma9[4];
125	int activeDMA7;
126	int activeDMA9;
127	int32_t nextDMA;
128	int32_t eventDiff;
129};
130
131struct DS;
132void DSMemoryInit(struct DS* ds);
133void DSMemoryDeinit(struct DS* ds);
134
135void DSMemoryReset(struct DS* ds);
136
137uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
138uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
139uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
140
141void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
142void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
143void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
144
145uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
146                         int* cycleCounter);
147uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
148                          int* cycleCounter);
149
150uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
151uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
152uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
153
154void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
155void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
156void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
157
158uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
159                         int* cycleCounter);
160uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
161                          int* cycleCounter);
162
163#endif