1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17#include <time.h>
 18
 19mLOG_DECLARE_CATEGORY(GB_MBC);
 20mLOG_DECLARE_CATEGORY(GB_MEM);
 21
 22struct GB;
 23
 24enum {
 25	GB_BASE_CART_BANK0 = 0x0000,
 26	GB_BASE_CART_BANK1 = 0x4000,
 27	GB_BASE_VRAM = 0x8000,
 28	GB_BASE_EXTERNAL_RAM = 0xA000,
 29	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 30	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 31	GB_BASE_OAM = 0xFE00,
 32	GB_BASE_UNUSABLE = 0xFEA0,
 33	GB_BASE_IO = 0xFF00,
 34	GB_BASE_HRAM = 0xFF80,
 35	GB_BASE_IE = 0xFFFF
 36};
 37
 38enum {
 39	GB_REGION_CART_BANK0 = 0x0,
 40	GB_REGION_CART_BANK1 = 0x4,
 41	GB_REGION_VRAM = 0x8,
 42	GB_REGION_EXTERNAL_RAM = 0xA,
 43	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 44	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 45	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 46	GB_REGION_OTHER = 0xF,
 47};
 48
 49enum {
 50	GB_SIZE_CART_BANK0 = 0x4000,
 51	GB_SIZE_CART_MAX = 0x800000,
 52	GB_SIZE_VRAM = 0x4000,
 53	GB_SIZE_VRAM_BANK0 = 0x2000,
 54	GB_SIZE_EXTERNAL_RAM = 0x2000,
 55	GB_SIZE_WORKING_RAM = 0x8000,
 56	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 57	GB_SIZE_OAM = 0xA0,
 58	GB_SIZE_IO = 0x80,
 59	GB_SIZE_HRAM = 0x7F,
 60};
 61
 62enum {
 63	GB_SRAM_DIRT_NEW = 1,
 64	GB_SRAM_DIRT_SEEN = 2
 65};
 66
 67struct GBMemory;
 68typedef void (*GBMemoryBankController)(struct GB*, uint16_t address, uint8_t value);
 69
 70DECL_BITFIELD(GBMBC7Field, uint8_t);
 71DECL_BIT(GBMBC7Field, SK, 6);
 72DECL_BIT(GBMBC7Field, CS, 7);
 73DECL_BIT(GBMBC7Field, IO, 1);
 74
 75enum GBMBC7MachineState {
 76	GBMBC7_STATE_NULL = -1,
 77	GBMBC7_STATE_IDLE = 0,
 78	GBMBC7_STATE_READ_COMMAND = 1,
 79	GBMBC7_STATE_READ_ADDRESS = 2,
 80	GBMBC7_STATE_COMMAND_0 = 3,
 81	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 82	GBMBC7_STATE_COMMAND_SR_READ = 5,
 83	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 84	GBMBC7_STATE_READ = 7,
 85	GBMBC7_STATE_WRITE = 8,
 86};
 87
 88struct GBMBC1State {
 89	int mode;
 90};
 91
 92struct GBMBC7State {
 93	enum GBMBC7MachineState state;
 94	uint32_t sr;
 95	uint8_t address;
 96	bool writable;
 97	int srBits;
 98	int command;
 99	GBMBC7Field field;
100};
101
102union GBMBCState {
103	struct GBMBC1State mbc1;
104	struct GBMBC7State mbc7;
105};
106
107struct mRotationSource;
108struct GBMemory {
109	uint8_t* rom;
110	uint8_t* romBase;
111	uint8_t* romBank;
112	enum GBMemoryBankControllerType mbcType;
113	GBMemoryBankController mbc;
114	union GBMBCState mbcState;
115	int currentBank;
116
117	uint8_t* wram;
118	uint8_t* wramBank;
119	int wramCurrentBank;
120
121	bool sramAccess;
122	uint8_t* sram;
123	uint8_t* sramBank;
124	int sramCurrentBank;
125
126	uint8_t io[GB_SIZE_IO];
127	bool ime;
128	uint8_t ie;
129
130	uint8_t hram[GB_SIZE_HRAM];
131
132	uint16_t dmaSource;
133	uint16_t dmaDest;
134	int dmaRemaining;
135
136	uint16_t hdmaSource;
137	uint16_t hdmaDest;
138	int hdmaRemaining;
139	bool isHdma;
140
141	struct mTimingEvent dmaEvent;
142	struct mTimingEvent hdmaEvent;
143
144	size_t romSize;
145
146	bool rtcAccess;
147	int activeRtcReg;
148	bool rtcLatched;
149	uint8_t rtcRegs[5];
150	time_t rtcLastLatch;
151	struct mRTCSource* rtc;
152	struct mRotationSource* rotation;
153	struct mRumble* rumble;
154};
155
156struct LR35902Core;
157void GBMemoryInit(struct GB* gb);
158void GBMemoryDeinit(struct GB* gb);
159
160void GBMemoryReset(struct GB* gb);
161void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
162
163uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
164void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
165
166uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
167
168void GBMemoryDMA(struct GB* gb, uint16_t base);
169void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
170
171uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
172void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
173
174void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
175
176struct GBSerializedState;
177void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
178void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
179
180CXX_GUARD_END
181
182#endif