src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
189 cpu->cpsr.flags = 0;
190 cpu->cpsr.n = ARM_SIGN(d);
191 cpu->cpsr.z = !d;
192 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
193 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
194}
195
196ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
197 cpu->cpsr.flags = 0;
198 cpu->cpsr.n = ARM_SIGN(d);
199 cpu->cpsr.z = !d;
200 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
201 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
202}
203
204ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
205 cpu->cpsr.n = ARM_SIGN(d);
206 cpu->cpsr.z = !d; \
207 cpu->cpsr.c = cpu->shifterCarryOut; \
208}
209
210#define ARM_ADDITION_S(M, N, D) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 _additionS(cpu, M, N, D); \
216 }
217
218#define ARM_SUBTRACTION_S(M, N, D) \
219 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
220 cpu->cpsr = cpu->spsr; \
221 _ARMReadCPSR(cpu); \
222 } else { \
223 _subtractionS(cpu, M, N, D); \
224 }
225
226#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
227 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
228 cpu->cpsr = cpu->spsr; \
229 _ARMReadCPSR(cpu); \
230 } else { \
231 cpu->cpsr.n = ARM_SIGN(D); \
232 cpu->cpsr.z = !(D); \
233 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
234 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
235 }
236
237#define ARM_NEUTRAL_S(M, N, D) \
238 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
239 cpu->cpsr = cpu->spsr; \
240 _ARMReadCPSR(cpu); \
241 } else { \
242 _neutralS(cpu, D); \
243 }
244
245#define ARM_NEUTRAL_HI_S(DLO, DHI) \
246 cpu->cpsr.n = ARM_SIGN(DHI); \
247 cpu->cpsr.z = !((DHI) | (DLO));
248
249#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
250#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
251#define ADDR_MODE_2_ADDRESS (address)
252#define ADDR_MODE_2_RN (cpu->gprs[rn])
253#define ADDR_MODE_2_RM (cpu->gprs[rm])
254#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
255#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
256#define ADDR_MODE_2_WRITEBACK(ADDR) \
257 cpu->gprs[rn] = ADDR; \
258 if (UNLIKELY(rn == ARM_PC)) { \
259 currentCycles += ARMWritePC(cpu); \
260 }
261
262#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
263#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
264#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
265#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
266
267#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
268#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
269#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
270#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
271
272#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
273#define ADDR_MODE_3_RN ADDR_MODE_2_RN
274#define ADDR_MODE_3_RM ADDR_MODE_2_RM
275#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
276#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
277#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
278#define ADDR_MODE_3_WRITEBACK_64(ADDR) ADDR_MODE_2_WRITEBACK(ADDR + 4)
279
280#define ADDR_MODE_4_WRITEBACK_LDM \
281 if (!((1 << rn) & rs)) { \
282 cpu->gprs[rn] = address; \
283 }
284
285#define ADDR_MODE_4_WRITEBACK_LDMv5 \
286 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
287 cpu->gprs[rn] = address; \
288 }
289
290#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
291
292#define ARM_LOAD_POST_BODY \
293 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
294 if (rd == ARM_PC) { \
295 currentCycles += ARMWritePC(cpu); \
296 }
297
298#define ARM_LOAD_POST_BODY_v5 \
299 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
300 if (rd == ARM_PC) { \
301 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
302 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
303 if (cpu->executionMode == MODE_THUMB) { \
304 currentCycles += ThumbWritePC(cpu); \
305 } else { \
306 currentCycles += ARMWritePC(cpu); \
307 } \
308 }
309
310#define ARM_STORE_POST_BODY \
311 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
312
313#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
314 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
315 int currentCycles = ARM_PREFETCH_CYCLES; \
316 BODY; \
317 cpu->cycles += currentCycles; \
318 }
319
320#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
321 DEFINE_INSTRUCTION_ARM(NAME, \
322 int rd = (opcode >> 12) & 0xF; \
323 int rn = (opcode >> 16) & 0xF; \
324 UNUSED(rn); \
325 SHIFTER(cpu, opcode); \
326 BODY; \
327 S_BODY; \
328 if (rd == ARM_PC) { \
329 if (cpu->executionMode == MODE_ARM) { \
330 currentCycles += ARMWritePC(cpu); \
331 } else { \
332 currentCycles += ThumbWritePC(cpu); \
333 } \
334 })
335
336#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
342 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
343 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
344 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
345 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
346 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
347
348#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
349 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
350 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
351 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
352 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
353 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
354
355#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
356 DEFINE_INSTRUCTION_ARM(NAME, \
357 int rd = (opcode >> 16) & 0xF; \
358 int rs = (opcode >> 8) & 0xF; \
359 int rm = opcode & 0xF; \
360 if (rd == ARM_PC) { \
361 return; \
362 } \
363 ARM_WAIT_MUL(cpu->gprs[rs]); \
364 BODY; \
365 S_BODY; \
366 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
367
368#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
369 DEFINE_INSTRUCTION_ARM(NAME, \
370 int rd = (opcode >> 12) & 0xF; \
371 int rdHi = (opcode >> 16) & 0xF; \
372 int rs = (opcode >> 8) & 0xF; \
373 int rm = opcode & 0xF; \
374 if (rdHi == ARM_PC || rd == ARM_PC) { \
375 return; \
376 } \
377 currentCycles += cpu->memory.stall(cpu, WAIT); \
378 BODY; \
379 S_BODY; \
380 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
381
382#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
383 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
384 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
385
386#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
387 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
388 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
389
390#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
391 DEFINE_INSTRUCTION_ARM(NAME, \
392 int rd = (opcode >> 16) & 0xF; \
393 int rs = (opcode >> 8) & 0xF; \
394 int rn = (opcode >> 12) & 0xF; \
395 int rm = opcode & 0xF; \
396 UNUSED(rn); \
397 if (rd == ARM_PC) { \
398 return; \
399 } \
400 /* TODO: Timing */ \
401 int32_t x; \
402 int32_t y; \
403 BODY; \
404 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
405
406#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
407 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
408 x = ARM_SXT_16(cpu->gprs[rm]); \
409 y = ARM_SXT_16(cpu->gprs[rs]); \
410 BODY) \
411 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
412 x = ARM_SXT_16(cpu->gprs[rm]); \
413 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
414 BODY) \
415 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
416 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
417 y = ARM_SXT_16(cpu->gprs[rs]); \
418 BODY) \
419 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
420 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
421 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
422 BODY)
423
424#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
425 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
426 UNUSED(x); \
427 y = ARM_SXT_16(cpu->gprs[rs]); \
428 BODY) \
429 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
430 UNUSED(x); \
431 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
432 BODY) \
433
434#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
435 DEFINE_INSTRUCTION_ARM(NAME, \
436 uint32_t address; \
437 int rn = (opcode >> 16) & 0xF; \
438 int rd = (opcode >> 12) & 0xF; \
439 int rm = opcode & 0xF; \
440 UNUSED(rm); \
441 address = ADDRESS; \
442 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
443 BODY; \
444 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
445
446#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
447 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
448 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
453
454#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
459 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
460 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
465
466#define DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, WRITEBACK) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
473 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
474 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
479
480#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, ADDR_MODE_3_WRITEBACK)
481#define DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(NAME, LS, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, ADDR_MODE_3_WRITEBACK_64)
482
483#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
485 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
486
487#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
488 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
489 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
490 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
491 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
492 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
493 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
494
495#define ARM_MS_PRE \
496 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
497 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
498
499#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
500
501#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
502 DEFINE_INSTRUCTION_ARM(NAME, \
503 int rn = (opcode >> 16) & 0xF; \
504 int rs = opcode & 0x0000FFFF; \
505 uint32_t address = cpu->gprs[rn]; \
506 S_PRE; \
507 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
508 S_POST; \
509 POST_BODY; \
510 WRITEBACK;)
511
512
513#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
514 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
515 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
516 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
517 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
518 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
519 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
520 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
521 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
522
523#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
524 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
525 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
526 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
527 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
528 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
529 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
530 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
531 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
532 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
533
534// Begin ALU definitions
535
536DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
537 int32_t n = cpu->gprs[rn];
538 cpu->gprs[rd] = n + cpu->shifterOperand;)
539
540DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
541 int32_t n = cpu->gprs[rn];
542 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
543
544DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
545 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
546
547DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
548 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
549
550DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
551 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
552
553DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
554 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
555
556DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
557 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
558
559DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
560 cpu->gprs[rd] = cpu->shifterOperand;)
561
562DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
563 cpu->gprs[rd] = ~cpu->shifterOperand;)
564
565DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
566 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
567
568DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
569 int32_t n = cpu->gprs[rn];
570 cpu->gprs[rd] = cpu->shifterOperand - n;)
571
572DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
573 int32_t n = cpu->gprs[rn];
574 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
575
576DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
577 int32_t n = cpu->gprs[rn];
578 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
579
580DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
581 int32_t n = cpu->gprs[rn];
582 cpu->gprs[rd] = n - cpu->shifterOperand;)
583
584DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
585 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
586
587DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
588 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
589
590// End ALU definitions
591
592// Begin multiply definitions
593
594DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
595DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
596
597DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
598 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
599 int32_t dm = cpu->gprs[rd];
600 int32_t dn = d;
601 cpu->gprs[rd] = dm + dn;
602 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
603 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
604
605DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
606 int32_t dn = cpu->gprs[rn]; \
607 int32_t d = x * y; \
608 cpu->gprs[rd] = d + dn; \
609 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
610
611DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
612
613DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
614 int32_t dn = cpu->gprs[rn]; \
615 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
616 cpu->gprs[rd] = d + dn; \
617 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
618
619DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
620
621DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
622 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
623 cpu->gprs[rd] = d;
624 cpu->gprs[rdHi] = d >> 32;,
625 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
626
627DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
628 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
629 int32_t dm = cpu->gprs[rd];
630 int32_t dn = d;
631 cpu->gprs[rd] = dm + dn;
632 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
633 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
634
635DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
636 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
637 cpu->gprs[rd] = d;
638 cpu->gprs[rdHi] = d >> 32;,
639 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
640
641// End multiply definitions
642
643// Begin load/store definitions
644
645DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
646DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
647DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
648DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(LDRD, LOAD, cpu->gprs[rd & ~1] = cpu->memory.load32(cpu, address, ¤tCycles); cpu->gprs[rd | 1] = cpu->memory.load32(cpu, address + 4, ¤tCycles); ARM_LOAD_POST_BODY;)
649DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
650DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
651DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
652DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
653DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
654DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(STRD, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd & ~1], ¤tCycles); cpu->memory.store32(cpu, address + 4, cpu->gprs[rd | 1], ¤tCycles); ARM_STORE_POST_BODY;)
655DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
656
657DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
658 enum PrivilegeMode priv = cpu->privilegeMode;
659 ARMSetPrivilegeMode(cpu, MODE_USER);
660 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
661 ARMSetPrivilegeMode(cpu, priv);
662 cpu->gprs[rd] = r;
663 ARM_LOAD_POST_BODY;)
664
665DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
666 enum PrivilegeMode priv = cpu->privilegeMode;
667 ARMSetPrivilegeMode(cpu, MODE_USER);
668 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
669 ARMSetPrivilegeMode(cpu, priv);
670 cpu->gprs[rd] = r;
671 ARM_LOAD_POST_BODY;)
672
673DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
674 enum PrivilegeMode priv = cpu->privilegeMode;
675 int32_t r = cpu->gprs[rd];
676 ARMSetPrivilegeMode(cpu, MODE_USER);
677 cpu->memory.store8(cpu, address, r, ¤tCycles);
678 ARMSetPrivilegeMode(cpu, priv);
679 ARM_STORE_POST_BODY;)
680
681DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
682 enum PrivilegeMode priv = cpu->privilegeMode;
683 int32_t r = cpu->gprs[rd];
684 ARMSetPrivilegeMode(cpu, MODE_USER);
685 cpu->memory.store32(cpu, address, r, ¤tCycles);
686 ARMSetPrivilegeMode(cpu, priv);
687 ARM_STORE_POST_BODY;)
688
689DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
690 load,
691 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
692 if ((rs & 0x8000) || !rs) {
693 currentCycles += ARMWritePC(cpu);
694 })
695
696DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
697 load,
698 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
699 if (rs & 0x8000) {
700 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
701 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
702 if (cpu->executionMode == MODE_THUMB) {
703 currentCycles += ThumbWritePC(cpu);
704 } else {
705 currentCycles += ARMWritePC(cpu);
706
707 }
708 })
709
710DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
711 store,
712 ARM_STORE_POST_BODY;)
713
714DEFINE_INSTRUCTION_ARM(SWP,
715 int rm = opcode & 0xF;
716 int rd = (opcode >> 12) & 0xF;
717 int rn = (opcode >> 16) & 0xF;
718 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
719 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
720 cpu->gprs[rd] = d;)
721
722DEFINE_INSTRUCTION_ARM(SWPB,
723 int rm = opcode & 0xF;
724 int rd = (opcode >> 12) & 0xF;
725 int rn = (opcode >> 16) & 0xF;
726 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
727 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
728 cpu->gprs[rd] = d;)
729
730// End load/store definitions
731
732// Begin branch definitions
733
734DEFINE_INSTRUCTION_ARM(B,
735 int32_t offset = opcode << 8;
736 offset >>= 6;
737 cpu->gprs[ARM_PC] += offset;
738 currentCycles += ARMWritePC(cpu);)
739
740DEFINE_INSTRUCTION_ARM(BL,
741 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
742 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
743 cpu->gprs[ARM_PC] += immediate >> 6;
744 currentCycles += ARMWritePC(cpu);)
745
746DEFINE_INSTRUCTION_ARM(BX,
747 int rm = opcode & 0x0000000F;
748 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
749 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
750 if (cpu->executionMode == MODE_THUMB) {
751 currentCycles += ThumbWritePC(cpu);
752 } else {
753 currentCycles += ARMWritePC(cpu);
754
755 })
756
757DEFINE_INSTRUCTION_ARM(BLX,
758 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
759 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
760 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
761 _ARMSetMode(cpu, MODE_THUMB);
762 currentCycles += ThumbWritePC(cpu);)
763
764DEFINE_INSTRUCTION_ARM(BLX2,
765 int rm = opcode & 0x0000000F;
766 int address = cpu->gprs[rm];
767 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
768 _ARMSetMode(cpu, address & 0x00000001);
769 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
770 if (cpu->executionMode == MODE_THUMB) {
771 currentCycles += ThumbWritePC(cpu);
772 } else {
773 currentCycles += ARMWritePC(cpu);
774 })
775
776// End branch definitions
777
778// Begin coprocessor definitions
779
780#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
781 DEFINE_INSTRUCTION_ARM(NAME, \
782 int op1 = (opcode >> 21) & 7; \
783 int op2 = (opcode >> 5) & 7; \
784 int rd = (opcode >> 12) & 0xF; \
785 int cp = (opcode >> 8) & 0xF; \
786 int crn = (opcode >> 16) & 0xF; \
787 int crm = opcode & 0xF; \
788 UNUSED(op1); \
789 UNUSED(op2); \
790 UNUSED(rd); \
791 UNUSED(crn); \
792 UNUSED(crm); \
793 BODY;)
794
795DEFINE_COPROCESSOR_INSTRUCTION(MRC,
796 if (cp == 15 && cpu->irqh.readCP15) {
797 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
798 } else {
799 ARM_STUB;
800 })
801
802DEFINE_COPROCESSOR_INSTRUCTION(MCR,
803 if (cp == 15 && cpu->irqh.writeCP15) {
804 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
805 } else {
806 ARM_STUB;
807 })
808
809DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
810DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
811DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
812
813// Begin miscellaneous definitions
814
815DEFINE_INSTRUCTION_ARM(CLZ,
816 int rm = opcode & 0xF;
817 int rd = (opcode >> 12) & 0xF;
818 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
819
820DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
821DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
822
823DEFINE_INSTRUCTION_ARM(MSR,
824 int c = opcode & 0x00010000;
825 int f = opcode & 0x00080000;
826 int32_t operand = cpu->gprs[opcode & 0x0000000F];
827 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
828 if (mask & PSR_USER_MASK) {
829 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
830 }
831 if (mask & PSR_STATE_MASK) {
832 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
833 }
834 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
835 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
836 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
837 }
838 _ARMReadCPSR(cpu);
839 if (cpu->executionMode == MODE_THUMB) {
840 cpu->prefetch[0] = 0x46C0; // nop
841 cpu->prefetch[1] &= 0xFFFF;
842 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
843 } else {
844 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
845 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
846 })
847
848DEFINE_INSTRUCTION_ARM(MSRR,
849 int c = opcode & 0x00010000;
850 int f = opcode & 0x00080000;
851 int32_t operand = cpu->gprs[opcode & 0x0000000F];
852 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
853 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
854 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
855
856DEFINE_INSTRUCTION_ARM(MRS, \
857 int rd = (opcode >> 12) & 0xF; \
858 cpu->gprs[rd] = cpu->cpsr.packed;)
859
860DEFINE_INSTRUCTION_ARM(MRSR, \
861 int rd = (opcode >> 12) & 0xF; \
862 cpu->gprs[rd] = cpu->spsr.packed;)
863
864DEFINE_INSTRUCTION_ARM(MSRI,
865 int c = opcode & 0x00010000;
866 int f = opcode & 0x00080000;
867 int rotate = (opcode & 0x00000F00) >> 7;
868 int32_t operand = ROR(opcode & 0x000000FF, rotate);
869 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
870 if (mask & PSR_USER_MASK) {
871 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
872 }
873 if (mask & PSR_STATE_MASK) {
874 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
875 }
876 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
877 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
878 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
879 }
880 _ARMReadCPSR(cpu);
881 if (cpu->executionMode == MODE_THUMB) {
882 cpu->prefetch[0] = 0x46C0; // nop
883 cpu->prefetch[1] &= 0xFFFF;
884 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
885 } else {
886 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
887 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
888 })
889
890DEFINE_INSTRUCTION_ARM(MSRRI,
891 int c = opcode & 0x00010000;
892 int f = opcode & 0x00080000;
893 int rotate = (opcode & 0x00000F00) >> 7;
894 int32_t operand = ROR(opcode & 0x000000FF, rotate);
895 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
896 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
897 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
898
899DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
900
901const ARMInstruction _armv4Table[0x1000] = {
902 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
903};
904
905const ARMInstruction _armv5Table[0x1000] = {
906 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
907};
908
909const ARMInstruction _armv4FTable[0x1000] = {
910 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
911};
912
913const ARMInstruction _armv5FTable[0x1000] = {
914 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
915};