src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77}
78
79void DSCreate(struct DS* ds) {
80 ds->d.id = DS_COMPONENT_MAGIC;
81 ds->d.init = DSInit;
82 ds->d.deinit = NULL;
83 ds->ds7.p = ds;
84 ds->ds9.p = ds;
85 ds->ds7.cpu = NULL;
86 ds->ds9.cpu = NULL;
87 ds->ds7.ipc = &ds->ds9;
88 ds->ds9.ipc = &ds->ds7;
89}
90
91static void DSInit(void* cpu, struct mCPUComponent* component) {
92 struct DS* ds = (struct DS*) component;
93 struct ARMCore* core = cpu;
94 if (!ds->ds7.cpu) {
95 // The ARM7 must get initialized first
96 ds->ds7.cpu = core;
97 ds->debugger = 0;
98 ds->sync = 0;
99 return;
100 }
101 ds->ds9.cpu = cpu;
102 ds->activeCpu = NULL;
103
104 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
105
106 ds->slice.name = "DS CPU Time Slicing";
107 ds->slice.callback = _slice;
108 ds->slice.context = ds;
109 ds->slice.priority = UINT_MAX;
110
111 CircleBufferInit(&ds->ds7.fifo, 64);
112 CircleBufferInit(&ds->ds9.fifo, 64);
113
114 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
115 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
116 DSMemoryInit(ds);
117 DSDMAInit(ds);
118
119 DSVideoInit(&ds->video);
120 ds->video.p = ds;
121
122 ds->ds7.springIRQ = 0;
123 ds->ds9.springIRQ = 0;
124 DSTimerInit(ds);
125 ds->keySource = NULL;
126 ds->rtcSource = NULL;
127 ds->rumble = NULL;
128
129 ds->romVf = NULL;
130
131 ds->keyCallback = NULL;
132
133 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
134 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
135}
136
137void DSUnloadROM(struct DS* ds) {
138 if (ds->romVf) {
139 ds->romVf->close(ds->romVf);
140 ds->romVf = NULL;
141 }
142}
143
144void DSDestroy(struct DS* ds) {
145 CircleBufferDeinit(&ds->ds7.fifo);
146 CircleBufferDeinit(&ds->ds9.fifo);
147 DSUnloadROM(ds);
148 DSMemoryDeinit(ds);
149 mTimingDeinit(&ds->ds7.timing);
150 mTimingDeinit(&ds->ds9.timing);
151}
152
153void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
154 irqh->reset = DS7Reset;
155 irqh->processEvents = DS7ProcessEvents;
156 irqh->swi16 = DS7Swi16;
157 irqh->swi32 = DS7Swi32;
158 irqh->hitIllegal = DSIllegal;
159 irqh->readCPSR = DS7TestIRQ;
160 irqh->writeCP15 = NULL;
161 irqh->readCP15 = NULL;
162 irqh->hitStub = DSHitStub;
163 irqh->bkpt16 = DSBreakpoint;
164 irqh->bkpt32 = DSBreakpoint;
165}
166
167void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
168 irqh->reset = DS9Reset;
169 irqh->processEvents = DS9ProcessEvents;
170 irqh->swi16 = DS9Swi16;
171 irqh->swi32 = DS9Swi32;
172 irqh->hitIllegal = DSIllegal;
173 irqh->readCPSR = DS9TestIRQ;
174 irqh->writeCP15 = DS9WriteCP15;
175 irqh->readCP15 = DS9ReadCP15;
176 irqh->hitStub = DSHitStub;
177 irqh->bkpt16 = DSBreakpoint;
178 irqh->bkpt32 = DSBreakpoint;
179}
180
181void DS7Reset(struct ARMCore* cpu) {
182 ARMSetPrivilegeMode(cpu, MODE_IRQ);
183 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
184 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
185 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
186 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
187 cpu->gprs[ARM_SP] = DS7_SP_BASE;
188
189 struct DS* ds = (struct DS*) cpu->master;
190 mTimingClear(&ds->ds7.timing);
191 CircleBufferInit(&ds->ds7.fifo, 64);
192 DSMemoryReset(ds);
193 DSDMAReset(&ds->ds7);
194 DS7IOInit(ds);
195
196 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
197 if (header) {
198 // TODO: Error check
199 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
200 uint32_t base = header->arm7Base - DS_BASE_RAM;
201 uint32_t* basePointer = &ds->memory.ram[base >> 2];
202 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
203 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
204 }
205 cpu->gprs[12] = header->arm7Entry;
206 cpu->gprs[ARM_LR] = header->arm7Entry;
207 cpu->gprs[ARM_PC] = header->arm7Entry;
208 int currentCycles = 0;
209 ARM_WRITE_PC;
210
211 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
212 }
213}
214
215void DS9Reset(struct ARMCore* cpu) {
216 ARMSetPrivilegeMode(cpu, MODE_IRQ);
217 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
218 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
219 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
220 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
221 cpu->gprs[ARM_SP] = DS9_SP_BASE;
222
223 struct DS* ds = (struct DS*) cpu->master;
224 mTimingClear(&ds->ds9.timing);
225 CircleBufferInit(&ds->ds9.fifo, 64);
226 DSDMAReset(&ds->ds9);
227 DS9IOInit(ds);
228 DSVideoReset(&ds->video);
229
230 ds->activeCpu = cpu;
231 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
232 ds->cycleDrift = 0;
233 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
234
235 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
236 if (header) {
237 // TODO: Error check
238 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
239 uint32_t base = header->arm9Base - DS_BASE_RAM;
240 uint32_t* basePointer = &ds->memory.ram[base >> 2];
241 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
242 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
243 }
244 cpu->gprs[12] = header->arm9Entry;
245 cpu->gprs[ARM_LR] = header->arm9Entry;
246 cpu->gprs[ARM_PC] = header->arm9Entry;
247 int currentCycles = 0;
248 ARM_WRITE_PC;
249
250 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
251 }
252}
253
254static void DS7ProcessEvents(struct ARMCore* cpu) {
255 struct DS* ds = (struct DS*) cpu->master;
256 DSProcessEvents(&ds->ds7);
257}
258
259static void DS9ProcessEvents(struct ARMCore* cpu) {
260 struct DS* ds = (struct DS*) cpu->master;
261 DSProcessEvents(&ds->ds9);
262}
263
264static void DSProcessEvents(struct DSCommon* dscore) {
265 struct ARMCore* cpu = dscore->cpu;
266 struct DS* ds = dscore->p;
267 if (dscore->springIRQ && !cpu->cpsr.i) {
268 ARMRaiseIRQ(cpu);
269 dscore->springIRQ = 0;
270 }
271
272 int32_t nextEvent = cpu->nextEvent;
273 while (cpu->cycles >= nextEvent) {
274 int32_t cycles = cpu->cycles;
275
276 cpu->cycles = 0;
277 cpu->nextEvent = INT_MAX;
278
279#ifndef NDEBUG
280 if (cycles < 0) {
281 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
282 }
283#endif
284 nextEvent = cycles;
285 do {
286 nextEvent = mTimingTick(&dscore->timing, nextEvent);
287 } while (ds->cpuBlocked);
288
289 cpu->nextEvent = nextEvent;
290
291 if (ds->earlyExit) {
292 ds->earlyExit = false;
293 break;
294 }
295 if (cpu->halted) {
296 cpu->cycles = nextEvent;
297 }
298#ifndef NDEBUG
299 else if (nextEvent < 0) {
300 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
301 }
302#endif
303 }
304}
305
306void DSRunLoop(struct DS* ds) {
307 if (ds->activeCpu == ds->ds9.cpu) {
308 ARMv5RunLoop(ds->ds9.cpu);
309 } else {
310 ARMv4RunLoop(ds->ds7.cpu);
311 }
312}
313
314void DS7Step(struct DS* ds) {
315 while (ds->activeCpu == ds->ds9.cpu) {
316 ARMv5RunLoop(ds->ds9.cpu);
317 }
318 ARMv4Run(ds->ds7.cpu);
319}
320
321void DS9Step(struct DS* ds) {
322 while (ds->activeCpu == ds->ds7.cpu) {
323 ARMv4RunLoop(ds->ds7.cpu);
324 }
325 ARMv5Run(ds->ds9.cpu);
326}
327
328void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
329 ds->debugger = (struct ARMDebugger*) debugger->platform;
330 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
331 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
332 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
333 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
334}
335
336void DSDetachDebugger(struct DS* ds) {
337 ds->debugger = NULL;
338 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
339 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
340 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
341 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
342}
343
344bool DSLoadROM(struct DS* ds, struct VFile* vf) {
345 DSUnloadROM(ds);
346 ds->romVf = vf;
347 // TODO: error check
348 return true;
349}
350
351bool DSIsROM(struct VFile* vf) {
352 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
353 return false;
354 }
355 uint8_t signature[sizeof(DS_ROM_MAGIC)];
356 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
357 return false;
358 }
359 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
360}
361
362bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
363 size_t size = vf->size(vf);
364 void* data = NULL;
365 uint32_t crc;
366 if (size == DS7_SIZE_BIOS) {
367 data = vf->map(vf, size, MAP_READ);
368 } else if (size == 0x1000) {
369 data = vf->map(vf, size, MAP_READ);
370 }
371 if (!data) {
372 return false;
373 }
374 crc = doCrc32(data, size);
375 if (crc == DS7_BIOS_CHECKSUM) {
376 ds->bios7Vf = vf;
377 ds->memory.bios7 = data;
378 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
379 } else if (crc == DS9_BIOS_CHECKSUM) {
380 ds->bios9Vf = vf;
381 ds->memory.bios9 = data;
382 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
383 } else {
384 mLOG(DS, WARN, "BIOS checksum incorrect");
385 vf->unmap(vf, data, size);
386 return false;
387 }
388 return true;
389}
390
391void DSGetGameCode(struct DS* ds, char* out) {
392 memset(out, 0, 8);
393 if (!ds->romVf) {
394 return;
395 }
396
397 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
398 memcpy(out, "NTR-", 4);
399 memcpy(&out[4], &cart->id, 4);
400 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
401}
402
403void DSGetGameTitle(struct DS* ds, char* out) {
404 memset(out, 0, 12);
405 if (!ds->romVf) {
406 return;
407 }
408
409 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
410 memcpy(out, &cart->title, 4);
411 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
412}
413
414void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
415 struct DS* ds = (struct DS*) cpu->master;
416 if (ds->debugger) {
417 struct mDebuggerEntryInfo info = {
418 .address = _ARMPCAddress(cpu),
419 .opcode = opcode
420 };
421 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
422 }
423 // TODO: More sensible category?
424 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
425}
426
427void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
428 struct DS* ds = (struct DS*) cpu->master;
429 if (ds->debugger) {
430 struct mDebuggerEntryInfo info = {
431 .address = _ARMPCAddress(cpu),
432 .opcode = opcode
433 };
434 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
435 } else {
436 ARMRaiseUndefined(cpu);
437 }
438}
439
440void DSBreakpoint(struct ARMCore* cpu, int immediate) {
441 struct DS* ds = (struct DS*) cpu->master;
442 if (immediate >= CPU_COMPONENT_MAX) {
443 return;
444 }
445 switch (immediate) {
446 case CPU_COMPONENT_DEBUGGER:
447 if (ds->debugger) {
448 struct mDebuggerEntryInfo info = {
449 .address = _ARMPCAddress(cpu)
450 };
451 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
452 }
453 break;
454 default:
455 break;
456 }
457}
458
459void DS7TestIRQ(struct ARMCore* cpu) {
460 struct DS* ds = (struct DS*) cpu->master;
461 if (0) {
462 ds->ds7.springIRQ = 1;
463 cpu->nextEvent = cpu->cycles;
464 }
465}
466
467void DS9TestIRQ(struct ARMCore* cpu) {
468 struct DS* ds = (struct DS*) cpu->master;
469 if (0) {
470 ds->ds9.springIRQ = 1;
471 cpu->nextEvent = cpu->cycles;
472 }
473}
474
475static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
476 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
477}
478
479static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
480 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
481 switch (opcode2) {
482 case 0:
483 cpu->cp15.r2.d = value;
484 break;
485 case 1:
486 cpu->cp15.r2.i = value;
487 break;
488 default:
489 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
490 break;
491 }
492}
493
494static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
495 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
496 switch (opcode2) {
497 case 0:
498 cpu->cp15.r3.d = value;
499 break;
500 default:
501 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
502 break;
503 }
504}
505
506static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
507 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
508}
509
510static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
511 cpu->cp15.r6.region[crm] = value;
512 uint32_t base = ARMProtectionGetBase(value) << 12;
513 uint32_t size = 2 << ARMProtectionGetSize(value);
514 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
515}
516
517static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
518 switch (crm) {
519 case 0:
520 if (opcode2 == 4) {
521 ARMHalt(cpu);
522 return;
523 }
524 break;
525 }
526 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
527}
528
529static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
530 uint32_t base = ARMTCMControlGetBase(value) << 12;
531 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
532 struct DS* ds = (struct DS*) cpu->master;
533 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
534 switch (opcode2) {
535 case 0:
536 cpu->cp15.r9.d = value;
537 ds->memory.dtcmBase = base;
538 ds->memory.dtcmSize = size;
539 break;
540 case 1:
541 cpu->cp15.r9.i = value;
542 ds->memory.itcmSize = size;
543 break;
544 default:
545 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
546 break;
547 }
548}
549
550void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
551 switch (crn) {
552 default:
553 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
554 break;
555 case 0:
556 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
557 ARMRaiseUndefined(cpu);
558 break;
559 case 1:
560 _writeSysControl(cpu, crm, opcode2, value);
561 break;
562 case 2:
563 _writeCacheControl(cpu, crm, opcode2, value);
564 break;
565 case 3:
566 _writeWriteBufferControl(cpu, crm, opcode2, value);
567 break;
568 case 5:
569 _writeAccessControl(cpu, crm, opcode2, value);
570 break;
571 case 6:
572 _writeRegionConfiguration(cpu, crm, opcode2, value);
573 break;
574 case 7:
575 _writeCache(cpu, crm, opcode2, value);
576 break;
577 case 9:
578 _writeTCMControl(cpu, crm, opcode2, value);
579 break;
580 }
581}
582
583static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
584 switch (opcode2) {
585 case 0:
586 return cpu->cp15.r9.d;
587 case 1:
588 return cpu->cp15.r9.i;
589 default:
590 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
591 return 0;
592 }
593}
594
595uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
596 switch (crn) {
597 default:
598 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
599 return 0;
600 case 9:
601 return _readTCMControl(cpu, crm, opcode2);
602 }
603}
604
605void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
606 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
607 ARMRaiseIRQ(cpu);
608 }
609}
610void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
611 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
612 ARMRaiseIRQ(cpu);
613 }
614}
615
616void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
617 if (irq < 16) {
618 io[DS_REG_IF_LO >> 1] |= 1 << irq;
619 } else {
620 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
621 }
622
623 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
624 cpu->halted = 0;
625 if (io[DS_REG_IME >> 1]) {
626 ARMRaiseIRQ(cpu);
627 }
628 }
629}
630
631void DSFrameStarted(struct DS* ds) {
632 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
633 if (callbacks && callbacks->videoFrameStarted) {
634 callbacks->videoFrameStarted(callbacks->context);
635 }
636}
637
638void DSFrameEnded(struct DS* ds) {
639 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
640 if (callbacks && callbacks->videoFrameEnded) {
641 callbacks->videoFrameEnded(callbacks->context);
642 }
643}