1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/cpu.h>
 14
 15enum {
 16	ARM_SP = 13,
 17	ARM_LR = 14,
 18	ARM_PC = 15
 19};
 20
 21enum ExecutionMode {
 22	MODE_ARM = 0,
 23	MODE_THUMB = 1
 24};
 25
 26enum PrivilegeMode {
 27	MODE_USER = 0x10,
 28	MODE_FIQ = 0x11,
 29	MODE_IRQ = 0x12,
 30	MODE_SUPERVISOR = 0x13,
 31	MODE_ABORT = 0x17,
 32	MODE_UNDEFINED = 0x1B,
 33	MODE_SYSTEM = 0x1F
 34};
 35
 36enum WordSize {
 37	WORD_SIZE_ARM = 4,
 38	WORD_SIZE_THUMB = 2
 39};
 40
 41enum ExecutionVector {
 42	BASE_RESET = 0x00000000,
 43	BASE_UNDEF = 0x00000004,
 44	BASE_SWI = 0x00000008,
 45	BASE_PABT = 0x0000000C,
 46	BASE_DABT = 0x00000010,
 47	BASE_IRQ = 0x00000018,
 48	BASE_FIQ = 0x0000001C
 49};
 50
 51enum RegisterBank {
 52	BANK_NONE = 0,
 53	BANK_FIQ = 1,
 54	BANK_IRQ = 2,
 55	BANK_SUPERVISOR = 3,
 56	BANK_ABORT = 4,
 57	BANK_UNDEFINED = 5
 58};
 59
 60enum LSMDirection {
 61	LSM_B = 1,
 62	LSM_D = 2,
 63	LSM_IA = 0,
 64	LSM_IB = 1,
 65	LSM_DA = 2,
 66	LSM_DB = 3
 67};
 68
 69struct ARMCore;
 70
 71DECL_BITFIELD(ARMPSR, uint32_t);
 72DECL_BITS(ARMPSR, Priv, 0, 5);
 73DECL_BIT(ARMPSR, T, 5);
 74DECL_BIT(ARMPSR, F, 6);
 75DECL_BIT(ARMPSR, I, 7);
 76DECL_BIT(ARMPSR, V, 28);
 77DECL_BIT(ARMPSR, C, 29);
 78DECL_BIT(ARMPSR, Z, 30);
 79DECL_BIT(ARMPSR, N, 31);
 80
 81struct ARMMemory {
 82	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 83	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 84	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 85
 86	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
 87	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
 88	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
 89
 90	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
 91	                         int* cycleCounter);
 92	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
 93	                          int* cycleCounter);
 94
 95	uint32_t* activeRegion;
 96	uint32_t activeMask;
 97	uint32_t activeSeqCycles32;
 98	uint32_t activeSeqCycles16;
 99	uint32_t activeNonseqCycles32;
100	uint32_t activeNonseqCycles16;
101	int32_t (*stall)(struct ARMCore*, int32_t wait);
102	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
103};
104
105struct ARMInterruptHandler {
106	void (*reset)(struct ARMCore* cpu);
107	void (*processEvents)(struct ARMCore* cpu);
108	void (*swi16)(struct ARMCore* cpu, int immediate);
109	void (*swi32)(struct ARMCore* cpu, int immediate);
110	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
111	void (*bkpt16)(struct ARMCore* cpu, int immediate);
112	void (*bkpt32)(struct ARMCore* cpu, int immediate);
113	void (*readCPSR)(struct ARMCore* cpu);
114
115	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
116};
117
118struct ARMCore {
119	int32_t gprs[16];
120	ARMPSR cpsr;
121	ARMPSR spsr;
122
123	int32_t cycles;
124	int32_t nextEvent;
125	int halted;
126
127	int32_t bankedRegisters[6][7];
128	int32_t bankedSPSRs[6];
129
130	int32_t shifterOperand;
131	int32_t shifterCarryOut;
132
133	uint32_t prefetch[2];
134	enum ExecutionMode executionMode;
135	enum PrivilegeMode privilegeMode;
136
137	struct ARMMemory memory;
138	struct ARMInterruptHandler irqh;
139
140	struct mCPUComponent* master;
141
142	size_t numComponents;
143	struct mCPUComponent** components;
144};
145
146void ARMInit(struct ARMCore* cpu);
147void ARMDeinit(struct ARMCore* cpu);
148void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
149void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
150void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
151
152void ARMReset(struct ARMCore* cpu);
153void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
154void ARMRaiseIRQ(struct ARMCore*);
155void ARMRaiseSWI(struct ARMCore*);
156void ARMRaiseUndefined(struct ARMCore*);
157
158void ARMRun(struct ARMCore* cpu);
159void ARMRunLoop(struct ARMCore* cpu);
160void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
161
162CXX_GUARD_END
163
164#endif