src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define ARM_ADDITION_S(M, N, D) \
188 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
189 cpu->cpsr = cpu->spsr; \
190 _ARMReadCPSR(cpu); \
191 } else { \
192 ARMPSR cpsr = 0; \
193 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
194 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
195 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM(M, N, D)); \
196 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
197 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
198 }
199
200#define ARM_ADDITION_CARRY_S(M, N, D, C) \
201 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
202 cpu->cpsr = cpu->spsr; \
203 _ARMReadCPSR(cpu); \
204 } else { \
205 ARMPSR cpsr = 0; \
206 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
207 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
208 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM_CARRY(M, N, D, C)); \
209 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
210 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
211 }
212
213#define ARM_SUBTRACTION_S(M, N, D) \
214 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
215 cpu->cpsr = cpu->spsr; \
216 _ARMReadCPSR(cpu); \
217 } else { \
218 ARMPSR cpsr = 0; \
219 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
220 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
221 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM(M, N, D)); \
222 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
223 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
224 }
225
226#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
227 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
228 cpu->cpsr = cpu->spsr; \
229 _ARMReadCPSR(cpu); \
230 } else { \
231 ARMPSR cpsr = 0; \
232 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
233 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
234 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM_CARRY(M, N, D, C)); \
235 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
236 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
237 }
238
239#define ARM_NEUTRAL_S(M, N, D) \
240 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
241 cpu->cpsr = cpu->spsr; \
242 _ARMReadCPSR(cpu); \
243 } else { \
244 ARMPSR cpsr = 0; \
245 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
246 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
247 cpsr = ARMPSROrUnsafeC(cpsr, cpu->shifterCarryOut); \
248 cpu->cpsr = (cpu->cpsr & (0x1FFFFFFF)) | cpsr; \
249 }
250
251#define ARM_NEUTRAL_HI_S(DLO, DHI) \
252 { \
253 ARMPSR cpsr = 0; \
254 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(DHI)); \
255 cpsr = ARMPSROrUnsafeZ(cpsr, !((DHI) | (DLO))); \
256 cpu->cpsr = (cpu->cpsr & (0x3FFFFFFF)) | cpsr; \
257 }
258
259#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
260#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
261#define ADDR_MODE_2_ADDRESS (address)
262#define ADDR_MODE_2_RN (cpu->gprs[rn])
263#define ADDR_MODE_2_RM (cpu->gprs[rm])
264#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
265#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
266#define ADDR_MODE_2_WRITEBACK(ADDR) \
267 cpu->gprs[rn] = ADDR; \
268 if (UNLIKELY(rn == ARM_PC)) { \
269 ARM_WRITE_PC; \
270 }
271
272#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
273#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
274#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
275#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
276
277#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
278#define ADDR_MODE_3_RN ADDR_MODE_2_RN
279#define ADDR_MODE_3_RM ADDR_MODE_2_RM
280#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
281#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
282#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
283
284#define ADDR_MODE_4_WRITEBACK_LDM \
285 if (!((1 << rn) & rs)) { \
286 cpu->gprs[rn] = address; \
287 }
288
289#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
290
291#define ARM_LOAD_POST_BODY \
292 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
293 if (rd == ARM_PC) { \
294 ARM_WRITE_PC; \
295 }
296
297#define ARM_STORE_POST_BODY \
298 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
299
300#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
301 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
302 int currentCycles = ARM_PREFETCH_CYCLES; \
303 BODY; \
304 cpu->cycles += currentCycles; \
305 }
306
307#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
308 DEFINE_INSTRUCTION_ARM(NAME, \
309 int rd = (opcode >> 12) & 0xF; \
310 int rn = (opcode >> 16) & 0xF; \
311 UNUSED(rn); \
312 SHIFTER(cpu, opcode); \
313 BODY; \
314 S_BODY; \
315 if (rd == ARM_PC) { \
316 if (cpu->executionMode == MODE_ARM) { \
317 ARM_WRITE_PC; \
318 } else { \
319 THUMB_WRITE_PC; \
320 } \
321 })
322
323#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
334
335#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
341
342#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
343 DEFINE_INSTRUCTION_ARM(NAME, \
344 int rd = (opcode >> 16) & 0xF; \
345 int rs = (opcode >> 8) & 0xF; \
346 int rm = opcode & 0xF; \
347 if (rd == ARM_PC) { \
348 return; \
349 } \
350 ARM_WAIT_MUL(cpu->gprs[rs]); \
351 BODY; \
352 S_BODY; \
353 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
354
355#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
356 DEFINE_INSTRUCTION_ARM(NAME, \
357 int rd = (opcode >> 12) & 0xF; \
358 int rdHi = (opcode >> 16) & 0xF; \
359 int rs = (opcode >> 8) & 0xF; \
360 int rm = opcode & 0xF; \
361 if (rdHi == ARM_PC || rd == ARM_PC) { \
362 return; \
363 } \
364 currentCycles += cpu->memory.stall(cpu, WAIT); \
365 BODY; \
366 S_BODY; \
367 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
368
369#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
370 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
371 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
372
373#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
374 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
375 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
376
377#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
378 DEFINE_INSTRUCTION_ARM(NAME, \
379 uint32_t address; \
380 int rn = (opcode >> 16) & 0xF; \
381 int rd = (opcode >> 12) & 0xF; \
382 int rm = opcode & 0xF; \
383 UNUSED(rm); \
384 address = ADDRESS; \
385 WRITEBACK; \
386 BODY;)
387
388#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
395
396#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
407
408#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
421
422#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
423 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
424 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
425
426#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
427 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
428 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
429 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
430 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
431 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
433
434#define ARM_MS_PRE \
435 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
436 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
437
438#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
439
440#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
441 DEFINE_INSTRUCTION_ARM(NAME, \
442 int rn = (opcode >> 16) & 0xF; \
443 int rs = opcode & 0x0000FFFF; \
444 uint32_t address = cpu->gprs[rn]; \
445 S_PRE; \
446 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
447 S_POST; \
448 POST_BODY; \
449 WRITEBACK;)
450
451
452#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
464 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
465 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
469
470// Begin ALU definitions
471
472DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
473 int32_t n = cpu->gprs[rn];
474 cpu->gprs[rd] = n + cpu->shifterOperand;)
475
476DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], ARMPSRGetC(cpu->cpsr)),
477 int32_t n = cpu->gprs[rn];
478 cpu->gprs[rd] = n + cpu->shifterOperand + ARMPSRGetC(cpu->cpsr);)
479
480DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
481 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
482
483DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
484 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
487 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
490 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
493 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
496 cpu->gprs[rd] = cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = ~cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
502 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
505 int32_t n = cpu->gprs[rn];
506 cpu->gprs[rd] = cpu->shifterOperand - n;)
507
508DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
509 int32_t n = cpu->gprs[rn];
510 cpu->gprs[rd] = cpu->shifterOperand - n - !ARMPSRIsC(cpu->cpsr);)
511
512DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
513 int32_t n = cpu->gprs[rn];
514 cpu->gprs[rd] = n - cpu->shifterOperand - !ARMPSRIsC(cpu->cpsr);)
515
516DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
517 int32_t n = cpu->gprs[rn];
518 cpu->gprs[rd] = n - cpu->shifterOperand;)
519
520DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
521 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
522
523DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
524 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
525
526// End ALU definitions
527
528// Begin multiply definitions
529
530DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
531DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
532
533DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
534 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
535 int32_t dm = cpu->gprs[rd];
536 int32_t dn = d;
537 cpu->gprs[rd] = dm + dn;
538 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
539 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
540
541DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
542 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
543 cpu->gprs[rd] = d;
544 cpu->gprs[rdHi] = d >> 32;,
545 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
546
547DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
548 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
549 int32_t dm = cpu->gprs[rd];
550 int32_t dn = d;
551 cpu->gprs[rd] = dm + dn;
552 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
553 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
554
555DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
556 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
557 cpu->gprs[rd] = d;
558 cpu->gprs[rdHi] = d >> 32;,
559 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
560
561// End multiply definitions
562
563// Begin load/store definitions
564
565DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
566DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
567DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
568DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
569DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
570DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
571DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
572DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
573
574DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
575 enum PrivilegeMode priv = cpu->privilegeMode;
576 ARMSetPrivilegeMode(cpu, MODE_USER);
577 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
578 ARMSetPrivilegeMode(cpu, priv);
579 cpu->gprs[rd] = r;
580 ARM_LOAD_POST_BODY;)
581
582DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
583 enum PrivilegeMode priv = cpu->privilegeMode;
584 ARMSetPrivilegeMode(cpu, MODE_USER);
585 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
586 ARMSetPrivilegeMode(cpu, priv);
587 cpu->gprs[rd] = r;
588 ARM_LOAD_POST_BODY;)
589
590DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
591 enum PrivilegeMode priv = cpu->privilegeMode;
592 int32_t r = cpu->gprs[rd];
593 ARMSetPrivilegeMode(cpu, MODE_USER);
594 cpu->memory.store8(cpu, address, r, ¤tCycles);
595 ARMSetPrivilegeMode(cpu, priv);
596 ARM_STORE_POST_BODY;)
597
598DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
599 enum PrivilegeMode priv = cpu->privilegeMode;
600 int32_t r = cpu->gprs[rd];
601 ARMSetPrivilegeMode(cpu, MODE_USER);
602 cpu->memory.store32(cpu, address, r, ¤tCycles);
603 ARMSetPrivilegeMode(cpu, priv);
604 ARM_STORE_POST_BODY;)
605
606DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
607 load,
608 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
609 if (rs & 0x8000) {
610 ARM_WRITE_PC;
611 })
612
613DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
614 store,
615 ARM_STORE_POST_BODY;)
616
617DEFINE_INSTRUCTION_ARM(SWP,
618 int rm = opcode & 0xF;
619 int rd = (opcode >> 12) & 0xF;
620 int rn = (opcode >> 16) & 0xF;
621 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
622 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
623 cpu->gprs[rd] = d;)
624
625DEFINE_INSTRUCTION_ARM(SWPB,
626 int rm = opcode & 0xF;
627 int rd = (opcode >> 12) & 0xF;
628 int rn = (opcode >> 16) & 0xF;
629 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
630 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
631 cpu->gprs[rd] = d;)
632
633// End load/store definitions
634
635// Begin branch definitions
636
637DEFINE_INSTRUCTION_ARM(B,
638 int32_t offset = opcode << 8;
639 offset >>= 6;
640 cpu->gprs[ARM_PC] += offset;
641 ARM_WRITE_PC;)
642
643DEFINE_INSTRUCTION_ARM(BL,
644 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
645 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
646 cpu->gprs[ARM_PC] += immediate >> 6;
647 ARM_WRITE_PC;)
648
649DEFINE_INSTRUCTION_ARM(BX,
650 int rm = opcode & 0x0000000F;
651 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
652 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
653 if (cpu->executionMode == MODE_THUMB) {
654 THUMB_WRITE_PC;
655 } else {
656 ARM_WRITE_PC;
657 })
658
659// End branch definitions
660
661// Begin coprocessor definitions
662
663DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
664DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
665DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
666DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
667DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
668
669// Begin miscellaneous definitions
670
671DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
672DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
673
674DEFINE_INSTRUCTION_ARM(MSR,
675 int c = opcode & 0x00010000;
676 int f = opcode & 0x00080000;
677 int32_t operand = cpu->gprs[opcode & 0x0000000F];
678 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
679 if (mask & PSR_USER_MASK) {
680 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
681 }
682 if (mask & PSR_STATE_MASK) {
683 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
684 }
685 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
686 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
687 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
688 }
689 _ARMReadCPSR(cpu);
690 if (cpu->executionMode == MODE_THUMB) {
691 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
692 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
693 } else {
694 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
695 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
696 })
697
698DEFINE_INSTRUCTION_ARM(MSRR,
699 int c = opcode & 0x00010000;
700 int f = opcode & 0x00080000;
701 int32_t operand = cpu->gprs[opcode & 0x0000000F];
702 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
703 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
704 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
705
706DEFINE_INSTRUCTION_ARM(MRS, \
707 int rd = (opcode >> 12) & 0xF; \
708 cpu->gprs[rd] = cpu->cpsr;)
709
710DEFINE_INSTRUCTION_ARM(MRSR, \
711 int rd = (opcode >> 12) & 0xF; \
712 cpu->gprs[rd] = cpu->spsr;)
713
714DEFINE_INSTRUCTION_ARM(MSRI,
715 int c = opcode & 0x00010000;
716 int f = opcode & 0x00080000;
717 int rotate = (opcode & 0x00000F00) >> 7;
718 int32_t operand = ROR(opcode & 0x000000FF, rotate);
719 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
720 if (mask & PSR_USER_MASK) {
721 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
722 }
723 if (mask & PSR_STATE_MASK) {
724 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
725 }
726 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
727 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
728 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
729 }
730 _ARMReadCPSR(cpu);
731 if (cpu->executionMode == MODE_THUMB) {
732 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
733 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
734 } else {
735 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
736 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
737 })
738
739DEFINE_INSTRUCTION_ARM(MSRRI,
740 int c = opcode & 0x00010000;
741 int f = opcode & 0x00080000;
742 int rotate = (opcode & 0x00000F00) >> 7;
743 int32_t operand = ROR(opcode & 0x000000FF, rotate);
744 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
745 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
746 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
747
748DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
749
750const ARMInstruction _armTable[0x1000] = {
751 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
752};