src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-thumb.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/emitter-thumb.h>
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 { \
16 ARMPSR cpsr = 0; \
17 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
18 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
19 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM(M, N, D)); \
20 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
21 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
22 }
23
24#define THUMB_ADDITION_CARRY_S(M, N, D, C) \
25 { \
26 ARMPSR cpsr = 0; \
27 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
28 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
29 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM_CARRY(M, N, D, C)); \
30 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
31 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
32 }
33
34#define THUMB_SUBTRACTION_S(M, N, D) \
35 { \
36 ARMPSR cpsr = 0; \
37 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
38 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
39 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM(M, N, D)); \
40 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
41 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
42 }
43
44#define THUMB_NEUTRAL_S(M, N, D) \
45{ \
46 ARMPSR cpsr = 0; \
47 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
48 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
49 cpu->cpsr = (cpu->cpsr & (0x3FFFFFFF)) | cpsr; \
50 }
51
52#define THUMB_ADDITION(D, M, N) \
53 int n = N; \
54 int m = M; \
55 D = M + N; \
56 THUMB_ADDITION_S(m, n, D)
57
58#define THUMB_SUBTRACTION(D, M, N) \
59 int n = N; \
60 int m = M; \
61 D = M - N; \
62 THUMB_SUBTRACTION_S(m, n, D)
63
64#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
65
66#define THUMB_LOAD_POST_BODY \
67 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
68
69#define THUMB_STORE_POST_BODY \
70 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
71
72#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
73 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
74 int currentCycles = THUMB_PREFETCH_CYCLES; \
75 BODY; \
76 cpu->cycles += currentCycles; \
77 }
78
79#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
80 DEFINE_INSTRUCTION_THUMB(NAME, \
81 int immediate = (opcode >> 6) & 0x001F; \
82 int rd = opcode & 0x0007; \
83 int rm = (opcode >> 3) & 0x0007; \
84 BODY;)
85
86DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
87 if (!immediate) {
88 cpu->gprs[rd] = cpu->gprs[rm];
89 } else {
90 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (32 - immediate)) & 1);
91 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
92 }
93 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
94
95DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
96 if (!immediate) {
97 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rm]));
98 cpu->gprs[rd] = 0;
99 } else {
100 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (immediate - 1)) & 1);
101 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
102 }
103 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
104
105DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
106 if (!immediate) {
107 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rm]));
108 if (ARMPSRIsC(cpu->cpsr)) {
109 cpu->gprs[rd] = 0xFFFFFFFF;
110 } else {
111 cpu->gprs[rd] = 0;
112 }
113 } else {
114 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (immediate - 1)) & 1);
115 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
116 }
117 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
118
119DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
120DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
121DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
122DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
123DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
124DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
125
126#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
127 DEFINE_INSTRUCTION_THUMB(NAME, \
128 int rm = (opcode >> 6) & 0x0007; \
129 int rd = opcode & 0x0007; \
130 int rn = (opcode >> 3) & 0x0007; \
131 BODY;)
132
133DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
134DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
135
136#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
137 DEFINE_INSTRUCTION_THUMB(NAME, \
138 int immediate = (opcode >> 6) & 0x0007; \
139 int rd = opcode & 0x0007; \
140 int rn = (opcode >> 3) & 0x0007; \
141 BODY;)
142
143DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
144DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
145
146#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
147 DEFINE_INSTRUCTION_THUMB(NAME, \
148 int rd = (opcode >> 8) & 0x0007; \
149 int immediate = opcode & 0x00FF; \
150 BODY;)
151
152DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
153DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
154DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
155DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
156
157#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
158 DEFINE_INSTRUCTION_THUMB(NAME, \
159 int rd = opcode & 0x0007; \
160 int rn = (opcode >> 3) & 0x0007; \
161 BODY;)
162
163DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
164DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
165DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
166 int rs = cpu->gprs[rn] & 0xFF;
167 if (rs) {
168 if (rs < 32) {
169 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (32 - rs)) & 1);
170 cpu->gprs[rd] <<= rs;
171 } else {
172 if (rs > 32) {
173 cpu->cpsr = ARMPSRClearC(cpu->cpsr);
174 } else {
175 cpu->cpsr = ARMPSRSetC(cpu->cpsr, cpu->gprs[rd] & 0x00000001);
176 }
177 cpu->gprs[rd] = 0;
178 }
179 }
180 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
181
182DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
183 int rs = cpu->gprs[rn] & 0xFF;
184 if (rs) {
185 if (rs < 32) {
186 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (rs - 1)) & 1);
187 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
188 } else {
189 if (rs > 32) {
190 cpu->cpsr = ARMPSRClearC(cpu->cpsr);
191 } else {
192 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
193 }
194 cpu->gprs[rd] = 0;
195 }
196 }
197 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
198
199DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
200 int rs = cpu->gprs[rn] & 0xFF;
201 if (rs) {
202 if (rs < 32) {
203 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (rs - 1)) & 1);
204 cpu->gprs[rd] >>= rs;
205 } else {
206 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
207 if (ARMPSRIsC(cpu->cpsr)) {
208 cpu->gprs[rd] = 0xFFFFFFFF;
209 } else {
210 cpu->gprs[rd] = 0;
211 }
212 }
213 }
214 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
215
216DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
217 int n = cpu->gprs[rn];
218 int d = cpu->gprs[rd];
219 cpu->gprs[rd] = d + n + ARMPSRGetC(cpu->cpsr);
220 THUMB_ADDITION_CARRY_S(d, n, cpu->gprs[rd], ARMPSRGetC(cpu->cpsr));)
221
222DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
223 int n = cpu->gprs[rn] + !ARMPSRIsC(cpu->cpsr);
224 int d = cpu->gprs[rd];
225 cpu->gprs[rd] = d - n;
226 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
227DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
228 int rs = cpu->gprs[rn] & 0xFF;
229 if (rs) {
230 int r4 = rs & 0x1F;
231 if (r4 > 0) {
232 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (r4 - 1)) & 1);
233 cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
234 } else {
235 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
236 }
237 }
238 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
239DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
240DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
241DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
242DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
243DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
244DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
245DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
246DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
247
248#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
249 DEFINE_INSTRUCTION_THUMB(NAME, \
250 int rd = (opcode & 0x0007) | H1; \
251 int rm = ((opcode >> 3) & 0x0007) | H2; \
252 BODY;)
253
254#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
255 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
256 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
257 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
258 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
259
260DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
261 cpu->gprs[rd] += cpu->gprs[rm];
262 if (rd == ARM_PC) {
263 THUMB_WRITE_PC;
264 })
265
266DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
267DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
268 cpu->gprs[rd] = cpu->gprs[rm];
269 if (rd == ARM_PC) {
270 THUMB_WRITE_PC;
271 })
272
273#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
274 DEFINE_INSTRUCTION_THUMB(NAME, \
275 int rd = (opcode >> 8) & 0x0007; \
276 int immediate = (opcode & 0x00FF) << 2; \
277 BODY;)
278
279DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
280DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
281DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
282
283DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
284DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
285
286#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
287 DEFINE_INSTRUCTION_THUMB(NAME, \
288 int rm = (opcode >> 6) & 0x0007; \
289 int rd = opcode & 0x0007; \
290 int rn = (opcode >> 3) & 0x0007; \
291 BODY;)
292
293DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
294DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
295DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
296DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
297DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, rm = cpu->gprs[rn] + cpu->gprs[rm]; cpu->gprs[rd] = rm & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, rm, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, rm, ¤tCycles)); THUMB_LOAD_POST_BODY;)
298DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
299DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
300DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
301
302#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
303 DEFINE_INSTRUCTION_THUMB(NAME, \
304 int rn = RN; \
305 UNUSED(rn); \
306 int rs = opcode & 0xFF; \
307 int32_t address = cpu->gprs[RN]; \
308 PRE_BODY; \
309 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
310 WRITEBACK;)
311
312DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
313 (opcode >> 8) & 0x0007,
314 load,
315 IA,
316 ,
317 THUMB_LOAD_POST_BODY;
318 if (!((1 << rn) & rs)) {
319 cpu->gprs[rn] = address;
320 })
321
322DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
323 (opcode >> 8) & 0x0007,
324 store,
325 IA,
326 ,
327 THUMB_STORE_POST_BODY;
328 cpu->gprs[rn] = address;)
329
330#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
331 DEFINE_INSTRUCTION_THUMB(B ## COND, \
332 if (ARM_COND_ ## COND) { \
333 int8_t immediate = opcode; \
334 cpu->gprs[ARM_PC] += (int32_t) immediate << 1; \
335 THUMB_WRITE_PC; \
336 })
337
338DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
339DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
340DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
341DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
342DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
343DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
344DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
345DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
346DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
347DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
348DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
349DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
350DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
351DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
352
353DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
354DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
355
356DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
357 ARM_SP,
358 load,
359 IA,
360 ,
361 THUMB_LOAD_POST_BODY;
362 cpu->gprs[ARM_SP] = address)
363
364DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
365 ARM_SP,
366 load,
367 IA,
368 rs |= 1 << ARM_PC,
369 THUMB_LOAD_POST_BODY;
370 cpu->gprs[ARM_SP] = address;
371 THUMB_WRITE_PC;)
372
373DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
374 ARM_SP,
375 store,
376 DB,
377 ,
378 THUMB_STORE_POST_BODY;
379 cpu->gprs[ARM_SP] = address)
380
381DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
382 ARM_SP,
383 store,
384 DB,
385 rs |= 1 << ARM_LR,
386 THUMB_STORE_POST_BODY;
387 cpu->gprs[ARM_SP] = address)
388
389DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
390DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
391DEFINE_INSTRUCTION_THUMB(B,
392 int16_t immediate = (opcode & 0x07FF) << 5;
393 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
394 THUMB_WRITE_PC;)
395
396DEFINE_INSTRUCTION_THUMB(BL1,
397 int16_t immediate = (opcode & 0x07FF) << 5;
398 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
399
400DEFINE_INSTRUCTION_THUMB(BL2,
401 uint16_t immediate = (opcode & 0x07FF) << 1;
402 uint32_t pc = cpu->gprs[ARM_PC];
403 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
404 cpu->gprs[ARM_LR] = pc - 1;
405 THUMB_WRITE_PC;)
406
407DEFINE_INSTRUCTION_THUMB(BX,
408 int rm = (opcode >> 3) & 0xF;
409 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
410 int misalign = 0;
411 if (rm == ARM_PC) {
412 misalign = cpu->gprs[rm] & 0x00000002;
413 }
414 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
415 if (cpu->executionMode == MODE_THUMB) {
416 THUMB_WRITE_PC;
417 } else {
418 ARM_WRITE_PC;
419 })
420
421DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
422
423const ThumbInstruction _thumbTable[0x400] = {
424 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
425};