src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_IE] = 0xE0,
105};
106
107static void _writeSGBBits(struct GB* gb, int bits) {
108 if (!bits) {
109 gb->sgbBit = -1;
110 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
111 }
112 if (bits == gb->currentSgbBits) {
113 return;
114 }
115 gb->currentSgbBits = bits;
116 if (gb->sgbBit == 128 && bits == 2) {
117 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
118 ++gb->sgbBit;
119 }
120 if (gb->sgbBit >= 128) {
121 return;
122 }
123 switch (bits) {
124 case 1:
125 if (gb->sgbBit < 0) {
126 return;
127 }
128 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
129 break;
130 case 3:
131 ++gb->sgbBit;
132 default:
133 break;
134 }
135}
136
137void GBIOInit(struct GB* gb) {
138 memset(gb->memory.io, 0, sizeof(gb->memory.io));
139}
140
141void GBIOReset(struct GB* gb) {
142 memset(gb->memory.io, 0, sizeof(gb->memory.io));
143
144 GBIOWrite(gb, REG_TIMA, 0);
145 GBIOWrite(gb, REG_TMA, 0);
146 GBIOWrite(gb, REG_TAC, 0);
147 GBIOWrite(gb, REG_IF, 1);
148 GBIOWrite(gb, REG_NR52, 0xF1);
149 GBIOWrite(gb, REG_NR14, 0x3F);
150 GBIOWrite(gb, REG_NR10, 0x80);
151 GBIOWrite(gb, REG_NR11, 0xBF);
152 GBIOWrite(gb, REG_NR12, 0xF3);
153 GBIOWrite(gb, REG_NR13, 0xF3);
154 GBIOWrite(gb, REG_NR24, 0x3F);
155 GBIOWrite(gb, REG_NR21, 0x3F);
156 GBIOWrite(gb, REG_NR22, 0x00);
157 GBIOWrite(gb, REG_NR34, 0x3F);
158 GBIOWrite(gb, REG_NR30, 0x7F);
159 GBIOWrite(gb, REG_NR31, 0xFF);
160 GBIOWrite(gb, REG_NR32, 0x9F);
161 GBIOWrite(gb, REG_NR44, 0x3F);
162 GBIOWrite(gb, REG_NR41, 0xFF);
163 GBIOWrite(gb, REG_NR42, 0x00);
164 GBIOWrite(gb, REG_NR43, 0x00);
165 GBIOWrite(gb, REG_NR50, 0x77);
166 GBIOWrite(gb, REG_NR51, 0xF3);
167 GBIOWrite(gb, REG_LCDC, 0x91);
168 GBIOWrite(gb, REG_SCY, 0x00);
169 GBIOWrite(gb, REG_SCX, 0x00);
170 GBIOWrite(gb, REG_LYC, 0x00);
171 GBIOWrite(gb, REG_BGP, 0xFC);
172 if (gb->model < GB_MODEL_CGB) {
173 GBIOWrite(gb, REG_OBP0, 0xFF);
174 GBIOWrite(gb, REG_OBP1, 0xFF);
175 }
176 GBIOWrite(gb, REG_WY, 0x00);
177 GBIOWrite(gb, REG_WX, 0x00);
178 if (gb->model >= GB_MODEL_CGB) {
179 GBIOWrite(gb, REG_UNK4C, 0);
180 GBIOWrite(gb, REG_JOYP, 0xFF);
181 GBIOWrite(gb, REG_VBK, 0);
182 GBIOWrite(gb, REG_BCPS, 0);
183 GBIOWrite(gb, REG_OCPS, 0);
184 GBIOWrite(gb, REG_SVBK, 1);
185 GBIOWrite(gb, REG_HDMA1, 0xFF);
186 GBIOWrite(gb, REG_HDMA2, 0xFF);
187 GBIOWrite(gb, REG_HDMA3, 0xFF);
188 GBIOWrite(gb, REG_HDMA4, 0xFF);
189 gb->memory.io[REG_HDMA5] = 0xFF;
190 } else if (gb->model == GB_MODEL_SGB) {
191 GBIOWrite(gb, REG_JOYP, 0xFF);
192 }
193 GBIOWrite(gb, REG_IE, 0x00);
194}
195
196void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
197 switch (address) {
198 case REG_SB:
199 GBSIOWriteSB(&gb->sio, value);
200 break;
201 case REG_SC:
202 GBSIOWriteSC(&gb->sio, value);
203 break;
204 case REG_DIV:
205 GBTimerDivReset(&gb->timer);
206 return;
207 case REG_NR10:
208 if (gb->audio.enable) {
209 GBAudioWriteNR10(&gb->audio, value);
210 } else {
211 value = 0;
212 }
213 break;
214 case REG_NR11:
215 if (gb->audio.enable) {
216 GBAudioWriteNR11(&gb->audio, value);
217 } else {
218 if (gb->audio.style == GB_AUDIO_DMG) {
219 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
220 }
221 value = 0;
222 }
223 break;
224 case REG_NR12:
225 if (gb->audio.enable) {
226 GBAudioWriteNR12(&gb->audio, value);
227 } else {
228 value = 0;
229 }
230 break;
231 case REG_NR13:
232 if (gb->audio.enable) {
233 GBAudioWriteNR13(&gb->audio, value);
234 } else {
235 value = 0;
236 }
237 break;
238 case REG_NR14:
239 if (gb->audio.enable) {
240 GBAudioWriteNR14(&gb->audio, value);
241 } else {
242 value = 0;
243 }
244 break;
245 case REG_NR21:
246 if (gb->audio.enable) {
247 GBAudioWriteNR21(&gb->audio, value);
248 } else {
249 if (gb->audio.style == GB_AUDIO_DMG) {
250 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
251 }
252 value = 0;
253 }
254 break;
255 case REG_NR22:
256 if (gb->audio.enable) {
257 GBAudioWriteNR22(&gb->audio, value);
258 } else {
259 value = 0;
260 }
261 break;
262 case REG_NR23:
263 if (gb->audio.enable) {
264 GBAudioWriteNR23(&gb->audio, value);
265 } else {
266 value = 0;
267 }
268 break;
269 case REG_NR24:
270 if (gb->audio.enable) {
271 GBAudioWriteNR24(&gb->audio, value);
272 } else {
273 value = 0;
274 }
275 break;
276 case REG_NR30:
277 if (gb->audio.enable) {
278 GBAudioWriteNR30(&gb->audio, value);
279 } else {
280 value = 0;
281 }
282 break;
283 case REG_NR31:
284 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
285 GBAudioWriteNR31(&gb->audio, value);
286 } else {
287 value = 0;
288 }
289 break;
290 case REG_NR32:
291 if (gb->audio.enable) {
292 GBAudioWriteNR32(&gb->audio, value);
293 } else {
294 value = 0;
295 }
296 break;
297 case REG_NR33:
298 if (gb->audio.enable) {
299 GBAudioWriteNR33(&gb->audio, value);
300 } else {
301 value = 0;
302 }
303 break;
304 case REG_NR34:
305 if (gb->audio.enable) {
306 GBAudioWriteNR34(&gb->audio, value);
307 } else {
308 value = 0;
309 }
310 break;
311 case REG_NR41:
312 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
313 GBAudioWriteNR41(&gb->audio, value);
314 } else {
315 value = 0;
316 }
317 break;
318 case REG_NR42:
319 if (gb->audio.enable) {
320 GBAudioWriteNR42(&gb->audio, value);
321 } else {
322 value = 0;
323 }
324 break;
325 case REG_NR43:
326 if (gb->audio.enable) {
327 GBAudioWriteNR43(&gb->audio, value);
328 } else {
329 value = 0;
330 }
331 break;
332 case REG_NR44:
333 if (gb->audio.enable) {
334 GBAudioWriteNR44(&gb->audio, value);
335 } else {
336 value = 0;
337 }
338 break;
339 case REG_NR50:
340 if (gb->audio.enable) {
341 GBAudioWriteNR50(&gb->audio, value);
342 } else {
343 value = 0;
344 }
345 break;
346 case REG_NR51:
347 if (gb->audio.enable) {
348 GBAudioWriteNR51(&gb->audio, value);
349 } else {
350 value = 0;
351 }
352 break;
353 case REG_NR52:
354 GBAudioWriteNR52(&gb->audio, value);
355 value &= 0x80;
356 value |= gb->memory.io[REG_NR52] & 0x0F;
357 break;
358 case REG_WAVE_0:
359 case REG_WAVE_1:
360 case REG_WAVE_2:
361 case REG_WAVE_3:
362 case REG_WAVE_4:
363 case REG_WAVE_5:
364 case REG_WAVE_6:
365 case REG_WAVE_7:
366 case REG_WAVE_8:
367 case REG_WAVE_9:
368 case REG_WAVE_A:
369 case REG_WAVE_B:
370 case REG_WAVE_C:
371 case REG_WAVE_D:
372 case REG_WAVE_E:
373 case REG_WAVE_F:
374 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
375 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
376 } else if(gb->audio.ch3.readable) {
377 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
378 }
379 break;
380 case REG_JOYP:
381 if (gb->model == GB_MODEL_SGB) {
382 _writeSGBBits(gb, (value >> 4) & 3);
383 }
384 break;
385 case REG_TIMA:
386 if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 1) {
387 mTimingDeschedule(&gb->timing, &gb->timer.irq);
388 }
389 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
390 return;
391 }
392 break;
393 case REG_TMA:
394 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
395 gb->memory.io[REG_TIMA] = value;
396 }
397 break;
398 case REG_TAC:
399 value = GBTimerUpdateTAC(&gb->timer, value);
400 break;
401 case REG_IF:
402 gb->memory.io[REG_IF] = value | 0xE0;
403 GBUpdateIRQs(gb);
404 return;
405 case REG_LCDC:
406 // TODO: handle GBC differences
407 GBVideoProcessDots(&gb->video, 0);
408 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
409 GBVideoWriteLCDC(&gb->video, value);
410 break;
411 case REG_LYC:
412 GBVideoWriteLYC(&gb->video, value);
413 break;
414 case REG_DMA:
415 GBMemoryDMA(gb, value << 8);
416 break;
417 case REG_SCY:
418 case REG_SCX:
419 case REG_WY:
420 case REG_WX:
421 GBVideoProcessDots(&gb->video, 0);
422 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
423 break;
424 case REG_BGP:
425 case REG_OBP0:
426 case REG_OBP1:
427 GBVideoProcessDots(&gb->video, 0);
428 GBVideoWritePalette(&gb->video, address, value);
429 break;
430 case REG_STAT:
431 GBVideoWriteSTAT(&gb->video, value);
432 value = gb->video.stat;
433 break;
434 case 0x50:
435 GBUnmapBIOS(gb);
436 if (gb->model >= GB_MODEL_CGB && gb->memory.io[REG_UNK4C] < 0x80) {
437 gb->model = GB_MODEL_DMG;
438 GBVideoDisableCGB(&gb->video);
439 }
440 break;
441 case REG_IE:
442 gb->memory.ie = value;
443 GBUpdateIRQs(gb);
444 return;
445 default:
446 if (gb->model >= GB_MODEL_CGB) {
447 switch (address) {
448 case REG_UNK4C:
449 break;
450 case REG_KEY1:
451 value &= 0x1;
452 value |= gb->memory.io[address] & 0x80;
453 break;
454 case REG_VBK:
455 GBVideoSwitchBank(&gb->video, value);
456 break;
457 case REG_HDMA1:
458 case REG_HDMA2:
459 case REG_HDMA3:
460 case REG_HDMA4:
461 // Handled transparently by the registers
462 break;
463 case REG_HDMA5:
464 value = GBMemoryWriteHDMA5(gb, value);
465 break;
466 case REG_BCPS:
467 gb->video.bcpIndex = value & 0x3F;
468 gb->video.bcpIncrement = value & 0x80;
469 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
470 break;
471 case REG_BCPD:
472 GBVideoProcessDots(&gb->video, 0);
473 GBVideoWritePalette(&gb->video, address, value);
474 return;
475 case REG_OCPS:
476 gb->video.ocpIndex = value & 0x3F;
477 gb->video.ocpIncrement = value & 0x80;
478 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
479 break;
480 case REG_OCPD:
481 GBVideoProcessDots(&gb->video, 0);
482 GBVideoWritePalette(&gb->video, address, value);
483 return;
484 case REG_SVBK:
485 GBMemorySwitchWramBank(&gb->memory, value);
486 value = gb->memory.wramCurrentBank;
487 break;
488 default:
489 goto failed;
490 }
491 goto success;
492 }
493 failed:
494 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
495 if (address >= GB_SIZE_IO) {
496 return;
497 }
498 break;
499 }
500 success:
501 gb->memory.io[address] = value;
502}
503
504static uint8_t _readKeys(struct GB* gb) {
505 uint8_t keys = *gb->keySource;
506 switch (gb->memory.io[REG_JOYP] & 0x30) {
507 case 0x30:
508 // TODO: Increment
509 keys = (gb->video.sgbCommandHeader >> 3) == SGB_MLT_REG ? 0xF : 0;
510 break;
511 case 0x20:
512 keys >>= 4;
513 break;
514 case 0x10:
515 break;
516 case 0x00:
517 keys |= keys >> 4;
518 break;
519 }
520 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
521}
522
523uint8_t GBIORead(struct GB* gb, unsigned address) {
524 switch (address) {
525 case REG_JOYP:
526 return _readKeys(gb);
527 case REG_IE:
528 return gb->memory.ie;
529 case REG_WAVE_0:
530 case REG_WAVE_1:
531 case REG_WAVE_2:
532 case REG_WAVE_3:
533 case REG_WAVE_4:
534 case REG_WAVE_5:
535 case REG_WAVE_6:
536 case REG_WAVE_7:
537 case REG_WAVE_8:
538 case REG_WAVE_9:
539 case REG_WAVE_A:
540 case REG_WAVE_B:
541 case REG_WAVE_C:
542 case REG_WAVE_D:
543 case REG_WAVE_E:
544 case REG_WAVE_F:
545 if (gb->audio.playingCh3) {
546 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
547 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
548 } else {
549 return 0xFF;
550 }
551 } else {
552 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
553 }
554 break;
555 case REG_SB:
556 case REG_SC:
557 case REG_IF:
558 case REG_NR10:
559 case REG_NR11:
560 case REG_NR12:
561 case REG_NR14:
562 case REG_NR21:
563 case REG_NR22:
564 case REG_NR24:
565 case REG_NR30:
566 case REG_NR32:
567 case REG_NR34:
568 case REG_NR41:
569 case REG_NR42:
570 case REG_NR43:
571 case REG_NR44:
572 case REG_NR50:
573 case REG_NR51:
574 case REG_NR52:
575 case REG_DIV:
576 case REG_TIMA:
577 case REG_TMA:
578 case REG_TAC:
579 case REG_STAT:
580 case REG_LCDC:
581 case REG_SCY:
582 case REG_SCX:
583 case REG_LY:
584 case REG_LYC:
585 case REG_BGP:
586 case REG_OBP0:
587 case REG_OBP1:
588 case REG_WY:
589 case REG_WX:
590 // Handled transparently by the registers
591 break;
592 default:
593 if (gb->model >= GB_MODEL_CGB) {
594 switch (address) {
595 case REG_KEY1:
596 case REG_VBK:
597 case REG_HDMA1:
598 case REG_HDMA2:
599 case REG_HDMA3:
600 case REG_HDMA4:
601 case REG_HDMA5:
602 case REG_BCPS:
603 case REG_BCPD:
604 case REG_OCPS:
605 case REG_OCPD:
606 case REG_SVBK:
607 // Handled transparently by the registers
608 goto success;
609 case REG_DMA:
610 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
611 return 0;
612 default:
613 break;
614 }
615 }
616 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
617 return 0xFF;
618 }
619 success:
620 return gb->memory.io[address] | _registerMask[address];
621}
622
623void GBTestKeypadIRQ(struct GB* gb) {
624 if (_readKeys(gb)) {
625 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
626 GBUpdateIRQs(gb);
627 }
628}
629
630struct GBSerializedState;
631void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
632 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
633 state->ie = gb->memory.ie;
634}
635
636void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
637 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
638 gb->memory.ie = state->ie;
639
640 if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
641 GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
642 GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
643 GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
644 GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
645 gb->audio.ch1.control.frequency &= 0xFF;
646 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
647 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
648 GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
649 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
650 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
651 gb->audio.ch2.control.frequency &= 0xFF;
652 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
653 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
654 GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
655 GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
656 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
657 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
658 gb->audio.ch3.rate &= 0xFF;
659 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
660 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
661 GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
662 GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
663 GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
664 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
665 GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
666 GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
667 }
668
669 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
670 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
671 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
672 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
673 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
674 if (gb->model == GB_MODEL_SGB) {
675 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
676 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
677 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
678 }
679 gb->video.stat = state->io[REG_STAT];
680}