src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_IE] = 0xE0,
105};
106
107static void _writeSGBBits(struct GB* gb, int bits) {
108 if (!bits) {
109 gb->sgbBit = -1;
110 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
111 }
112 if (bits == gb->currentSgbBits) {
113 return;
114 }
115 gb->currentSgbBits = bits;
116 if (bits == 3) {
117 gb->sgbCurrentController = (gb->sgbCurrentController + 1) & gb->sgbControllers;
118 }
119 if (gb->sgbBit == 128 && bits == 2) {
120 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
121 ++gb->sgbBit;
122 }
123 if (gb->sgbBit >= 128) {
124 return;
125 }
126 switch (bits) {
127 case 1:
128 if (gb->sgbBit < 0) {
129 return;
130 }
131 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
132 break;
133 case 3:
134 ++gb->sgbBit;
135 default:
136 break;
137 }
138}
139
140void GBIOInit(struct GB* gb) {
141 memset(gb->memory.io, 0, sizeof(gb->memory.io));
142}
143
144void GBIOReset(struct GB* gb) {
145 memset(gb->memory.io, 0, sizeof(gb->memory.io));
146
147 GBIOWrite(gb, REG_TIMA, 0);
148 GBIOWrite(gb, REG_TMA, 0);
149 GBIOWrite(gb, REG_TAC, 0);
150 GBIOWrite(gb, REG_IF, 1);
151 GBIOWrite(gb, REG_NR52, 0xF1);
152 GBIOWrite(gb, REG_NR14, 0x3F);
153 GBIOWrite(gb, REG_NR10, 0x80);
154 GBIOWrite(gb, REG_NR11, 0xBF);
155 GBIOWrite(gb, REG_NR12, 0xF3);
156 GBIOWrite(gb, REG_NR13, 0xF3);
157 GBIOWrite(gb, REG_NR24, 0x3F);
158 GBIOWrite(gb, REG_NR21, 0x3F);
159 GBIOWrite(gb, REG_NR22, 0x00);
160 GBIOWrite(gb, REG_NR34, 0x3F);
161 GBIOWrite(gb, REG_NR30, 0x7F);
162 GBIOWrite(gb, REG_NR31, 0xFF);
163 GBIOWrite(gb, REG_NR32, 0x9F);
164 GBIOWrite(gb, REG_NR44, 0x3F);
165 GBIOWrite(gb, REG_NR41, 0xFF);
166 GBIOWrite(gb, REG_NR42, 0x00);
167 GBIOWrite(gb, REG_NR43, 0x00);
168 GBIOWrite(gb, REG_NR50, 0x77);
169 GBIOWrite(gb, REG_NR51, 0xF3);
170 GBIOWrite(gb, REG_LCDC, 0x91);
171 GBIOWrite(gb, REG_SCY, 0x00);
172 GBIOWrite(gb, REG_SCX, 0x00);
173 GBIOWrite(gb, REG_LYC, 0x00);
174 GBIOWrite(gb, REG_BGP, 0xFC);
175 if (gb->model < GB_MODEL_CGB) {
176 GBIOWrite(gb, REG_OBP0, 0xFF);
177 GBIOWrite(gb, REG_OBP1, 0xFF);
178 }
179 GBIOWrite(gb, REG_WY, 0x00);
180 GBIOWrite(gb, REG_WX, 0x00);
181 if (gb->model >= GB_MODEL_CGB) {
182 GBIOWrite(gb, REG_UNK4C, 0);
183 GBIOWrite(gb, REG_JOYP, 0xFF);
184 GBIOWrite(gb, REG_VBK, 0);
185 GBIOWrite(gb, REG_BCPS, 0);
186 GBIOWrite(gb, REG_OCPS, 0);
187 GBIOWrite(gb, REG_SVBK, 1);
188 GBIOWrite(gb, REG_HDMA1, 0xFF);
189 GBIOWrite(gb, REG_HDMA2, 0xFF);
190 GBIOWrite(gb, REG_HDMA3, 0xFF);
191 GBIOWrite(gb, REG_HDMA4, 0xFF);
192 gb->memory.io[REG_HDMA5] = 0xFF;
193 } else if (gb->model == GB_MODEL_SGB) {
194 GBIOWrite(gb, REG_JOYP, 0xFF);
195 }
196 GBIOWrite(gb, REG_IE, 0x00);
197}
198
199void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
200 switch (address) {
201 case REG_SB:
202 GBSIOWriteSB(&gb->sio, value);
203 break;
204 case REG_SC:
205 GBSIOWriteSC(&gb->sio, value);
206 break;
207 case REG_DIV:
208 GBTimerDivReset(&gb->timer);
209 return;
210 case REG_NR10:
211 if (gb->audio.enable) {
212 GBAudioWriteNR10(&gb->audio, value);
213 } else {
214 value = 0;
215 }
216 break;
217 case REG_NR11:
218 if (gb->audio.enable) {
219 GBAudioWriteNR11(&gb->audio, value);
220 } else {
221 if (gb->audio.style == GB_AUDIO_DMG) {
222 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
223 }
224 value = 0;
225 }
226 break;
227 case REG_NR12:
228 if (gb->audio.enable) {
229 GBAudioWriteNR12(&gb->audio, value);
230 } else {
231 value = 0;
232 }
233 break;
234 case REG_NR13:
235 if (gb->audio.enable) {
236 GBAudioWriteNR13(&gb->audio, value);
237 } else {
238 value = 0;
239 }
240 break;
241 case REG_NR14:
242 if (gb->audio.enable) {
243 GBAudioWriteNR14(&gb->audio, value);
244 } else {
245 value = 0;
246 }
247 break;
248 case REG_NR21:
249 if (gb->audio.enable) {
250 GBAudioWriteNR21(&gb->audio, value);
251 } else {
252 if (gb->audio.style == GB_AUDIO_DMG) {
253 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
254 }
255 value = 0;
256 }
257 break;
258 case REG_NR22:
259 if (gb->audio.enable) {
260 GBAudioWriteNR22(&gb->audio, value);
261 } else {
262 value = 0;
263 }
264 break;
265 case REG_NR23:
266 if (gb->audio.enable) {
267 GBAudioWriteNR23(&gb->audio, value);
268 } else {
269 value = 0;
270 }
271 break;
272 case REG_NR24:
273 if (gb->audio.enable) {
274 GBAudioWriteNR24(&gb->audio, value);
275 } else {
276 value = 0;
277 }
278 break;
279 case REG_NR30:
280 if (gb->audio.enable) {
281 GBAudioWriteNR30(&gb->audio, value);
282 } else {
283 value = 0;
284 }
285 break;
286 case REG_NR31:
287 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
288 GBAudioWriteNR31(&gb->audio, value);
289 } else {
290 value = 0;
291 }
292 break;
293 case REG_NR32:
294 if (gb->audio.enable) {
295 GBAudioWriteNR32(&gb->audio, value);
296 } else {
297 value = 0;
298 }
299 break;
300 case REG_NR33:
301 if (gb->audio.enable) {
302 GBAudioWriteNR33(&gb->audio, value);
303 } else {
304 value = 0;
305 }
306 break;
307 case REG_NR34:
308 if (gb->audio.enable) {
309 GBAudioWriteNR34(&gb->audio, value);
310 } else {
311 value = 0;
312 }
313 break;
314 case REG_NR41:
315 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
316 GBAudioWriteNR41(&gb->audio, value);
317 } else {
318 value = 0;
319 }
320 break;
321 case REG_NR42:
322 if (gb->audio.enable) {
323 GBAudioWriteNR42(&gb->audio, value);
324 } else {
325 value = 0;
326 }
327 break;
328 case REG_NR43:
329 if (gb->audio.enable) {
330 GBAudioWriteNR43(&gb->audio, value);
331 } else {
332 value = 0;
333 }
334 break;
335 case REG_NR44:
336 if (gb->audio.enable) {
337 GBAudioWriteNR44(&gb->audio, value);
338 } else {
339 value = 0;
340 }
341 break;
342 case REG_NR50:
343 if (gb->audio.enable) {
344 GBAudioWriteNR50(&gb->audio, value);
345 } else {
346 value = 0;
347 }
348 break;
349 case REG_NR51:
350 if (gb->audio.enable) {
351 GBAudioWriteNR51(&gb->audio, value);
352 } else {
353 value = 0;
354 }
355 break;
356 case REG_NR52:
357 GBAudioWriteNR52(&gb->audio, value);
358 value &= 0x80;
359 value |= gb->memory.io[REG_NR52] & 0x0F;
360 break;
361 case REG_WAVE_0:
362 case REG_WAVE_1:
363 case REG_WAVE_2:
364 case REG_WAVE_3:
365 case REG_WAVE_4:
366 case REG_WAVE_5:
367 case REG_WAVE_6:
368 case REG_WAVE_7:
369 case REG_WAVE_8:
370 case REG_WAVE_9:
371 case REG_WAVE_A:
372 case REG_WAVE_B:
373 case REG_WAVE_C:
374 case REG_WAVE_D:
375 case REG_WAVE_E:
376 case REG_WAVE_F:
377 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
378 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
379 } else if(gb->audio.ch3.readable) {
380 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
381 }
382 break;
383 case REG_JOYP:
384 if (gb->model == GB_MODEL_SGB) {
385 _writeSGBBits(gb, (value >> 4) & 3);
386 }
387 break;
388 case REG_TIMA:
389 if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 1) {
390 mTimingDeschedule(&gb->timing, &gb->timer.irq);
391 }
392 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
393 return;
394 }
395 break;
396 case REG_TMA:
397 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
398 gb->memory.io[REG_TIMA] = value;
399 }
400 break;
401 case REG_TAC:
402 value = GBTimerUpdateTAC(&gb->timer, value);
403 break;
404 case REG_IF:
405 gb->memory.io[REG_IF] = value | 0xE0;
406 GBUpdateIRQs(gb);
407 return;
408 case REG_LCDC:
409 // TODO: handle GBC differences
410 GBVideoProcessDots(&gb->video, 0);
411 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
412 GBVideoWriteLCDC(&gb->video, value);
413 break;
414 case REG_LYC:
415 GBVideoWriteLYC(&gb->video, value);
416 break;
417 case REG_DMA:
418 GBMemoryDMA(gb, value << 8);
419 break;
420 case REG_SCY:
421 case REG_SCX:
422 case REG_WY:
423 case REG_WX:
424 GBVideoProcessDots(&gb->video, 0);
425 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
426 break;
427 case REG_BGP:
428 case REG_OBP0:
429 case REG_OBP1:
430 GBVideoProcessDots(&gb->video, 0);
431 GBVideoWritePalette(&gb->video, address, value);
432 break;
433 case REG_STAT:
434 GBVideoWriteSTAT(&gb->video, value);
435 value = gb->video.stat;
436 break;
437 case 0x50:
438 GBUnmapBIOS(gb);
439 if (gb->model >= GB_MODEL_CGB && gb->memory.io[REG_UNK4C] < 0x80) {
440 gb->model = GB_MODEL_DMG;
441 GBVideoDisableCGB(&gb->video);
442 }
443 break;
444 case REG_IE:
445 gb->memory.ie = value;
446 GBUpdateIRQs(gb);
447 return;
448 default:
449 if (gb->model >= GB_MODEL_CGB) {
450 switch (address) {
451 case REG_UNK4C:
452 break;
453 case REG_KEY1:
454 value &= 0x1;
455 value |= gb->memory.io[address] & 0x80;
456 break;
457 case REG_VBK:
458 GBVideoSwitchBank(&gb->video, value);
459 break;
460 case REG_HDMA1:
461 case REG_HDMA2:
462 case REG_HDMA3:
463 case REG_HDMA4:
464 // Handled transparently by the registers
465 break;
466 case REG_HDMA5:
467 value = GBMemoryWriteHDMA5(gb, value);
468 break;
469 case REG_BCPS:
470 gb->video.bcpIndex = value & 0x3F;
471 gb->video.bcpIncrement = value & 0x80;
472 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
473 break;
474 case REG_BCPD:
475 GBVideoProcessDots(&gb->video, 0);
476 GBVideoWritePalette(&gb->video, address, value);
477 return;
478 case REG_OCPS:
479 gb->video.ocpIndex = value & 0x3F;
480 gb->video.ocpIncrement = value & 0x80;
481 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
482 break;
483 case REG_OCPD:
484 GBVideoProcessDots(&gb->video, 0);
485 GBVideoWritePalette(&gb->video, address, value);
486 return;
487 case REG_SVBK:
488 GBMemorySwitchWramBank(&gb->memory, value);
489 value = gb->memory.wramCurrentBank;
490 break;
491 default:
492 goto failed;
493 }
494 goto success;
495 }
496 failed:
497 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
498 if (address >= GB_SIZE_IO) {
499 return;
500 }
501 break;
502 }
503 success:
504 gb->memory.io[address] = value;
505}
506
507static uint8_t _readKeys(struct GB* gb) {
508 uint8_t keys = *gb->keySource;
509 if (gb->sgbCurrentController != 0) {
510 keys = 0;
511 }
512 switch (gb->memory.io[REG_JOYP] & 0x30) {
513 case 0x30:
514 // TODO: Increment
515 keys = (gb->video.sgbCommandHeader >> 3) == SGB_MLT_REQ ? 0xF - gb->sgbCurrentController : 0;
516 break;
517 case 0x20:
518 keys >>= 4;
519 break;
520 case 0x10:
521 break;
522 case 0x00:
523 keys |= keys >> 4;
524 break;
525 }
526 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
527}
528
529uint8_t GBIORead(struct GB* gb, unsigned address) {
530 switch (address) {
531 case REG_JOYP:
532 return _readKeys(gb);
533 case REG_IE:
534 return gb->memory.ie;
535 case REG_WAVE_0:
536 case REG_WAVE_1:
537 case REG_WAVE_2:
538 case REG_WAVE_3:
539 case REG_WAVE_4:
540 case REG_WAVE_5:
541 case REG_WAVE_6:
542 case REG_WAVE_7:
543 case REG_WAVE_8:
544 case REG_WAVE_9:
545 case REG_WAVE_A:
546 case REG_WAVE_B:
547 case REG_WAVE_C:
548 case REG_WAVE_D:
549 case REG_WAVE_E:
550 case REG_WAVE_F:
551 if (gb->audio.playingCh3) {
552 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
553 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
554 } else {
555 return 0xFF;
556 }
557 } else {
558 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
559 }
560 break;
561 case REG_SB:
562 case REG_SC:
563 case REG_IF:
564 case REG_NR10:
565 case REG_NR11:
566 case REG_NR12:
567 case REG_NR14:
568 case REG_NR21:
569 case REG_NR22:
570 case REG_NR24:
571 case REG_NR30:
572 case REG_NR32:
573 case REG_NR34:
574 case REG_NR41:
575 case REG_NR42:
576 case REG_NR43:
577 case REG_NR44:
578 case REG_NR50:
579 case REG_NR51:
580 case REG_NR52:
581 case REG_DIV:
582 case REG_TIMA:
583 case REG_TMA:
584 case REG_TAC:
585 case REG_STAT:
586 case REG_LCDC:
587 case REG_SCY:
588 case REG_SCX:
589 case REG_LY:
590 case REG_LYC:
591 case REG_BGP:
592 case REG_OBP0:
593 case REG_OBP1:
594 case REG_WY:
595 case REG_WX:
596 // Handled transparently by the registers
597 break;
598 default:
599 if (gb->model >= GB_MODEL_CGB) {
600 switch (address) {
601 case REG_KEY1:
602 case REG_VBK:
603 case REG_HDMA1:
604 case REG_HDMA2:
605 case REG_HDMA3:
606 case REG_HDMA4:
607 case REG_HDMA5:
608 case REG_BCPS:
609 case REG_BCPD:
610 case REG_OCPS:
611 case REG_OCPD:
612 case REG_SVBK:
613 // Handled transparently by the registers
614 goto success;
615 case REG_DMA:
616 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
617 return 0;
618 default:
619 break;
620 }
621 }
622 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
623 return 0xFF;
624 }
625 success:
626 return gb->memory.io[address] | _registerMask[address];
627}
628
629void GBTestKeypadIRQ(struct GB* gb) {
630 if (_readKeys(gb)) {
631 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
632 GBUpdateIRQs(gb);
633 }
634}
635
636struct GBSerializedState;
637void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
638 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
639 state->ie = gb->memory.ie;
640}
641
642void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
643 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
644 gb->memory.ie = state->ie;
645
646 if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
647 GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
648 GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
649 GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
650 GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
651 gb->audio.ch1.control.frequency &= 0xFF;
652 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
653 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
654 GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
655 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
656 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
657 gb->audio.ch2.control.frequency &= 0xFF;
658 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
659 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
660 GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
661 GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
662 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
663 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
664 gb->audio.ch3.rate &= 0xFF;
665 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
666 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
667 GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
668 GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
669 GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
670 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
671 GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
672 GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
673 }
674
675 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
676 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
677 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
678 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
679 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
680 if (gb->model == GB_MODEL_SGB) {
681 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
682 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
683 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
684 }
685 gb->video.stat = state->io[REG_STAT];
686}