src/lr35902/isa-lr35902.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-lr35902.h"
7
8#include "lr35902/emitter-lr35902.h"
9#include "lr35902/lr35902.h"
10
11#define DEFINE_INSTRUCTION_LR35902(NAME, BODY) \
12 static void _LR35902Instruction ## NAME (struct LR35902Core* cpu) { \
13 UNUSED(cpu); \
14 BODY; \
15 }
16
17DEFINE_INSTRUCTION_LR35902(NOP,);
18
19#define DEFINE_CONDITIONAL_INSTRUCTION_LR35902(NAME) \
20 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(, true) \
21 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->f.c) \
22 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Z, cpu->f.z) \
23 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NC, !cpu->f.c) \
24 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NZ, !cpu->f.z)
25
26DEFINE_INSTRUCTION_LR35902(JPFinish,
27 if (cpu->condition) {
28 cpu->pc = (cpu->bus << 8) | cpu->index;
29 cpu->memory.setActiveRegion(cpu, cpu->pc);
30 cpu->executionState = LR35902_CORE_STALL;
31 })
32
33DEFINE_INSTRUCTION_LR35902(JPDelay,
34 cpu->executionState = LR35902_CORE_READ_PC;
35 cpu->instruction = _LR35902InstructionJPFinish;
36 cpu->index = cpu->bus;)
37
38#define DEFINE_JP_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
39 DEFINE_INSTRUCTION_LR35902(JP ## CONDITION_NAME, \
40 cpu->executionState = LR35902_CORE_READ_PC; \
41 cpu->instruction = _LR35902InstructionJPDelay; \
42 cpu->condition = CONDITION;)
43
44DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JP);
45
46DEFINE_INSTRUCTION_LR35902(JPHL,
47 cpu->pc = LR35902ReadHL(cpu);
48 cpu->memory.setActiveRegion(cpu, cpu->pc);)
49
50DEFINE_INSTRUCTION_LR35902(JRFinish,
51 if (cpu->condition) {
52 cpu->pc += (int8_t) cpu->bus;
53 cpu->memory.setActiveRegion(cpu, cpu->pc);
54 cpu->executionState = LR35902_CORE_STALL;
55 })
56
57#define DEFINE_JR_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
58 DEFINE_INSTRUCTION_LR35902(JR ## CONDITION_NAME, \
59 cpu->executionState = LR35902_CORE_READ_PC; \
60 cpu->instruction = _LR35902InstructionJRFinish; \
61 cpu->condition = CONDITION;)
62
63DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JR);
64
65DEFINE_INSTRUCTION_LR35902(CALLFinish,
66 if (cpu->condition) {
67 cpu->pc = (cpu->bus << 8) | cpu->index;
68 cpu->memory.setActiveRegion(cpu, cpu->pc);
69 cpu->executionState = LR35902_CORE_STALL;
70 })
71
72DEFINE_INSTRUCTION_LR35902(CALLUpdatePC,
73 cpu->executionState = LR35902_CORE_READ_PC;
74 cpu->index = cpu->bus;
75 cpu->instruction = _LR35902InstructionCALLFinish;)
76
77DEFINE_INSTRUCTION_LR35902(CALLUpdateSPL,
78 cpu->executionState = LR35902_CORE_READ_PC; \
79 cpu->instruction = _LR35902InstructionCALLUpdatePC;)
80
81DEFINE_INSTRUCTION_LR35902(CALLUpdateSPH,
82 cpu->index = cpu->sp + 1;
83 cpu->bus = (cpu->pc + 2) >> 8;
84 cpu->executionState = LR35902_CORE_MEMORY_STORE;
85 cpu->instruction = _LR35902InstructionCALLUpdateSPL;)
86
87#define DEFINE_CALL_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
88 DEFINE_INSTRUCTION_LR35902(CALL ## CONDITION_NAME, \
89 cpu->condition = CONDITION; \
90 if (CONDITION) { \
91 cpu->sp -= 2; /* TODO: Atomic incrementing? */ \
92 cpu->index = cpu->sp; \
93 cpu->bus = cpu->pc + 2; \
94 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
95 cpu->instruction = _LR35902InstructionCALLUpdateSPH; \
96 } else { \
97 cpu->executionState = LR35902_CORE_READ_PC; \
98 cpu->instruction = _LR35902InstructionCALLUpdatePC; \
99 })
100
101DEFINE_CONDITIONAL_INSTRUCTION_LR35902(CALL)
102
103DEFINE_INSTRUCTION_LR35902(RETUpdateSPL,
104 cpu->pc |= cpu->bus << 8;
105 cpu->sp += 2; /* TODO: Atomic incrementing? */
106 cpu->memory.setActiveRegion(cpu, cpu->pc);
107 cpu->executionState = LR35902_CORE_STALL;)
108
109DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
110 if (cpu->condition) {
111 cpu->index = cpu->sp + 1;
112 cpu->pc = cpu->bus;
113 cpu->executionState = LR35902_CORE_MEMORY_LOAD;
114 cpu->instruction = _LR35902InstructionRETUpdateSPL;
115 })
116
117#define DEFINE_RET_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
118 DEFINE_INSTRUCTION_LR35902(RET ## CONDITION_NAME, \
119 cpu->condition = CONDITION; \
120 cpu->index = cpu->sp; \
121 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
122 cpu->instruction = _LR35902InstructionRETUpdateSPH;)
123
124DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
125
126#define DEFINE_AND_INSTRUCTION_LR35902(NAME, OPERAND) \
127 DEFINE_INSTRUCTION_LR35902(AND ## NAME, \
128 cpu->a &= OPERAND; \
129 cpu->f.z = !cpu->a; \
130 cpu->f.n = 0; \
131 cpu->f.c = 0; \
132 cpu->f.h = 1;)
133
134#define DEFINE_XOR_INSTRUCTION_LR35902(NAME, OPERAND) \
135 DEFINE_INSTRUCTION_LR35902(XOR ## NAME, \
136 cpu->a ^= OPERAND; \
137 cpu->f.z = !cpu->a; \
138 cpu->f.n = 0; \
139 cpu->f.c = 0; \
140 cpu->f.h = 0;)
141
142#define DEFINE_OR_INSTRUCTION_LR35902(NAME, OPERAND) \
143 DEFINE_INSTRUCTION_LR35902(OR ## NAME, \
144 cpu->a |= OPERAND; \
145 cpu->f.z = !cpu->a; \
146 cpu->f.n = 0; \
147 cpu->f.c = 0; \
148 cpu->f.h = 0;)
149
150#define DEFINE_CP_INSTRUCTION_LR35902(NAME, OPERAND) \
151 DEFINE_INSTRUCTION_LR35902(CP ## NAME, \
152 int diff = cpu->a - OPERAND; \
153 cpu->f.n = 1; \
154 cpu->f.z = !diff; \
155 cpu->f.c = diff < 0; \
156 /* TODO: Find explanation of H flag */)
157
158#define DEFINE_LDB__INSTRUCTION_LR35902(NAME, OPERAND) \
159 DEFINE_INSTRUCTION_LR35902(LDB_ ## NAME, \
160 cpu->b = OPERAND;)
161
162#define DEFINE_LDC__INSTRUCTION_LR35902(NAME, OPERAND) \
163 DEFINE_INSTRUCTION_LR35902(LDC_ ## NAME, \
164 cpu->c = OPERAND;)
165
166#define DEFINE_LDD__INSTRUCTION_LR35902(NAME, OPERAND) \
167 DEFINE_INSTRUCTION_LR35902(LDD_ ## NAME, \
168 cpu->d = OPERAND;)
169
170#define DEFINE_LDE__INSTRUCTION_LR35902(NAME, OPERAND) \
171 DEFINE_INSTRUCTION_LR35902(LDE_ ## NAME, \
172 cpu->e = OPERAND;)
173
174#define DEFINE_LDH__INSTRUCTION_LR35902(NAME, OPERAND) \
175 DEFINE_INSTRUCTION_LR35902(LDH_ ## NAME, \
176 cpu->h = OPERAND;)
177
178#define DEFINE_LDL__INSTRUCTION_LR35902(NAME, OPERAND) \
179 DEFINE_INSTRUCTION_LR35902(LDL_ ## NAME, \
180 cpu->l = OPERAND;)
181
182#define DEFINE_LDHL__INSTRUCTION_LR35902(NAME, OPERAND) \
183 DEFINE_INSTRUCTION_LR35902(LDHL_ ## NAME, \
184 cpu->bus = OPERAND; \
185 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
186 cpu->instruction = _LR35902InstructionLDHL_Bus;)
187
188#define DEFINE_LDA__INSTRUCTION_LR35902(NAME, OPERAND) \
189 DEFINE_INSTRUCTION_LR35902(LDA_ ## NAME, \
190 cpu->a = OPERAND;)
191
192#define DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME) \
193 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(A, cpu->a); \
194 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(B, cpu->b); \
195 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->c); \
196 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(D, cpu->d); \
197 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(E, cpu->e); \
198 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(H, cpu->h); \
199 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(L, cpu->l);
200
201DEFINE_INSTRUCTION_LR35902(LDHL_Bus, \
202 cpu->index = LR35902ReadHL(cpu); \
203 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
204 cpu->instruction = _LR35902InstructionNOP;)
205
206DEFINE_INSTRUCTION_LR35902(LDHL_, \
207 cpu->executionState = LR35902_CORE_READ_PC; \
208 cpu->instruction = _LR35902InstructionLDHL_Bus;)
209
210#define DEFINE_ALU_INSTRUCTION_LR35902_MEM(NAME, REG) \
211 DEFINE_INSTRUCTION_LR35902(NAME ## REG, \
212 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
213 cpu->index = LR35902Read ## REG (cpu); \
214 cpu->instruction = _LR35902Instruction ## NAME ## Bus;)
215
216#define DEFINE_ALU_INSTRUCTION_LR35902(NAME) \
217 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Bus, cpu->bus); \
218 DEFINE_ALU_INSTRUCTION_LR35902_MEM(NAME, HL) \
219 DEFINE_INSTRUCTION_LR35902(NAME, \
220 cpu->executionState = LR35902_CORE_READ_PC; \
221 cpu->instruction = _LR35902Instruction ## NAME ## Bus;) \
222 DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME)
223
224DEFINE_ALU_INSTRUCTION_LR35902(AND);
225DEFINE_ALU_INSTRUCTION_LR35902(XOR);
226DEFINE_ALU_INSTRUCTION_LR35902(OR);
227DEFINE_ALU_INSTRUCTION_LR35902(CP);
228
229static void _LR35902InstructionLDB_Bus(struct LR35902Core*);
230static void _LR35902InstructionLDC_Bus(struct LR35902Core*);
231static void _LR35902InstructionLDD_Bus(struct LR35902Core*);
232static void _LR35902InstructionLDE_Bus(struct LR35902Core*);
233static void _LR35902InstructionLDH_Bus(struct LR35902Core*);
234static void _LR35902InstructionLDL_Bus(struct LR35902Core*);
235static void _LR35902InstructionLDHL_Bus(struct LR35902Core*);
236static void _LR35902InstructionLDA_Bus(struct LR35902Core*);
237
238#define DEFINE_ADD_INSTRUCTION_LR35902(NAME, OPERAND) \
239 DEFINE_INSTRUCTION_LR35902(ADD ## NAME, \
240 int diff = cpu->a + OPERAND; \
241 cpu->a = diff; \
242 cpu->f.n = 0; \
243 cpu->f.z = !diff; \
244 cpu->f.c = diff >= 0x100; \
245 /* TODO: Find explanation of H flag */)
246
247#define DEFINE_ADC_INSTRUCTION_LR35902(NAME, OPERAND) \
248 DEFINE_INSTRUCTION_LR35902(ADC ## NAME, \
249 int diff = cpu->a + OPERAND + cpu->f.c; \
250 cpu->a = diff; \
251 cpu->f.n = 0; \
252 cpu->f.z = !diff; \
253 cpu->f.c = diff > 0x100; \
254 /* TODO: Find explanation of H flag */)
255
256#define DEFINE_SUB_INSTRUCTION_LR35902(NAME, OPERAND) \
257 DEFINE_INSTRUCTION_LR35902(SUB ## NAME, \
258 int diff = cpu->a - OPERAND; \
259 cpu->a = diff; \
260 cpu->f.n = 1; \
261 cpu->f.z = !diff; \
262 cpu->f.c = diff < 0; \
263 /* TODO: Find explanation of H flag */)
264
265#define DEFINE_SBC_INSTRUCTION_LR35902(NAME, OPERAND) \
266 DEFINE_INSTRUCTION_LR35902(SBC ## NAME, \
267 int diff = cpu->a - OPERAND - cpu->f.c; \
268 cpu->a = diff; \
269 cpu->f.n = 1; \
270 cpu->f.z = !diff; \
271 cpu->f.c = diff < 0; \
272 /* TODO: Find explanation of H flag */)
273
274DEFINE_ALU_INSTRUCTION_LR35902(LDB_);
275DEFINE_ALU_INSTRUCTION_LR35902(LDC_);
276DEFINE_ALU_INSTRUCTION_LR35902(LDD_);
277DEFINE_ALU_INSTRUCTION_LR35902(LDE_);
278DEFINE_ALU_INSTRUCTION_LR35902(LDH_);
279DEFINE_ALU_INSTRUCTION_LR35902(LDL_);
280DEFINE_ALU_INSTRUCTION_LR35902_NOHL(LDHL_);
281DEFINE_ALU_INSTRUCTION_LR35902(LDA_);
282DEFINE_ALU_INSTRUCTION_LR35902_MEM(LDA_, BC);
283DEFINE_ALU_INSTRUCTION_LR35902_MEM(LDA_, DE);
284DEFINE_ALU_INSTRUCTION_LR35902(ADD);
285DEFINE_ALU_INSTRUCTION_LR35902(ADC);
286DEFINE_ALU_INSTRUCTION_LR35902(SUB);
287DEFINE_ALU_INSTRUCTION_LR35902(SBC);
288
289DEFINE_INSTRUCTION_LR35902(LDBCDelay, \
290 cpu->c = cpu->bus; \
291 cpu->executionState = LR35902_CORE_READ_PC; \
292 cpu->instruction = _LR35902InstructionLDB_Bus;)
293
294DEFINE_INSTRUCTION_LR35902(LDBC, \
295 cpu->executionState = LR35902_CORE_READ_PC; \
296 cpu->instruction = _LR35902InstructionLDBCDelay;)
297
298DEFINE_INSTRUCTION_LR35902(LDBC_A, \
299 cpu->index = LR35902ReadBC(cpu); \
300 cpu->bus = cpu->a; \
301 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
302 cpu->instruction = _LR35902InstructionNOP;)
303
304DEFINE_INSTRUCTION_LR35902(LDDEDelay, \
305 cpu->e = cpu->bus; \
306 cpu->executionState = LR35902_CORE_READ_PC; \
307 cpu->instruction = _LR35902InstructionLDD_Bus;)
308
309DEFINE_INSTRUCTION_LR35902(LDDE, \
310 cpu->executionState = LR35902_CORE_READ_PC; \
311 cpu->instruction = _LR35902InstructionLDDEDelay;)
312
313DEFINE_INSTRUCTION_LR35902(LDDE_A, \
314 cpu->index = LR35902ReadDE(cpu); \
315 cpu->bus = cpu->a; \
316 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
317 cpu->instruction = _LR35902InstructionNOP;)
318
319DEFINE_INSTRUCTION_LR35902(LDHLDelay, \
320 cpu->l = cpu->bus; \
321 cpu->executionState = LR35902_CORE_READ_PC; \
322 cpu->instruction = _LR35902InstructionLDH_Bus;)
323
324DEFINE_INSTRUCTION_LR35902(LDHL, \
325 cpu->executionState = LR35902_CORE_READ_PC; \
326 cpu->instruction = _LR35902InstructionLDHLDelay;)
327
328DEFINE_INSTRUCTION_LR35902(LDSPFinish, cpu->sp |= cpu->bus << 8;)
329
330DEFINE_INSTRUCTION_LR35902(LDSPDelay, \
331 cpu->sp = cpu->bus; \
332 cpu->executionState = LR35902_CORE_READ_PC; \
333 cpu->instruction = _LR35902InstructionLDSPFinish;)
334
335DEFINE_INSTRUCTION_LR35902(LDSP, \
336 cpu->executionState = LR35902_CORE_READ_PC; \
337 cpu->instruction = _LR35902InstructionLDSPDelay;)
338
339DEFINE_INSTRUCTION_LR35902(LDIHLA, \
340 cpu->index = LR35902ReadHL(cpu); \
341 LR35902WriteHL(cpu, cpu->index + 1); \
342 cpu->bus = cpu->a; \
343 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
344 cpu->instruction = _LR35902InstructionNOP;)
345
346DEFINE_INSTRUCTION_LR35902(LDDHLA, \
347 cpu->index = LR35902ReadHL(cpu); \
348 LR35902WriteHL(cpu, cpu->index - 1); \
349 cpu->bus = cpu->a; \
350 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
351 cpu->instruction = _LR35902InstructionNOP;)
352
353DEFINE_INSTRUCTION_LR35902(LDA_IHL, \
354 cpu->index = LR35902ReadHL(cpu); \
355 LR35902WriteHL(cpu, cpu->index + 1); \
356 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
357 cpu->instruction = _LR35902InstructionLDA_Bus;)
358
359DEFINE_INSTRUCTION_LR35902(LDA_DHL, \
360 cpu->index = LR35902ReadHL(cpu); \
361 LR35902WriteHL(cpu, cpu->index - 1); \
362 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
363 cpu->instruction = _LR35902InstructionLDA_Bus;)
364
365DEFINE_INSTRUCTION_LR35902(LDIAFinish, \
366 cpu->index |= cpu->bus << 8;
367 cpu->bus = cpu->a; \
368 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
369 cpu->instruction = _LR35902InstructionNOP;)
370
371DEFINE_INSTRUCTION_LR35902(LDIADelay, \
372 cpu->index = cpu->bus;
373 cpu->executionState = LR35902_CORE_READ_PC; \
374 cpu->instruction = _LR35902InstructionLDIAFinish;)
375
376DEFINE_INSTRUCTION_LR35902(LDIA, \
377 cpu->executionState = LR35902_CORE_READ_PC; \
378 cpu->instruction = _LR35902InstructionLDIADelay;)
379
380DEFINE_INSTRUCTION_LR35902(LDAIFinish, \
381 cpu->index |= cpu->bus << 8;
382 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
383 cpu->instruction = _LR35902InstructionLDA_Bus;)
384
385DEFINE_INSTRUCTION_LR35902(LDAIDelay, \
386 cpu->index = cpu->bus;
387 cpu->executionState = LR35902_CORE_READ_PC; \
388 cpu->instruction = _LR35902InstructionLDAIFinish;)
389
390DEFINE_INSTRUCTION_LR35902(LDAI, \
391 cpu->executionState = LR35902_CORE_READ_PC; \
392 cpu->instruction = _LR35902InstructionLDAIDelay;)
393
394DEFINE_INSTRUCTION_LR35902(LDAIOC, \
395 cpu->index = 0xFF00 | cpu->c; \
396 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
397 cpu->instruction = _LR35902InstructionLDA_Bus;)
398
399DEFINE_INSTRUCTION_LR35902(LDIOCA, \
400 cpu->index = 0xFF00 | cpu->c; \
401 cpu->bus = cpu->a; \
402 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
403 cpu->instruction = _LR35902InstructionNOP;)
404
405DEFINE_INSTRUCTION_LR35902(LDAIODelay, \
406 cpu->index = 0xFF00 | cpu->bus; \
407 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
408 cpu->instruction = _LR35902InstructionLDA_Bus;)
409
410DEFINE_INSTRUCTION_LR35902(LDAIO, \
411 cpu->executionState = LR35902_CORE_READ_PC; \
412 cpu->instruction = _LR35902InstructionLDAIODelay;)
413
414DEFINE_INSTRUCTION_LR35902(LDIOADelay, \
415 cpu->index = 0xFF00 | cpu->bus; \
416 cpu->bus = cpu->a; \
417 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
418 cpu->instruction = _LR35902InstructionNOP;)
419
420DEFINE_INSTRUCTION_LR35902(LDIOA, \
421 cpu->executionState = LR35902_CORE_READ_PC; \
422 cpu->instruction = _LR35902InstructionLDIOADelay;)
423
424#define DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(REG) \
425 DEFINE_INSTRUCTION_LR35902(INC ## REG, \
426 uint16_t reg = LR35902Read ## REG (cpu); \
427 LR35902Write ## REG (cpu, reg + 1); \
428 cpu->executionState = LR35902_CORE_STALL;) \
429 DEFINE_INSTRUCTION_LR35902(DEC ## REG, \
430 uint16_t reg = LR35902Read ## REG (cpu); \
431 LR35902Write ## REG (cpu, reg - 1); \
432 cpu->executionState = LR35902_CORE_STALL;)
433
434DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(BC);
435DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(DE);
436DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(HL);
437
438#define DEFINE_ADD_HL_INSTRUCTION_LR35902(REG, L, H) \
439 DEFINE_INSTRUCTION_LR35902(ADDHL_ ## REG ## Finish, \
440 int diff = H + cpu->h + cpu->f.c; \
441 cpu->h = diff; \
442 cpu->f.c = diff >= 0x100; \
443 cpu->f.n = 0; \
444 /* TODO: Find explanation of H flag */) \
445 DEFINE_INSTRUCTION_LR35902(ADDHL_ ## REG, \
446 int diff = L + cpu->l; \
447 cpu->l = diff; \
448 cpu->f.c = diff >= 0x100; \
449 cpu->executionState = LR35902_CORE_STALL; \
450 cpu->instruction = _LR35902InstructionADDHL_ ## REG ## Finish;)
451
452DEFINE_ADD_HL_INSTRUCTION_LR35902(BC, cpu->c, cpu->b);
453DEFINE_ADD_HL_INSTRUCTION_LR35902(DE, cpu->e, cpu->d);
454DEFINE_ADD_HL_INSTRUCTION_LR35902(HL, cpu->l, cpu->h);
455DEFINE_ADD_HL_INSTRUCTION_LR35902(SP, (cpu->sp & 0xFF), (cpu->sp >> 8));
456
457
458#define DEFINE_INC_INSTRUCTION_LR35902(NAME, OPERAND) \
459 DEFINE_INSTRUCTION_LR35902(INC ## NAME, \
460 int diff = OPERAND + 1; \
461 OPERAND = diff; \
462 cpu->f.n = 0; \
463 cpu->f.z = !diff; \
464 /* TODO: Find explanation of H flag */)
465
466#define DEFINE_DEC_INSTRUCTION_LR35902(NAME, OPERAND) \
467 DEFINE_INSTRUCTION_LR35902(DEC ## NAME, \
468 int diff = OPERAND - 1; \
469 OPERAND = diff; \
470 cpu->f.n = 1; \
471 cpu->f.z = !diff; \
472 /* TODO: Find explanation of H flag */)
473
474DEFINE_ALU_INSTRUCTION_LR35902_NOHL(INC);
475DEFINE_ALU_INSTRUCTION_LR35902_NOHL(DEC);
476
477DEFINE_INSTRUCTION_LR35902(INC_HLDelay,
478 int diff = cpu->bus + 1;
479 cpu->bus = diff;
480 cpu->f.n = 0;
481 cpu->f.z = !diff;
482 /* TODO: Find explanation of H flag */
483 cpu->instruction = _LR35902InstructionNOP;
484 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
485
486DEFINE_INSTRUCTION_LR35902(INC_HL,
487 cpu->index = LR35902ReadHL(cpu);
488 cpu->instruction = _LR35902InstructionINC_HLDelay;
489 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
490
491DEFINE_INSTRUCTION_LR35902(DEC_HLDelay,
492 int diff = cpu->bus - 1;
493 cpu->bus = diff;
494 cpu->f.n = 1;
495 cpu->f.z = !diff;
496 /* TODO: Find explanation of H flag */
497 cpu->instruction = _LR35902InstructionNOP;
498 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
499
500DEFINE_INSTRUCTION_LR35902(DEC_HL,
501 cpu->index = LR35902ReadHL(cpu);
502 cpu->instruction = _LR35902InstructionDEC_HLDelay;
503 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
504
505DEFINE_INSTRUCTION_LR35902(INCSP,
506 ++cpu->sp;
507 cpu->executionState = LR35902_CORE_STALL;)
508
509DEFINE_INSTRUCTION_LR35902(DECSP,
510 --cpu->sp;
511 cpu->executionState = LR35902_CORE_STALL;)
512
513
514#define DEFINE_POPPUSH_INSTRUCTION_LR35902(REG, HH, H, L) \
515 DEFINE_INSTRUCTION_LR35902(POP ## REG ## Delay, \
516 cpu-> L = cpu->bus; \
517 cpu->index = cpu->sp; \
518 ++cpu->sp; \
519 cpu->instruction = _LR35902InstructionLD ## HH ## _Bus; \
520 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
521 DEFINE_INSTRUCTION_LR35902(POP ## REG, \
522 cpu->index = cpu->sp; \
523 ++cpu->sp; \
524 cpu->instruction = _LR35902InstructionPOP ## REG ## Delay; \
525 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
526 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Finish, \
527 cpu->executionState = LR35902_CORE_STALL;) \
528 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Delay, \
529 --cpu->sp; \
530 cpu->index = cpu->sp; \
531 cpu->bus = cpu-> L; \
532 cpu->instruction = _LR35902InstructionPUSH ## REG ## Finish; \
533 cpu->executionState = LR35902_CORE_MEMORY_STORE;) \
534 DEFINE_INSTRUCTION_LR35902(PUSH ## REG, \
535 --cpu->sp; \
536 cpu->index = cpu->sp; \
537 cpu->bus = cpu-> H; \
538 cpu->instruction = _LR35902InstructionPUSH ## REG ## Delay; \
539 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
540
541DEFINE_POPPUSH_INSTRUCTION_LR35902(BC, B, b, c);
542DEFINE_POPPUSH_INSTRUCTION_LR35902(DE, D, d, e);
543DEFINE_POPPUSH_INSTRUCTION_LR35902(HL, H, h, l);
544DEFINE_POPPUSH_INSTRUCTION_LR35902(AF, A, a, f.packed);
545
546DEFINE_INSTRUCTION_LR35902(DI, cpu->irqh.setInterrupts(cpu, false));
547DEFINE_INSTRUCTION_LR35902(EI, cpu->irqh.setInterrupts(cpu, true));
548
549DEFINE_INSTRUCTION_LR35902(STUB, cpu->irqh.hitStub(cpu));
550
551static const LR35902Instruction _lr35902CBInstructionTable[0x100] = {
552 DECLARE_LR35902_CB_EMITTER_BLOCK(_LR35902Instruction)
553};
554
555DEFINE_INSTRUCTION_LR35902(CBDelegate, _lr35902CBInstructionTable[cpu->bus](cpu))
556
557DEFINE_INSTRUCTION_LR35902(CB, \
558 cpu->executionState = LR35902_CORE_READ_PC; \
559 cpu->instruction = _LR35902InstructionCBDelegate;)
560
561const LR35902Instruction _lr35902InstructionTable[0x100] = {
562 DECLARE_LR35902_EMITTER_BLOCK(_LR35902Instruction)
563};