src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define THUMB_SUBTRACTION(D, M, N) \
42 int n = N; \
43 int m = M; \
44 D = M - N; \
45 THUMB_SUBTRACTION_S(m, n, D)
46
47#define THUMB_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles16)
48
49#define THUMB_STORE_POST_BODY \
50 currentCycles -= THUMB_PREFETCH_CYCLES; \
51 currentCycles += 1 + cpu->memory->activeNonseqCycles16;
52
53#define APPLY(F, ...) F(__VA_ARGS__)
54
55#define COUNT_1(EMITTER, PREFIX, ...) \
56 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
57 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
58
59#define COUNT_2(EMITTER, PREFIX, ...) \
60 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
61 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
62 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
63
64#define COUNT_3(EMITTER, PREFIX, ...) \
65 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
66 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
67 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
68 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
69 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
70
71#define COUNT_4(EMITTER, PREFIX, ...) \
72 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
73 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
74 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
75 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
76 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
77 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
78 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
79 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
80 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
81
82#define COUNT_5(EMITTER, PREFIX, ...) \
83 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
84 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
85 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
86 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
87 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
88 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
89 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
90 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
91 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
92 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
93 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
94 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
95 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
96 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
97 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
98 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
99 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
100
101#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
102 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
103 int currentCycles = THUMB_PREFETCH_CYCLES; \
104 BODY; \
105 cpu->cycles += currentCycles; \
106 }
107
108#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
109 DEFINE_INSTRUCTION_THUMB(NAME, \
110 int immediate = IMMEDIATE; \
111 int rd = opcode & 0x0007; \
112 int rm = (opcode >> 3) & 0x0007; \
113 BODY;)
114
115#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
116 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
117
118DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
119 if (!immediate) {
120 cpu->gprs[rd] = cpu->gprs[rm];
121 } else {
122 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
123 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
124 }
125 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
126
127DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
128 if (!immediate) {
129 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
130 cpu->gprs[rd] = 0;
131 } else {
132 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
133 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
134 }
135 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
136
137DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
138 if (!immediate) {
139 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
140 if (cpu->cpsr.c) {
141 cpu->gprs[rd] = 0xFFFFFFFF;
142 } else {
143 cpu->gprs[rd] = 0;
144 }
145 } else {
146 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
147 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
148 }
149 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
150
151DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4, ¤tCycles))
152DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate, ¤tCycles))
153DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2, ¤tCycles))
154DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
155DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
156DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
157
158#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
159 DEFINE_INSTRUCTION_THUMB(NAME, \
160 int rm = RM; \
161 int rd = opcode & 0x0007; \
162 int rn = (opcode >> 3) & 0x0007; \
163 BODY;)
164
165#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
166 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
167
168DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
169DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
170
171#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
172 DEFINE_INSTRUCTION_THUMB(NAME, \
173 int immediate = IMMEDIATE; \
174 int rd = opcode & 0x0007; \
175 int rn = (opcode >> 3) & 0x0007; \
176 BODY;)
177
178#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
179 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
180
181DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
182DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
183
184#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
185 DEFINE_INSTRUCTION_THUMB(NAME, \
186 int rd = RD; \
187 int immediate = opcode & 0x00FF; \
188 BODY;)
189
190#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
191 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
192
193DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
194DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
195DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
196DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
197
198#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
199 DEFINE_INSTRUCTION_THUMB(NAME, \
200 int rd = opcode & 0x0007; \
201 int rn = (opcode >> 3) & 0x0007; \
202 BODY;)
203
204DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
207 int rs = cpu->gprs[rn] & 0xFF;
208 if (rs) {
209 if (rs < 32) {
210 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
211 cpu->gprs[rd] <<= rs;
212 } else {
213 if (rs > 32) {
214 cpu->cpsr.c = 0;
215 } else {
216 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
217 }
218 cpu->gprs[rd] = 0;
219 }
220 }
221 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
222
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
224 int rs = cpu->gprs[rn] & 0xFF;
225 if (rs) {
226 if (rs < 32) {
227 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
228 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
229 } else {
230 if (rs > 32) {
231 cpu->cpsr.c = 0;
232 } else {
233 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
234 }
235 cpu->gprs[rd] = 0;
236 }
237 }
238 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
239
240DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
241 int rs = cpu->gprs[rn] & 0xFF;
242 if (rs) {
243 if (rs < 32) {
244 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
245 cpu->gprs[rd] >>= rs;
246 } else {
247 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
248 if (cpu->cpsr.c) {
249 cpu->gprs[rd] = 0xFFFFFFFF;
250 } else {
251 cpu->gprs[rd] = 0;
252 }
253 }
254 }
255 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
256
257DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
258 int n = cpu->gprs[rn] + cpu->cpsr.c;
259 int d = cpu->gprs[rd];
260 cpu->gprs[rd] = d + n;
261 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
262
263DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
264 int n = cpu->gprs[rn] + !cpu->cpsr.c;
265 int d = cpu->gprs[rd];
266 cpu->gprs[rd] = d - n;
267 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
268DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
269 int rs = cpu->gprs[rn] & 0xFF;
270 if (rs) {
271 int r4 = rs & 0x1F;
272 if (r4 > 0) {
273 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
274 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
275 } else {
276 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
277 }
278 }
279 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
280DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
281DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
282DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
283DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
284DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
285DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
286DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
287DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
288
289#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
290 DEFINE_INSTRUCTION_THUMB(NAME, \
291 int rd = (opcode & 0x0007) | H1; \
292 int rm = ((opcode >> 3) & 0x0007) | H2; \
293 BODY;)
294
295#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
296 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
297 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
298 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
299 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
300
301DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
302 cpu->gprs[rd] += cpu->gprs[rm];
303 if (rd == ARM_PC) {
304 THUMB_WRITE_PC;
305 })
306
307DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
308DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
309 cpu->gprs[rd] = cpu->gprs[rm];
310 if (rd == ARM_PC) {
311 THUMB_WRITE_PC;
312 })
313
314#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
315 DEFINE_INSTRUCTION_THUMB(NAME, \
316 int rd = RD; \
317 int immediate = (opcode & 0x00FF) << 2; \
318 BODY;)
319
320#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
321 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
322
323DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles))
324DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate, ¤tCycles))
325DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
326
327DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
328DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
329
330#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
331 DEFINE_INSTRUCTION_THUMB(NAME, \
332 int rm = RM; \
333 int rd = opcode & 0x0007; \
334 int rn = (opcode >> 3) & 0x0007; \
335 BODY;)
336
337#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
338 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
339
340DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
341DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
342DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
343DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
344DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
345DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
346DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
347DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
348
349#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
350 DEFINE_INSTRUCTION_THUMB(NAME, \
351 int rn = RN; \
352 UNUSED(rn); \
353 int rs = opcode & 0xFF; \
354 int32_t address = ADDRESS; \
355 int m; \
356 int i; \
357 int total = 0; \
358 PRE_BODY; \
359 for LOOP { \
360 if (rs & m) { \
361 BODY; \
362 address OP 4; \
363 ++total; \
364 } \
365 } \
366 POST_BODY; \
367 currentCycles += cpu->memory->waitMultiple(cpu->memory, address, total); \
368 WRITEBACK;)
369
370#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
371 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
372
373DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
374 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
375 if (!((1 << rn) & rs)) {
376 cpu->gprs[rn] = address;
377 })
378
379DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
380 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
381 cpu->gprs[rn] = address)
382
383#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
384 DEFINE_INSTRUCTION_THUMB(B ## COND, \
385 if (ARM_COND_ ## COND) { \
386 int8_t immediate = opcode; \
387 cpu->gprs[ARM_PC] += immediate << 1; \
388 THUMB_WRITE_PC; \
389 })
390
391DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
392DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
393DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
394DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
395DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
396DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
397DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
398DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
399DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
400DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
401DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
402DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
403DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
404DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
405
406DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
407DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
408
409DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
410 opcode & 0x00FF,
411 cpu->gprs[ARM_SP],
412 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
413 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
414 +=,
415 , ,
416 cpu->gprs[ARM_SP] = address)
417
418DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
419 opcode & 0x00FF,
420 cpu->gprs[ARM_SP],
421 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
422 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
423 +=,
424 ,
425 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address, 0) & 0xFFFFFFFE;
426 address += 4;,
427 cpu->gprs[ARM_SP] = address;
428 THUMB_WRITE_PC;)
429
430DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
431 opcode & 0x00FF,
432 cpu->gprs[ARM_SP] - 4,
433 (m = 0x80, i = 7; m; m >>= 1, --i),
434 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
435 -=,
436 , ,
437 cpu->gprs[ARM_SP] = address + 4)
438
439DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
440 opcode & 0x00FF,
441 cpu->gprs[ARM_SP] - 4,
442 (m = 0x80, i = 7; m; m >>= 1, --i),
443 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
444 -=,
445 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR], 0);
446 address -= 4;,
447 ,
448 cpu->gprs[ARM_SP] = address + 4)
449
450DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
451DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
452DEFINE_INSTRUCTION_THUMB(B,
453 int16_t immediate = (opcode & 0x07FF) << 5;
454 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
455 THUMB_WRITE_PC;)
456
457DEFINE_INSTRUCTION_THUMB(BL1,
458 int16_t immediate = (opcode & 0x07FF) << 5;
459 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
460
461DEFINE_INSTRUCTION_THUMB(BL2,
462 uint16_t immediate = (opcode & 0x07FF) << 1;
463 uint32_t pc = cpu->gprs[ARM_PC];
464 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
465 cpu->gprs[ARM_LR] = pc - 1;
466 THUMB_WRITE_PC;)
467
468DEFINE_INSTRUCTION_THUMB(BX,
469 int rm = (opcode >> 3) & 0xF;
470 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
471 int misalign = 0;
472 if (rm == ARM_PC) {
473 misalign = cpu->gprs[rm] & 0x00000002;
474 }
475 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
476 if (cpu->executionMode == MODE_THUMB) {
477 THUMB_WRITE_PC;
478 } else {
479 ARM_WRITE_PC;
480 })
481
482DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
483
484#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
485 EMITTER ## NAME
486
487#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
488 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
489 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
490 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
491 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
492
493#define DUMMY(X, ...) X,
494#define DUMMY_4(...) \
495 DUMMY(__VA_ARGS__) \
496 DUMMY(__VA_ARGS__) \
497 DUMMY(__VA_ARGS__) \
498 DUMMY(__VA_ARGS__)
499
500#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
501 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
502 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
503 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
504 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
505 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
506 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
507 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
508 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
509 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
510 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
511 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
512 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
513 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
514 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
515 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
516 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
517 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
518 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
519 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
520 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
521 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
522 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
523 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
524 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
525 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
526 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
527 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
528 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
529 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
530 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
531 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
532 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
533 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
534 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
535 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
536 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
537 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
538 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
539 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
540 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
541 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
542 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
543 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
544 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
545 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
546 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
547 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
548 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
549 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
550 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
551 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
552 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
553 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
554 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
555 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
556 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
557 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
558 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
559 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
560 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
561 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
562 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
563 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
564 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
565 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
566 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
567 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
568 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
569 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
570 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
571 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
572 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
573 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
574 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
575 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
576 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
577 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
578 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
579 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
580 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
581 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
582 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
583 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
584 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
585 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
586 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
587 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
588 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
589 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
590 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
591 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
592
593static const ThumbInstruction _thumbTable[0x400] = {
594 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
595};