src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12#define ARM_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles32)
13
14// Addressing mode 1
15static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
16 int rm = opcode & 0x0000000F;
17 int immediate = (opcode & 0x00000F80) >> 7;
18 if (!immediate) {
19 cpu->shifterOperand = cpu->gprs[rm];
20 cpu->shifterCarryOut = cpu->cpsr.c;
21 } else {
22 cpu->shifterOperand = cpu->gprs[rm] << immediate;
23 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
24 }
25}
26
27static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
28 int rm = opcode & 0x0000000F;
29 int rs = (opcode >> 8) & 0x0000000F;
30 ++cpu->cycles;
31 int shift = cpu->gprs[rs];
32 if (rs == ARM_PC) {
33 shift += 4;
34 }
35 shift &= 0xFF;
36 int32_t shiftVal = cpu->gprs[rm];
37 if (rm == ARM_PC) {
38 shiftVal += 4;
39 }
40 if (!shift) {
41 cpu->shifterOperand = shiftVal;
42 cpu->shifterCarryOut = cpu->cpsr.c;
43 } else if (shift < 32) {
44 cpu->shifterOperand = shiftVal << shift;
45 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
46 } else if (shift == 32) {
47 cpu->shifterOperand = 0;
48 cpu->shifterCarryOut = shiftVal & 1;
49 } else {
50 cpu->shifterOperand = 0;
51 cpu->shifterCarryOut = 0;
52 }
53}
54
55static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
56 int rm = opcode & 0x0000000F;
57 int immediate = (opcode & 0x00000F80) >> 7;
58 if (immediate) {
59 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
60 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
61 } else {
62 cpu->shifterOperand = 0;
63 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
64 }
65}
66
67static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
68 int rm = opcode & 0x0000000F;
69 int rs = (opcode >> 8) & 0x0000000F;
70 ++cpu->cycles;
71 int shift = cpu->gprs[rs];
72 if (rs == ARM_PC) {
73 shift += 4;
74 }
75 shift &= 0xFF;
76 uint32_t shiftVal = cpu->gprs[rm];
77 if (rm == ARM_PC) {
78 shiftVal += 4;
79 }
80 if (!shift) {
81 cpu->shifterOperand = shiftVal;
82 cpu->shifterCarryOut = cpu->cpsr.c;
83 } else if (shift < 32) {
84 cpu->shifterOperand = shiftVal >> shift;
85 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
86 } else if (shift == 32) {
87 cpu->shifterOperand = 0;
88 cpu->shifterCarryOut = shiftVal >> 31;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = 0;
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 int immediate = (opcode & 0x00000F80) >> 7;
98 if (immediate) {
99 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
100 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
101 } else {
102 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
103 cpu->shifterOperand = cpu->shifterCarryOut;
104 }
105}
106
107static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
108 int rm = opcode & 0x0000000F;
109 int rs = (opcode >> 8) & 0x0000000F;
110 ++cpu->cycles;
111 int shift = cpu->gprs[rs];
112 if (rs == ARM_PC) {
113 shift += 4;
114 }
115 shift &= 0xFF;
116 int shiftVal = cpu->gprs[rm];
117 if (rm == ARM_PC) {
118 shiftVal += 4;
119 }
120 if (!shift) {
121 cpu->shifterOperand = shiftVal;
122 cpu->shifterCarryOut = cpu->cpsr.c;
123 } else if (shift < 32) {
124 cpu->shifterOperand = shiftVal >> shift;
125 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
126 } else if (cpu->gprs[rm] >> 31) {
127 cpu->shifterOperand = 0xFFFFFFFF;
128 cpu->shifterCarryOut = 1;
129 } else {
130 cpu->shifterOperand = 0;
131 cpu->shifterCarryOut = 0;
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 int immediate = (opcode & 0x00000F80) >> 7;
138 if (immediate) {
139 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
140 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
141 } else {
142 // RRX
143 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
144 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
145 }
146}
147
148static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
149 int rm = opcode & 0x0000000F;
150 int rs = (opcode >> 8) & 0x0000000F;
151 ++cpu->cycles;
152 int shift = cpu->gprs[rs];
153 if (rs == ARM_PC) {
154 shift += 4;
155 }
156 shift &= 0xFF;
157 int shiftVal = cpu->gprs[rm];
158 if (rm == ARM_PC) {
159 shiftVal += 4;
160 }
161 int rotate = shift & 0x1F;
162 if (!shift) {
163 cpu->shifterOperand = shiftVal;
164 cpu->shifterCarryOut = cpu->cpsr.c;
165 } else if (rotate) {
166 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
167 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
168 } else {
169 cpu->shifterOperand = shiftVal;
170 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
171 }
172}
173
174static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
175 int rotate = (opcode & 0x00000F00) >> 7;
176 int immediate = opcode & 0x000000FF;
177 if (!rotate) {
178 cpu->shifterOperand = immediate;
179 cpu->shifterCarryOut = cpu->cpsr.c;
180 } else {
181 cpu->shifterOperand = ARM_ROR(immediate, rotate);
182 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
183 }
184}
185
186static const ARMInstruction _armTable[0x1000];
187
188static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
189 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
190 *opcodeOut = opcode;
191 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
192}
193
194void ARMStep(struct ARMCore* cpu) {
195 // TODO
196 uint32_t opcode;
197 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
198 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
199
200 int condition = opcode >> 28;
201 if (condition == 0xE) {
202 instruction(cpu, opcode);
203 return;
204 } else {
205 switch (condition) {
206 case 0x0:
207 if (!ARM_COND_EQ) {
208 cpu->cycles += ARM_PREFETCH_CYCLES;
209 return;
210 }
211 break;
212 case 0x1:
213 if (!ARM_COND_NE) {
214 cpu->cycles += ARM_PREFETCH_CYCLES;
215 return;
216 }
217 break;
218 case 0x2:
219 if (!ARM_COND_CS) {
220 cpu->cycles += ARM_PREFETCH_CYCLES;
221 return;
222 }
223 break;
224 case 0x3:
225 if (!ARM_COND_CC) {
226 cpu->cycles += ARM_PREFETCH_CYCLES;
227 return;
228 }
229 break;
230 case 0x4:
231 if (!ARM_COND_MI) {
232 cpu->cycles += ARM_PREFETCH_CYCLES;
233 return;
234 }
235 break;
236 case 0x5:
237 if (!ARM_COND_PL) {
238 cpu->cycles += ARM_PREFETCH_CYCLES;
239 return;
240 }
241 break;
242 case 0x6:
243 if (!ARM_COND_VS) {
244 cpu->cycles += ARM_PREFETCH_CYCLES;
245 return;
246 }
247 break;
248 case 0x7:
249 if (!ARM_COND_VC) {
250 cpu->cycles += ARM_PREFETCH_CYCLES;
251 return;
252 }
253 break;
254 case 0x8:
255 if (!ARM_COND_HI) {
256 cpu->cycles += ARM_PREFETCH_CYCLES;
257 return;
258 }
259 break;
260 case 0x9:
261 if (!ARM_COND_LS) {
262 cpu->cycles += ARM_PREFETCH_CYCLES;
263 return;
264 }
265 break;
266 case 0xA:
267 if (!ARM_COND_GE) {
268 cpu->cycles += ARM_PREFETCH_CYCLES;
269 return;
270 }
271 break;
272 case 0xB:
273 if (!ARM_COND_LT) {
274 cpu->cycles += ARM_PREFETCH_CYCLES;
275 return;
276 }
277 break;
278 case 0xC:
279 if (!ARM_COND_GT) {
280 cpu->cycles += ARM_PREFETCH_CYCLES;
281 return;
282 }
283 break;
284 case 0xD:
285 if (!ARM_COND_LE) {
286 cpu->cycles += ARM_PREFETCH_CYCLES;
287 return;
288 }
289 break;
290 default:
291 break;
292 }
293 }
294 instruction(cpu, opcode);
295}
296
297// Instruction definitions
298// Beware pre-processor antics
299
300#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
301
302#define ARM_ADDITION_S(M, N, D) \
303 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
304 cpu->cpsr = cpu->spsr; \
305 _ARMReadCPSR(cpu); \
306 } else { \
307 cpu->cpsr.n = ARM_SIGN(D); \
308 cpu->cpsr.z = !(D); \
309 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
310 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
311 }
312
313#define ARM_SUBTRACTION_S(M, N, D) \
314 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
315 cpu->cpsr = cpu->spsr; \
316 _ARMReadCPSR(cpu); \
317 } else { \
318 cpu->cpsr.n = ARM_SIGN(D); \
319 cpu->cpsr.z = !(D); \
320 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
321 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
322 }
323
324#define ARM_NEUTRAL_S(M, N, D) \
325 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
326 cpu->cpsr = cpu->spsr; \
327 _ARMReadCPSR(cpu); \
328 } else { \
329 cpu->cpsr.n = ARM_SIGN(D); \
330 cpu->cpsr.z = !(D); \
331 cpu->cpsr.c = cpu->shifterCarryOut; \
332 }
333
334#define ARM_NEUTRAL_HI_S(DLO, DHI) \
335 cpu->cpsr.n = ARM_SIGN(DHI); \
336 cpu->cpsr.z = !((DHI) | (DLO));
337
338#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
339#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
340#define ADDR_MODE_2_ADDRESS (address)
341#define ADDR_MODE_2_RN (cpu->gprs[rn])
342#define ADDR_MODE_2_RM (cpu->gprs[rm])
343#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
344#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
345#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
346#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
347#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
348#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
349#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
350
351#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
352#define ADDR_MODE_3_RN ADDR_MODE_2_RN
353#define ADDR_MODE_3_RM ADDR_MODE_2_RM
354#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
355#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
356#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
357
358#define ARM_LOAD_POST_BODY \
359 if (rd == ARM_PC) { \
360 ARM_WRITE_PC; \
361 }
362
363#define ARM_STORE_POST_BODY \
364 currentCycles -= ARM_PREFETCH_CYCLES; \
365 currentCycles += 1 + cpu->memory->activeNonseqCycles32;
366
367#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
368 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
369 int currentCycles = ARM_PREFETCH_CYCLES; \
370 BODY; \
371 cpu->cycles += currentCycles; \
372 }
373
374#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
375 DEFINE_INSTRUCTION_ARM(NAME, \
376 int rd = (opcode >> 12) & 0xF; \
377 int rn = (opcode >> 16) & 0xF; \
378 UNUSED(rn); \
379 SHIFTER(cpu, opcode); \
380 BODY; \
381 S_BODY; \
382 if (rd == ARM_PC) { \
383 if (cpu->executionMode == MODE_ARM) { \
384 ARM_WRITE_PC; \
385 } else { \
386 THUMB_WRITE_PC; \
387 } \
388 })
389
390#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
391 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
392 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
393 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
394 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
395 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
396 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
397 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
398 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
399 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
400 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
401 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
402 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
403 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
404 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
405 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
406 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
407 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
408 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
409
410#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
411 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
412 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
413 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
414 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
415 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
416 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
417 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
418 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
419 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
420
421#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
422 DEFINE_INSTRUCTION_ARM(NAME, \
423 int rd = (opcode >> 12) & 0xF; \
424 int rdHi = (opcode >> 16) & 0xF; \
425 int rs = (opcode >> 8) & 0xF; \
426 int rm = opcode & 0xF; \
427 UNUSED(rdHi); \
428 ARM_WAIT_MUL(cpu->gprs[rs]); \
429 BODY; \
430 S_BODY; \
431 if (rd == ARM_PC) { \
432 ARM_WRITE_PC; \
433 })
434
435#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
436 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
437 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
438
439#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
440 DEFINE_INSTRUCTION_ARM(NAME, \
441 uint32_t address; \
442 int rn = (opcode >> 16) & 0xF; \
443 int rd = (opcode >> 12) & 0xF; \
444 int rm = opcode & 0xF; \
445 UNUSED(rm); \
446 address = ADDRESS; \
447 WRITEBACK; \
448 BODY;)
449
450#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
457
458#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
459 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
460 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
469
470#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
473 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
474 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
479 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
480 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
481 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
482 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
483
484#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
485 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
486 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
487
488#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
489 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
490 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
491 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
492 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
493 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
494 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
495
496#define ARM_MS_PRE \
497 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
498 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
499
500#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
501
502#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
503#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
504#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
505#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
506#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
507#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
508#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
509#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
510
511#define ARM_M_INCREMENT(BODY) \
512 for (m = rs, i = 0; m; m >>= 1, ++i) { \
513 if (m & 1) { \
514 BODY; \
515 addr += 4; \
516 total += 1; \
517 } \
518 }
519
520#define ARM_M_DECREMENT(BODY) \
521 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
522 if (rs & m) { \
523 BODY; \
524 addr -= 4; \
525 total += 1; \
526 } \
527 }
528
529#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
530 DEFINE_INSTRUCTION_ARM(NAME, \
531 int rn = (opcode >> 16) & 0xF; \
532 int rs = opcode & 0x0000FFFF; \
533 int writeback = 1; \
534 int m; \
535 int i; \
536 int total = 0; \
537 ADDRESS; \
538 S_PRE; \
539 LOOP(BODY); \
540 S_POST; \
541 currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
542 POST_BODY; \
543 if (writeback) { \
544 WRITEBACK; \
545 })
546
547
548#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
549 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
550 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
551 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
552 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
553 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
554 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
555 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
556 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
557 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
558 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
559 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
560 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
561 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
562 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
563 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
564 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
565
566// Begin ALU definitions
567
568DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
569 int32_t n = cpu->gprs[rn];
570 cpu->gprs[rd] = n + cpu->shifterOperand;)
571
572DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
573 int32_t n = cpu->gprs[rn];
574 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
575
576DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
577 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
578
579DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
580 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
581
582DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
583 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
584
585DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
586 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
587
588DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
589 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
590
591DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
592 cpu->gprs[rd] = cpu->shifterOperand;)
593
594DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
595 cpu->gprs[rd] = ~cpu->shifterOperand;)
596
597DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
598 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
599
600DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
601 int32_t n = cpu->gprs[rn];
602 cpu->gprs[rd] = cpu->shifterOperand - n;)
603
604DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
605 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
606 cpu->gprs[rd] = cpu->shifterOperand - n;)
607
608DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
609 int32_t n = cpu->gprs[rn];
610 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
611 cpu->gprs[rd] = n - shifterOperand;)
612
613DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
614 int32_t n = cpu->gprs[rn];
615 cpu->gprs[rd] = n - cpu->shifterOperand;)
616
617DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
618 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
619
620DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
621 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
622
623// End ALU definitions
624
625// Begin multiply definitions
626
627DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
628DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
629
630DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
631 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
632 int32_t dm = cpu->gprs[rd];
633 int32_t dn = d;
634 cpu->gprs[rd] = dm + dn;
635 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
636 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
637
638DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
639 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
640 cpu->gprs[rd] = d;
641 cpu->gprs[rdHi] = d >> 32;,
642 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
643
644DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
645 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
646 int32_t dm = cpu->gprs[rd];
647 int32_t dn = d;
648 cpu->gprs[rd] = dm + dn;
649 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
650 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
651
652DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
653 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
654 cpu->gprs[rd] = d;
655 cpu->gprs[rdHi] = d >> 32;,
656 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
657
658// End multiply definitions
659
660// Begin load/store definitions
661
662DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
663DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
664DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
665DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
666DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
667DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
668DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
669DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
670
671DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
672 enum PrivilegeMode priv = cpu->privilegeMode;
673 ARMSetPrivilegeMode(cpu, MODE_USER);
674 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles);
675 ARMSetPrivilegeMode(cpu, priv);
676 ARM_LOAD_POST_BODY;)
677
678DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
679 enum PrivilegeMode priv = cpu->privilegeMode;
680 ARMSetPrivilegeMode(cpu, MODE_USER);
681 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles);
682 ARMSetPrivilegeMode(cpu, priv);
683 ARM_LOAD_POST_BODY;)
684
685DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
686 enum PrivilegeMode priv = cpu->privilegeMode;
687 ARMSetPrivilegeMode(cpu, MODE_USER);
688 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
689 ARMSetPrivilegeMode(cpu, priv);
690 ARM_STORE_POST_BODY;)
691
692DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
693 enum PrivilegeMode priv = cpu->privilegeMode;
694 ARMSetPrivilegeMode(cpu, MODE_USER);
695 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
696 ARMSetPrivilegeMode(cpu, priv);
697 ARM_STORE_POST_BODY;)
698
699DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
700 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr & 0xFFFFFFFC, 0);,
701 ++currentCycles;
702 if (rs & 0x8000) {
703 ARM_WRITE_PC;
704 }
705 int rnx = 1 << rn;
706 if (rnx & rs && ((rnx - 1) & rs)) {
707 writeback = 0;
708 })
709
710DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
711 cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
712 currentCycles -= ARM_PREFETCH_CYCLES)
713
714DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
715DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
716
717// End load/store definitions
718
719// Begin branch definitions
720
721DEFINE_INSTRUCTION_ARM(B,
722 int32_t offset = opcode << 8;
723 offset >>= 6;
724 cpu->gprs[ARM_PC] += offset;
725 ARM_WRITE_PC;)
726
727DEFINE_INSTRUCTION_ARM(BL,
728 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
729 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
730 cpu->gprs[ARM_PC] += immediate >> 6;
731 ARM_WRITE_PC;)
732
733DEFINE_INSTRUCTION_ARM(BX,
734 int rm = opcode & 0x0000000F;
735 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
736 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
737 if (cpu->executionMode == MODE_THUMB) {
738 THUMB_WRITE_PC;
739 } else {
740 ARM_WRITE_PC;
741 })
742
743// End branch definitions
744
745// Begin miscellaneous definitions
746
747DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
748DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
749
750DEFINE_INSTRUCTION_ARM(MSR,
751 int c = opcode & 0x00010000;
752 int f = opcode & 0x00080000;
753 int32_t operand = cpu->gprs[opcode & 0x0000000F];
754 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
755 if (mask & PSR_USER_MASK) {
756 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
757 }
758 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
759 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
760 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
761 })
762
763DEFINE_INSTRUCTION_ARM(MSRR,
764 int c = opcode & 0x00010000;
765 int f = opcode & 0x00080000;
766 int32_t operand = cpu->gprs[opcode & 0x0000000F];
767 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
768 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
769 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
770
771DEFINE_INSTRUCTION_ARM(MRS, \
772 int rd = (opcode >> 12) & 0xF; \
773 cpu->gprs[rd] = cpu->cpsr.packed;)
774
775DEFINE_INSTRUCTION_ARM(MRSR, \
776 int rd = (opcode >> 12) & 0xF; \
777 cpu->gprs[rd] = cpu->spsr.packed;)
778
779DEFINE_INSTRUCTION_ARM(MSRI,
780 int c = opcode & 0x00010000;
781 int f = opcode & 0x00080000;
782 int rotate = (opcode & 0x00000F00) >> 8;
783 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
784 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
785 if (mask & PSR_USER_MASK) {
786 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
787 }
788 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
789 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
790 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
791 })
792
793DEFINE_INSTRUCTION_ARM(MSRRI,
794 int c = opcode & 0x00010000;
795 int f = opcode & 0x00080000;
796 int rotate = (opcode & 0x00000F00) >> 8;
797 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
798 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
799 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
800 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
801
802DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
803
804#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
805 EMITTER ## NAME
806
807#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
808 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
809 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
810
811#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
822 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
823 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
828
829#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
830 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
831 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
832
833#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
834 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
846 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
847 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
848 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
849 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
850
851#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
852 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
853 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
854
855#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
856 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
857
858// TODO: Support coprocessors
859#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
860 DO_8(0), \
861 DO_8(0)
862
863#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
864 DO_8(DO_8(DO_INTERLACE(0, 0))), \
865 DO_8(DO_8(DO_INTERLACE(0, 0)))
866
867#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
868 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
869
870#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
871 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
872 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
873 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
874 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
875 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
876 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
877 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
878 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
879 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
880 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
881 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
882 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
883 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
884 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
885 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
886 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
887 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
888 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
889 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
890 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
891 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
892 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
893 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
894 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
895 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
896 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
897 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
898 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
899 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
900 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
901 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
902 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
903 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
904 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
905 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
906 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
907 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
908 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
909 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
910 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
911 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
912 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
913 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
914 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
915 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
916 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
917 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
918 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
919 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
920 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
921 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
922 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
923 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
924 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
925 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
926 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
927 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
928 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
929 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
930 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
931 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
932 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
933 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
934 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
935 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
936 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
937 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
938 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
939 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
940 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
941 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
942 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
943 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
944 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
945 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
946 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
947 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
948 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
949 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
950 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
951 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
952 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
953 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
954 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
955 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
956 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
957 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
958 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
959 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
960 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
961 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
962 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
963 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
964 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
965 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
966 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
967 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
968 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
969 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
970 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
971 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
972 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
973 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
974 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
975 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
976 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
977 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
978 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
979 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
980 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
981 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
982 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
983 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
984 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
985 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
986 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
987 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
988 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
989 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
990 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
991 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
992 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
993 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
994 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
995 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
996 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
997 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
998 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
999 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
1000 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
1001 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
1002 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
1003 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
1004 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
1005 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
1006 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
1007 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
1008 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
1009 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
1010 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
1011 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
1012 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
1013 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
1014 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
1015 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
1016 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
1017 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
1018 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
1019 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
1020 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
1021 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
1022 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
1023 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
1024 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
1025 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
1026 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
1027 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
1028 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
1029 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
1030 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
1031 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
1032 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
1033 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
1034 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
1035 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
1036 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
1037 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
1038 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
1039 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
1040 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
1041 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
1042 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
1043 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
1044 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
1045 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
1046 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
1047 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
1048 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
1049 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
1050 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
1051 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
1052 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
1053 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
1054 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
1055 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
1056 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
1057 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
1058 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
1059 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
1060 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
1061 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
1062 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
1063 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
1064 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
1065 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
1066 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
1067 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
1068 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
1069 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
1070 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
1071 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
1072 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
1073 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
1074 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
1075 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
1076 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
1077 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
1078 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
1079 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
1080 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
1081 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
1082 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
1083 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
1084 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
1085 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
1086 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
1087 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
1088 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
1089 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
1090 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
1091 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
1092 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
1093 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
1094 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
1095 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
1096 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1097 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1098 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1099 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1100 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1101 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1102 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1103 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1104 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1105 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1106 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1107 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1108 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1109 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1110 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1111 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1112 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1113 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1114 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1115 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1116 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1117 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1118 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1119 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1120 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1121 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1122 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1123 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1124 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1125 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1126 DECLARE_ARM_SWI_BLOCK(EMITTER)
1127
1128static const ARMInstruction _armTable[0x1000] = {
1129 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1130};