src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
189 cpu->cpsr.flags = 0;
190 cpu->cpsr.n = ARM_SIGN(d);
191 cpu->cpsr.z = !d;
192 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
193 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
194}
195
196ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
197 cpu->cpsr.flags = 0;
198 cpu->cpsr.n = ARM_SIGN(d);
199 cpu->cpsr.z = !d;
200 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
201 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
202}
203
204ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
205 cpu->cpsr.n = ARM_SIGN(d);
206 cpu->cpsr.z = !d; \
207 cpu->cpsr.c = cpu->shifterCarryOut; \
208}
209
210#define ARM_ADDITION_S(M, N, D) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 _additionS(cpu, M, N, D); \
216 }
217
218#define ARM_SUBTRACTION_S(M, N, D) \
219 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
220 cpu->cpsr = cpu->spsr; \
221 _ARMReadCPSR(cpu); \
222 } else { \
223 _subtractionS(cpu, M, N, D); \
224 }
225
226#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
227 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
228 cpu->cpsr = cpu->spsr; \
229 _ARMReadCPSR(cpu); \
230 } else { \
231 cpu->cpsr.n = ARM_SIGN(D); \
232 cpu->cpsr.z = !(D); \
233 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
234 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
235 }
236
237#define ARM_NEUTRAL_S(M, N, D) \
238 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
239 cpu->cpsr = cpu->spsr; \
240 _ARMReadCPSR(cpu); \
241 } else { \
242 _neutralS(cpu, D); \
243 }
244
245#define ARM_NEUTRAL_HI_S(DLO, DHI) \
246 cpu->cpsr.n = ARM_SIGN(DHI); \
247 cpu->cpsr.z = !((DHI) | (DLO));
248
249#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
250#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
251#define ADDR_MODE_2_ADDRESS (address)
252#define ADDR_MODE_2_RN (cpu->gprs[rn])
253#define ADDR_MODE_2_RM (cpu->gprs[rm])
254#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
255#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
256#define ADDR_MODE_2_WRITEBACK(ADDR) \
257 cpu->gprs[rn] = ADDR; \
258 if (UNLIKELY(rn == ARM_PC)) { \
259 currentCycles += ARMWritePC(cpu); \
260 }
261
262#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
263#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
264#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
265#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
266
267#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
268#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
269#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
270#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
271
272#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
273#define ADDR_MODE_3_RN ADDR_MODE_2_RN
274#define ADDR_MODE_3_RM ADDR_MODE_2_RM
275#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
276#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
277#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
278#define ADDR_MODE_3_WRITEBACK_64(ADDR) ADDR_MODE_2_WRITEBACK(ADDR + 4)
279
280#define ADDR_MODE_4_WRITEBACK_LDM \
281 if (!((1 << rn) & rs)) { \
282 cpu->gprs[rn] = address; \
283 }
284
285#define ADDR_MODE_4_WRITEBACK_LDMv5 \
286 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
287 cpu->gprs[rn] = address; \
288 }
289
290#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
291
292#define ARM_LOAD_POST_BODY \
293 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
294 if (rd == ARM_PC) { \
295 currentCycles += ARMWritePC(cpu); \
296 }
297
298#define ARM_LOAD_POST_BODY_v5 \
299 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
300 if (rd == ARM_PC) { \
301 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
302 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
303 if (cpu->executionMode == MODE_THUMB) { \
304 currentCycles += ThumbWritePC(cpu); \
305 } else { \
306 currentCycles += ARMWritePC(cpu); \
307 } \
308 }
309
310#define ARM_STORE_POST_BODY \
311 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
312
313#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
314 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
315 int currentCycles = ARM_PREFETCH_CYCLES; \
316 BODY; \
317 cpu->cycles += currentCycles; \
318 }
319
320#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
321 DEFINE_INSTRUCTION_ARM(NAME, \
322 int rd = (opcode >> 12) & 0xF; \
323 int rn = (opcode >> 16) & 0xF; \
324 int32_t n = cpu->gprs[rn]; \
325 if (UNLIKELY(rn == ARM_PC && (opcode & 0x02000010) == 0x00000010)) { \
326 n += WORD_SIZE_ARM; \
327 } \
328 SHIFTER(cpu, opcode); \
329 BODY; \
330 S_BODY; \
331 if (rd == ARM_PC) { \
332 if (cpu->executionMode == MODE_ARM) { \
333 currentCycles += ARMWritePC(cpu); \
334 } else { \
335 currentCycles += ThumbWritePC(cpu); \
336 } \
337 })
338
339#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
342 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
343 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
344 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
345 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
346 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
347 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
348 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
349 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
350
351#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
352 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
353 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
354 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
355 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
356 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
357
358#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
359 DEFINE_INSTRUCTION_ARM(NAME, \
360 int rd = (opcode >> 16) & 0xF; \
361 int rs = (opcode >> 8) & 0xF; \
362 int rm = opcode & 0xF; \
363 if (rd == ARM_PC) { \
364 return; \
365 } \
366 ARM_WAIT_MUL(cpu->gprs[rs]); \
367 BODY; \
368 S_BODY; \
369 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
370
371#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
372 DEFINE_INSTRUCTION_ARM(NAME, \
373 int rd = (opcode >> 12) & 0xF; \
374 int rdHi = (opcode >> 16) & 0xF; \
375 int rs = (opcode >> 8) & 0xF; \
376 int rm = opcode & 0xF; \
377 if (rdHi == ARM_PC || rd == ARM_PC) { \
378 return; \
379 } \
380 currentCycles += cpu->memory.stall(cpu, WAIT); \
381 BODY; \
382 S_BODY; \
383 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
384
385#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
386 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
387 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
388
389#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
390 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
391 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
392
393#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
394 DEFINE_INSTRUCTION_ARM(NAME, \
395 int rd = (opcode >> 16) & 0xF; \
396 int rs = (opcode >> 8) & 0xF; \
397 int rn = (opcode >> 12) & 0xF; \
398 int rm = opcode & 0xF; \
399 UNUSED(rn); \
400 if (rd == ARM_PC) { \
401 return; \
402 } \
403 /* TODO: Timing */ \
404 int32_t x; \
405 int32_t y; \
406 BODY; \
407 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
408
409#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
410 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
411 x = ARM_SXT_16(cpu->gprs[rm]); \
412 y = ARM_SXT_16(cpu->gprs[rs]); \
413 BODY) \
414 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
415 x = ARM_SXT_16(cpu->gprs[rm]); \
416 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
417 BODY) \
418 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
419 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
420 y = ARM_SXT_16(cpu->gprs[rs]); \
421 BODY) \
422 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
423 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
424 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
425 BODY)
426
427#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
428 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
429 UNUSED(x); \
430 y = ARM_SXT_16(cpu->gprs[rs]); \
431 BODY) \
432 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
433 UNUSED(x); \
434 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
435 BODY) \
436
437#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
438 DEFINE_INSTRUCTION_ARM(NAME, \
439 uint32_t address; \
440 int rn = (opcode >> 16) & 0xF; \
441 int rd = (opcode >> 12) & 0xF; \
442 int32_t d = cpu->gprs[rd]; \
443 if (UNLIKELY(rd == ARM_PC)) { \
444 d += WORD_SIZE_ARM; \
445 } \
446 int rm = opcode & 0xF; \
447 UNUSED(rm); \
448 address = ADDRESS; \
449 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
450 BODY; \
451 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
452
453#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
459 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
460
461#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
472
473#define DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, WRITEBACK) \
474 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
479 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
480 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
481 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
482 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
483 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
485 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
486
487#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, ADDR_MODE_3_WRITEBACK)
488#define DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(NAME, LS, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, LS, BODY, ADDR_MODE_3_WRITEBACK_64)
489
490#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
491 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
492 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
493
494#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
495 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
496 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
497 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
498 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
499 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
500 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
501
502#define ARM_MS_PRE \
503 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
504 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
505
506#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
507
508#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
509 DEFINE_INSTRUCTION_ARM(NAME, \
510 int rn = (opcode >> 16) & 0xF; \
511 int rs = opcode & 0x0000FFFF; \
512 uint32_t address = cpu->gprs[rn]; \
513 S_PRE; \
514 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
515 S_POST; \
516 POST_BODY; \
517 WRITEBACK;)
518
519
520#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
521 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
522 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
523 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
524 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
525 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
526 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
527 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
528 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
529
530#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
531 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
532 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
533 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
534 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
535 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
536 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
537 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
538 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
539 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
540
541// Begin ALU definitions
542
543DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
544 cpu->gprs[rd] = n + cpu->shifterOperand;)
545
546DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
547 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
548
549DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
550 cpu->gprs[rd] = n & cpu->shifterOperand;)
551
552DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
553 cpu->gprs[rd] = n & ~cpu->shifterOperand;)
554
555DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(n, cpu->shifterOperand, aluOut),
556 int32_t aluOut = n + cpu->shifterOperand;)
557
558DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(n, cpu->shifterOperand, aluOut),
559 int32_t aluOut = n - cpu->shifterOperand;)
560
561DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
562 cpu->gprs[rd] = n ^ cpu->shifterOperand;)
563
564DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
565 cpu->gprs[rd] = cpu->shifterOperand;)
566
567DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
568 cpu->gprs[rd] = ~cpu->shifterOperand;)
569
570DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
571 cpu->gprs[rd] = n | cpu->shifterOperand;)
572
573DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
574 cpu->gprs[rd] = cpu->shifterOperand - n;)
575
576DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
577 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
578
579DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
580 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
581
582DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
583 cpu->gprs[rd] = n - cpu->shifterOperand;)
584
585DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
586 int32_t aluOut = n ^ cpu->shifterOperand;)
587
588DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
589 int32_t aluOut = n & cpu->shifterOperand;)
590
591// End ALU definitions
592
593// Begin multiply definitions
594
595DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
596DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
597
598DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
599 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
600 int32_t dm = cpu->gprs[rd];
601 int32_t dn = d;
602 cpu->gprs[rd] = dm + dn;
603 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
604 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
605
606DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
607 int32_t dn = cpu->gprs[rn]; \
608 int32_t d = x * y; \
609 cpu->gprs[rd] = d + dn; \
610 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
611
612DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
613
614DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
615 int32_t dn = cpu->gprs[rn]; \
616 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
617 cpu->gprs[rd] = d + dn; \
618 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
619
620DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
621
622DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
623 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
624 cpu->gprs[rd] = d;
625 cpu->gprs[rdHi] = d >> 32;,
626 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
627
628DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
629 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
630 int32_t dm = cpu->gprs[rd];
631 int32_t dn = d;
632 cpu->gprs[rd] = dm + dn;
633 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
634 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
635
636DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
637 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
638 cpu->gprs[rd] = d;
639 cpu->gprs[rdHi] = d >> 32;,
640 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
641
642// End multiply definitions
643
644// Begin load/store definitions
645
646DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
647DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
648DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
649DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(LDRD, LOAD, cpu->gprs[rd & ~1] = cpu->memory.load32(cpu, address, ¤tCycles); cpu->gprs[rd | 1] = cpu->memory.load32(cpu, address + 4, ¤tCycles); ARM_LOAD_POST_BODY;)
650DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
651DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
652DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
653DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
654DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
655DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(STRD, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd & ~1], ¤tCycles); cpu->memory.store32(cpu, address + 4, cpu->gprs[rd | 1], ¤tCycles); ARM_STORE_POST_BODY;)
656DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
657
658DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
659 enum PrivilegeMode priv = cpu->privilegeMode;
660 ARMSetPrivilegeMode(cpu, MODE_USER);
661 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
662 ARMSetPrivilegeMode(cpu, priv);
663 cpu->gprs[rd] = r;
664 ARM_LOAD_POST_BODY;)
665
666DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
667 enum PrivilegeMode priv = cpu->privilegeMode;
668 ARMSetPrivilegeMode(cpu, MODE_USER);
669 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
670 ARMSetPrivilegeMode(cpu, priv);
671 cpu->gprs[rd] = r;
672 ARM_LOAD_POST_BODY;)
673
674DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
675 enum PrivilegeMode priv = cpu->privilegeMode;
676 int32_t r = cpu->gprs[rd];
677 ARMSetPrivilegeMode(cpu, MODE_USER);
678 cpu->memory.store8(cpu, address, r, ¤tCycles);
679 ARMSetPrivilegeMode(cpu, priv);
680 ARM_STORE_POST_BODY;)
681
682DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
683 enum PrivilegeMode priv = cpu->privilegeMode;
684 int32_t r = cpu->gprs[rd];
685 ARMSetPrivilegeMode(cpu, MODE_USER);
686 cpu->memory.store32(cpu, address, r, ¤tCycles);
687 ARMSetPrivilegeMode(cpu, priv);
688 ARM_STORE_POST_BODY;)
689
690DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
691 load,
692 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
693 if ((rs & 0x8000) || !rs) {
694 currentCycles += ARMWritePC(cpu);
695 })
696
697DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
698 load,
699 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
700 if (rs & 0x8000) {
701 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
702 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
703 if (cpu->executionMode == MODE_THUMB) {
704 currentCycles += ThumbWritePC(cpu);
705 } else {
706 currentCycles += ARMWritePC(cpu);
707
708 }
709 })
710
711DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
712 store,
713 ARM_STORE_POST_BODY;)
714
715DEFINE_INSTRUCTION_ARM(SWP,
716 int rm = opcode & 0xF;
717 int rd = (opcode >> 12) & 0xF;
718 int rn = (opcode >> 16) & 0xF;
719 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
720 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
721 cpu->gprs[rd] = d;)
722
723DEFINE_INSTRUCTION_ARM(SWPB,
724 int rm = opcode & 0xF;
725 int rd = (opcode >> 12) & 0xF;
726 int rn = (opcode >> 16) & 0xF;
727 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
728 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
729 cpu->gprs[rd] = d;)
730
731// End load/store definitions
732
733// Begin branch definitions
734
735DEFINE_INSTRUCTION_ARM(B,
736 int32_t offset = opcode << 8;
737 offset >>= 6;
738 cpu->gprs[ARM_PC] += offset;
739 currentCycles += ARMWritePC(cpu);)
740
741DEFINE_INSTRUCTION_ARM(BL,
742 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
743 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
744 cpu->gprs[ARM_PC] += immediate >> 6;
745 currentCycles += ARMWritePC(cpu);)
746
747DEFINE_INSTRUCTION_ARM(BX,
748 int rm = opcode & 0x0000000F;
749 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
750 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
751 if (cpu->executionMode == MODE_THUMB) {
752 currentCycles += ThumbWritePC(cpu);
753 } else {
754 currentCycles += ARMWritePC(cpu);
755
756 })
757
758DEFINE_INSTRUCTION_ARM(BLX,
759 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
760 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
761 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
762 _ARMSetMode(cpu, MODE_THUMB);
763 currentCycles += ThumbWritePC(cpu);)
764
765DEFINE_INSTRUCTION_ARM(BLX2,
766 int rm = opcode & 0x0000000F;
767 int address = cpu->gprs[rm];
768 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
769 _ARMSetMode(cpu, address & 0x00000001);
770 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
771 if (cpu->executionMode == MODE_THUMB) {
772 currentCycles += ThumbWritePC(cpu);
773 } else {
774 currentCycles += ARMWritePC(cpu);
775 })
776
777// End branch definitions
778
779// Begin coprocessor definitions
780
781#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
782 DEFINE_INSTRUCTION_ARM(NAME, \
783 int op1 = (opcode >> 21) & 7; \
784 int op2 = (opcode >> 5) & 7; \
785 int rd = (opcode >> 12) & 0xF; \
786 int cp = (opcode >> 8) & 0xF; \
787 int crn = (opcode >> 16) & 0xF; \
788 int crm = opcode & 0xF; \
789 UNUSED(op1); \
790 UNUSED(op2); \
791 UNUSED(rd); \
792 UNUSED(crn); \
793 UNUSED(crm); \
794 BODY;)
795
796DEFINE_COPROCESSOR_INSTRUCTION(MRC,
797 if (cp == 15 && cpu->irqh.readCP15) {
798 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
799 } else {
800 ARM_STUB;
801 })
802
803DEFINE_COPROCESSOR_INSTRUCTION(MCR,
804 if (cp == 15 && cpu->irqh.writeCP15) {
805 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
806 } else {
807 ARM_STUB;
808 })
809
810DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
811DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
812DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
813
814// Begin miscellaneous definitions
815
816DEFINE_INSTRUCTION_ARM(CLZ,
817 int rm = opcode & 0xF;
818 int rd = (opcode >> 12) & 0xF;
819 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
820
821DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
822DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
823
824DEFINE_INSTRUCTION_ARM(MSR,
825 int c = opcode & 0x00010000;
826 int f = opcode & 0x00080000;
827 int32_t operand = cpu->gprs[opcode & 0x0000000F];
828 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
829 if (mask & PSR_USER_MASK) {
830 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
831 }
832 if (mask & PSR_STATE_MASK) {
833 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
834 }
835 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
836 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
837 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
838 }
839 _ARMReadCPSR(cpu);
840 if (cpu->executionMode == MODE_THUMB) {
841 cpu->prefetch[0] = 0x46C0; // nop
842 cpu->prefetch[1] &= 0xFFFF;
843 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
844 } else {
845 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
846 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
847 })
848
849DEFINE_INSTRUCTION_ARM(MSRR,
850 int c = opcode & 0x00010000;
851 int f = opcode & 0x00080000;
852 int32_t operand = cpu->gprs[opcode & 0x0000000F];
853 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
854 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
855 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
856
857DEFINE_INSTRUCTION_ARM(MRS, \
858 int rd = (opcode >> 12) & 0xF; \
859 cpu->gprs[rd] = cpu->cpsr.packed;)
860
861DEFINE_INSTRUCTION_ARM(MRSR, \
862 int rd = (opcode >> 12) & 0xF; \
863 cpu->gprs[rd] = cpu->spsr.packed;)
864
865DEFINE_INSTRUCTION_ARM(MSRI,
866 int c = opcode & 0x00010000;
867 int f = opcode & 0x00080000;
868 int rotate = (opcode & 0x00000F00) >> 7;
869 int32_t operand = ROR(opcode & 0x000000FF, rotate);
870 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
871 if (mask & PSR_USER_MASK) {
872 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
873 }
874 if (mask & PSR_STATE_MASK) {
875 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
876 }
877 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
878 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
879 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
880 }
881 _ARMReadCPSR(cpu);
882 if (cpu->executionMode == MODE_THUMB) {
883 cpu->prefetch[0] = 0x46C0; // nop
884 cpu->prefetch[1] &= 0xFFFF;
885 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
886 } else {
887 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
888 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
889 })
890
891DEFINE_INSTRUCTION_ARM(MSRRI,
892 int c = opcode & 0x00010000;
893 int f = opcode & 0x00080000;
894 int rotate = (opcode & 0x00000F00) >> 7;
895 int32_t operand = ROR(opcode & 0x000000FF, rotate);
896 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
897 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
898 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
899
900DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
901
902const ARMInstruction _armv4Table[0x1000] = {
903 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
904};
905
906const ARMInstruction _armv5Table[0x1000] = {
907 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
908};
909
910const ARMInstruction _armv4FTable[0x1000] = {
911 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
912};
913
914const ARMInstruction _armv5FTable[0x1000] = {
915 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
916};