1#ifndef GBA_MEMORY_H
  2#define GBA_MEMORY_H
  3
  4#include "arm.h"
  5
  6enum GBAError {
  7	GBA_NO_ERROR = 0,
  8	GBA_OUT_OF_MEMORY = -1
  9};
 10
 11enum GBALogLevel {
 12	GBA_LOG_STUB
 13};
 14
 15enum GBAMemoryRegion {
 16	REGION_BIOS = 0x0,
 17	REGION_WORKING_RAM = 0x2,
 18	REGION_WORKING_IRAM = 0x3,
 19	REGION_IO = 0x4,
 20	REGION_PALETTE_RAM = 0x5,
 21	REGION_VRAM = 0x6,
 22	REGION_OAM = 0x7,
 23	REGION_CART0 = 0x8,
 24	REGION_CART0_EX = 0x9,
 25	REGION_CART1 = 0xA,
 26	REGION_CART1_EX = 0xB,
 27	REGION_CART2 = 0xC,
 28	REGION_CART2_EX = 0xD,
 29	REGION_CART_SRAM = 0xE
 30};
 31
 32enum GBAMemoryBase {
 33	BASE_BIOS = 0x00000000,
 34	BASE_WORKING_RAM = 0x02000000,
 35	BASE_WORKING_IRAM = 0x03000000,
 36	BASE_IO = 0x04000000,
 37	BASE_PALETTE_RAM = 0x05000000,
 38	BASE_VRAM = 0x06000000,
 39	BASE_OAM = 0x07000000,
 40	BASE_CART0 = 0x08000000,
 41	BASE_CART0_EX = 0x09000000,
 42	BASE_CART1 = 0x0A000000,
 43	BASE_CART1_EX = 0x0B000000,
 44	BASE_CART2 = 0x0C000000,
 45	BASE_CART2_EX = 0x0D000000,
 46	BASE_CART_SRAM = 0x0E000000
 47};
 48
 49enum {
 50	SIZE_BIOS = 0x00004000,
 51	SIZE_WORKING_RAM = 0x00040000,
 52	SIZE_WORKING_IRAM = 0x00008000,
 53	SIZE_IO = 0x00000400,
 54	SIZE_PALETTE_RAM = 0x00000400,
 55	SIZE_VRAM = 0x00018000,
 56	SIZE_OAM = 0x00000400,
 57	SIZE_CART0 = 0x02000000,
 58	SIZE_CART1 = 0x02000000,
 59	SIZE_CART2 = 0x02000000,
 60	SIZE_CART_SRAM = 0x00008000,
 61	SIZE_CART_FLASH512 = 0x00010000,
 62	SIZE_CART_FLASH1M = 0x00020000,
 63	SIZE_CART_EEPROM = 0x00002000
 64};
 65
 66enum GBAIORegisters {
 67	REG_DISPCNT = 0x000,
 68	REG_GREENSWP = 0x002,
 69	REG_DISPSTAT = 0x004,
 70	REG_VCOUNT = 0x006,
 71	REG_BG0CNT = 0x008,
 72	REG_BG1CNT = 0x00A,
 73	REG_BG2CNT = 0x00C,
 74	REG_BG3CNT = 0x00E,
 75	REG_BG0HOFS = 0x010,
 76	REG_BG0VOFS = 0x012,
 77	REG_BG1HOFS = 0x014,
 78	REG_BG1VOFS = 0x016,
 79	REG_BG2HOFS = 0x018,
 80	REG_BG2VOFS = 0x01A,
 81	REG_BG3HOFS = 0x01C,
 82	REG_BG3VOFS = 0x01E,
 83	REG_BG2PA = 0x020,
 84	REG_BG2PB = 0x022,
 85	REG_BG2PC = 0x024,
 86	REG_BG2PD = 0x026,
 87	REG_BG2X_LO = 0x028,
 88	REG_BG2X_HI = 0x02A,
 89	REG_BG2Y_LO = 0x02C,
 90	REG_BG2Y_HI = 0x02E,
 91	REG_BG3PA = 0x030,
 92	REG_BG3PB = 0x032,
 93	REG_BG3PC = 0x034,
 94	REG_BG3PD = 0x036,
 95	REG_BG3X_LO = 0x038,
 96	REG_BG3X_HI = 0x03A,
 97	REG_BG3Y_LO = 0x03C,
 98	REG_BG3Y_HI = 0x03E,
 99	REG_WIN0H = 0x040,
100	REG_WIN1H = 0x042,
101	REG_WIN0V = 0x044,
102	REG_WIN1V = 0x046,
103	REG_WININ = 0x048,
104	REG_WINOUT = 0x04A,
105	REG_MOSAIC = 0x04C,
106	REG_BLDCNT = 0x050,
107	REG_BLDALPHA = 0x052,
108	REG_BLDY = 0x054,
109
110	// Sound
111	REG_SOUND1CNT_LO = 0x060,
112	REG_SOUND1CNT_HI = 0x062,
113	REG_SOUND1CNT_X = 0x064,
114	REG_SOUND2CNT_LO = 0x068,
115	REG_SOUND2CNT_HI = 0x06C,
116	REG_SOUND3CNT_LO = 0x070,
117	REG_SOUND3CNT_HI = 0x072,
118	REG_SOUND3CNT_X = 0x074,
119	REG_SOUND4CNT_LO = 0x078,
120	REG_SOUND4CNT_HI = 0x07C,
121	REG_SOUNDCNT_LO = 0x080,
122	REG_SOUNDCNT_HI = 0x082,
123	REG_SOUNDCNT_X = 0x084,
124	REG_SOUNDBIAS = 0x088,
125	REG_WAVE_RAM0_LO = 0x090,
126	REG_WAVE_RAM0_HI = 0x092,
127	REG_WAVE_RAM1_LO = 0x094,
128	REG_WAVE_RAM1_HI = 0x096,
129	REG_WAVE_RAM2_LO = 0x098,
130	REG_WAVE_RAM2_HI = 0x09A,
131	REG_WAVE_RAM3_LO = 0x09C,
132	REG_WAVE_RAM3_HI = 0x09E,
133	REG_FIFO_A_LO = 0x0A0,
134	REG_FIFO_A_HI = 0x0A2,
135	REG_FIFO_B_LO = 0x0A4,
136	REG_FIFO_B_HI = 0x0A6,
137
138	// DMA
139	REG_DMA0SAD_LO = 0x0B0,
140	REG_DMA0SAD_HI = 0x0B2,
141	REG_DMA0DAD_LO = 0x0B4,
142	REG_DMA0DAD_HI = 0x0B6,
143	REG_DMA0CNT_LO = 0x0B8,
144	REG_DMA0CNT_HI = 0x0BA,
145	REG_DMA1SAD_LO = 0x0BC,
146	REG_DMA1SAD_HI = 0x0BE,
147	REG_DMA1DAD_LO = 0x0C0,
148	REG_DMA1DAD_HI = 0x0C2,
149	REG_DMA1CNT_LO = 0x0C4,
150	REG_DMA1CNT_HI = 0x0C6,
151	REG_DMA2SAD_LO = 0x0C8,
152	REG_DMA2SAD_HI = 0x0CA,
153	REG_DMA2DAD_LO = 0x0CC,
154	REG_DMA2DAD_HI = 0x0CE,
155	REG_DMA2CNT_LO = 0x0D0,
156	REG_DMA2CNT_HI = 0x0D2,
157	REG_DMA3SAD_LO = 0x0D4,
158	REG_DMA3SAD_HI = 0x0D6,
159	REG_DMA3DAD_LO = 0x0D8,
160	REG_DMA3DAD_HI = 0x0DA,
161	REG_DMA3CNT_LO = 0x0DC,
162	REG_DMA3CNT_HI = 0x0DE,
163
164	// Timers
165	REG_TM0CNT_LO = 0x100,
166	REG_TM0CNT_HI = 0x102,
167	REG_TM1CNT_LO = 0x104,
168	REG_TM1CNT_HI = 0x106,
169	REG_TM2CNT_LO = 0x108,
170	REG_TM2CNT_HI = 0x10A,
171	REG_TM3CNT_LO = 0x10C,
172	REG_TM3CNT_HI = 0x10E,
173
174	// SIO (note: some of these are repeated)
175	REG_SIODATA32_LO = 0x120,
176	REG_SIOMULTI0 = 0x120,
177	REG_SIODATA32_HI = 0x122,
178	REG_SIOMULTI1 = 0x122,
179	REG_SIOMULTI2 = 0x124,
180	REG_SIOMULTI3 = 0x126,
181	REG_SIOCNT = 0x128,
182	REG_SIOMLT_SEND = 0x12A,
183	REG_SIODATA8 = 0x12A,
184	REG_RCNT = 0x134,
185	REG_JOYCNT = 0x140,
186	REG_JOY_RECV = 0x150,
187	REG_JOY_TRANS = 0x154,
188	REG_JOYSTAT = 0x158,
189
190	// Keypad
191	REG_KEYINPUT = 0x130,
192	REG_KEYCNT = 0x132,
193
194	// Interrupts, etc
195	REG_IE = 0x200,
196	REG_IF = 0x202,
197	REG_WAITCNT = 0x204,
198	REG_IME = 0x208,
199
200	REG_POSTFLG = 0x300,
201	REG_HALTCNT = 0x301
202};
203
204enum {
205	SP_BASE_SYSTEM = 0x03FFFF00,
206	SP_BASE_IRQ = 0x03FFFFA0,
207	SP_BASE_SUPERVISOR = 0x03FFFFE0
208};
209
210enum {
211	OFFSET_MASK = 0x00FFFFFF
212};
213
214struct GBAMemory {
215	struct ARMMemory d;
216	struct GBA* p;
217
218	uint32_t* bios;
219	uint32_t* wram;
220	uint32_t* iwram;
221	uint32_t* rom;
222	uint16_t io[SIZE_IO >> 1];
223};
224
225struct GBABoard {
226	struct ARMBoard d;
227	struct GBA* p;
228};
229
230struct GBA {
231	struct ARMCore cpu;
232	struct GBABoard board;
233	struct GBAMemory memory;
234
235	struct ARMDebugger* debugger;
236
237	enum GBAError errno;
238	const char* errstr;
239};
240
241void GBAInit(struct GBA* gba);
242void GBADeinit(struct GBA* gba);
243
244void GBAMemoryInit(struct GBAMemory* memory);
245void GBAMemoryDeinit(struct GBAMemory* memory);
246
247void GBABoardInit(struct GBABoard* board);
248void GBABoardReset(struct ARMBoard* board);
249
250void GBAAttachDebugger(struct GBA* gba, struct ARMDebugger* debugger);
251
252void GBALoadROM(struct GBA* gba, int fd);
253
254#endif