src/gba/gba-memory.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "gba-memory.h"
7
8#include "macros.h"
9
10#include "gba-gpio.h"
11#include "gba-io.h"
12#include "gba-serialize.h"
13#include "hle-bios.h"
14#include "util/memory.h"
15
16static uint32_t _popcount32(unsigned bits);
17static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
18
19static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
20static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
21
22static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
23static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
24static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
25static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
26static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
27static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
28static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
29
30void GBAMemoryInit(struct GBA* gba) {
31 struct ARMCore* cpu = gba->cpu;
32 cpu->memory.load32 = GBALoad32;
33 cpu->memory.load16 = GBALoad16;
34 cpu->memory.load8 = GBALoad8;
35 cpu->memory.loadMultiple = GBALoadMultiple;
36 cpu->memory.store32 = GBAStore32;
37 cpu->memory.store16 = GBAStore16;
38 cpu->memory.store8 = GBAStore8;
39 cpu->memory.storeMultiple = GBAStoreMultiple;
40
41 gba->memory.bios = (uint32_t*) hleBios;
42 gba->memory.fullBios = 0;
43 gba->memory.wram = 0;
44 gba->memory.iwram = 0;
45 gba->memory.rom = 0;
46 gba->memory.gpio.p = gba;
47
48 int i;
49 for (i = 0; i < 16; ++i) {
50 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
51 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
53 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
54 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
55 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
56 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
57 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
58 }
59 for (; i < 256; ++i) {
60 gba->memory.waitstatesNonseq16[i] = 0;
61 gba->memory.waitstatesSeq16[i] = 0;
62 gba->memory.waitstatesNonseq32[i] = 0;
63 gba->memory.waitstatesSeq32[i] = 0;
64 }
65
66 gba->memory.activeRegion = -1;
67 cpu->memory.activeRegion = 0;
68 cpu->memory.activeMask = 0;
69 cpu->memory.setActiveRegion = GBASetActiveRegion;
70 cpu->memory.activeSeqCycles32 = 0;
71 cpu->memory.activeSeqCycles16 = 0;
72 cpu->memory.activeNonseqCycles32 = 0;
73 cpu->memory.activeNonseqCycles16 = 0;
74 cpu->memory.activeUncachedCycles32 = 0;
75 cpu->memory.activeUncachedCycles16 = 0;
76 gba->memory.biosPrefetch = 0;
77}
78
79void GBAMemoryDeinit(struct GBA* gba) {
80 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
81 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
82 if (gba->memory.rom) {
83 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
84 }
85 GBASavedataDeinit(&gba->memory.savedata);
86}
87
88void GBAMemoryReset(struct GBA* gba) {
89 if (gba->memory.wram) {
90 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
91 }
92 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
93
94 if (gba->memory.iwram) {
95 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
96 }
97 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
98
99 memset(gba->memory.io, 0, sizeof(gba->memory.io));
100 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
101 int i;
102 for (i = 0; i < 4; ++i) {
103 gba->memory.dma[i].count = 0x10000;
104 gba->memory.dma[i].nextEvent = INT_MAX;
105 }
106 gba->memory.activeDMA = -1;
107 gba->memory.nextDMA = INT_MAX;
108 gba->memory.eventDiff = 0;
109
110 if (!gba->memory.wram || !gba->memory.iwram) {
111 GBAMemoryDeinit(gba);
112 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
113 }
114}
115
116static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
117 struct GBA* gba = (struct GBA*) cpu->master;
118 struct GBAMemory* memory = &gba->memory;
119
120 if (address == gba->busyLoop && memory->activeRegion != REGION_BIOS) {
121 GBAHalt(gba);
122 }
123
124 int newRegion = address >> BASE_OFFSET;
125 if (newRegion == memory->activeRegion) {
126 return;
127 }
128 if (memory->activeRegion == REGION_BIOS) {
129 memory->biosPrefetch = cpu->prefetch[1];
130 }
131 memory->activeRegion = newRegion;
132 switch (address & ~OFFSET_MASK) {
133 case BASE_BIOS:
134 cpu->memory.activeRegion = memory->bios;
135 cpu->memory.activeMask = SIZE_BIOS - 1;
136 break;
137 case BASE_WORKING_RAM:
138 cpu->memory.activeRegion = memory->wram;
139 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
140 break;
141 case BASE_WORKING_IRAM:
142 cpu->memory.activeRegion = memory->iwram;
143 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
144 break;
145 case BASE_VRAM:
146 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
147 cpu->memory.activeMask = 0x0000FFFF;
148 break;
149 case BASE_CART0:
150 case BASE_CART0_EX:
151 case BASE_CART1:
152 case BASE_CART1_EX:
153 case BASE_CART2:
154 case BASE_CART2_EX:
155 cpu->memory.activeRegion = memory->rom;
156 cpu->memory.activeMask = SIZE_CART0 - 1;
157 break;
158 default:
159 cpu->memory.activeRegion = _deadbeef;
160 cpu->memory.activeMask = 0;
161 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
162 break;
163 }
164 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
165 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
166 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
167 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
168 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
169 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
170}
171
172#define LOAD_BAD \
173 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
174 if (cpu->cycles >= cpu->nextEvent) { \
175 value = gba->bus; \
176 } else { \
177 value = cpu->prefetch[1]; \
178 if (cpu->executionMode == MODE_THUMB) { \
179 value |= value << 16; \
180 } \
181 }
182
183#define LOAD_BIOS \
184 if (address < SIZE_BIOS) { \
185 if (memory->activeRegion == REGION_BIOS) { \
186 LOAD_32(value, address, memory->bios); \
187 } else { \
188 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
189 value = memory->biosPrefetch; \
190 } \
191 } else { \
192 LOAD_BAD; \
193 }
194
195#define LOAD_WORKING_RAM \
196 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
197 wait += waitstatesRegion[REGION_WORKING_RAM];
198
199#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
200#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
201
202#define LOAD_PALETTE_RAM \
203 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
204 ++wait;
205
206#define LOAD_VRAM \
207 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
208 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
209 } else { \
210 LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
211 } \
212 ++wait;
213
214#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
215
216#define LOAD_CART \
217 wait += waitstatesRegion[address >> BASE_OFFSET]; \
218 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
219 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
220 } else { \
221 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
222 value = (address >> 1) & 0xFFFF; \
223 value |= value << 16; \
224 }
225
226#define LOAD_SRAM \
227 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
228 value = GBALoad8(cpu, address, 0); \
229 value |= value << 8; \
230 value |= value << 16;
231
232uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
233 struct GBA* gba = (struct GBA*) cpu->master;
234 struct GBAMemory* memory = &gba->memory;
235 uint32_t value = 0;
236 int wait = 0;
237 char* waitstatesRegion = memory->waitstatesNonseq32;
238
239 switch (address >> BASE_OFFSET) {
240 case REGION_BIOS:
241 LOAD_BIOS;
242 break;
243 case REGION_WORKING_RAM:
244 LOAD_WORKING_RAM;
245 break;
246 case REGION_WORKING_IRAM:
247 LOAD_WORKING_IRAM;
248 break;
249 case REGION_IO:
250 LOAD_IO;
251 break;
252 case REGION_PALETTE_RAM:
253 LOAD_PALETTE_RAM;
254 break;
255 case REGION_VRAM:
256 LOAD_VRAM;
257 break;
258 case REGION_OAM:
259 LOAD_OAM;
260 break;
261 case REGION_CART0:
262 case REGION_CART0_EX:
263 case REGION_CART1:
264 case REGION_CART1_EX:
265 case REGION_CART2:
266 case REGION_CART2_EX:
267 LOAD_CART;
268 break;
269 case REGION_CART_SRAM:
270 case REGION_CART_SRAM_MIRROR:
271 LOAD_SRAM;
272 break;
273 default:
274 LOAD_BAD;
275 break;
276 }
277
278 if (cycleCounter) {
279 *cycleCounter += 2 + wait;
280 }
281 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
282 int rotate = (address & 3) << 3;
283 return ROR(value, rotate);
284}
285
286uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
287 struct GBA* gba = (struct GBA*) cpu->master;
288 struct GBAMemory* memory = &gba->memory;
289 uint32_t value = 0;
290 int wait = 0;
291
292 switch (address >> BASE_OFFSET) {
293 case REGION_BIOS:
294 if (address < SIZE_BIOS) {
295 if (memory->activeRegion == REGION_BIOS) {
296 LOAD_16(value, address, memory->bios);
297 } else {
298 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
299 value = memory->biosPrefetch & 0xFFFF;
300 }
301 } else {
302 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
303 if (cpu->cycles >= cpu->nextEvent) {
304 value = gba->bus & 0xFFFF;
305 } else {
306 value = cpu->prefetch[1] & 0xFFFF;
307 }
308 }
309 break;
310 case REGION_WORKING_RAM:
311 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
312 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
313 break;
314 case REGION_WORKING_IRAM:
315 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
316 break;
317 case REGION_IO:
318 value = GBAIORead(gba, address & (SIZE_IO - 1));
319 break;
320 case REGION_PALETTE_RAM:
321 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
322 break;
323 case REGION_VRAM:
324 if ((address & 0x0001FFFF) < SIZE_VRAM) {
325 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
326 } else {
327 LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
328 }
329 break;
330 case REGION_OAM:
331 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
332 break;
333 case REGION_CART0:
334 case REGION_CART0_EX:
335 case REGION_CART1:
336 case REGION_CART1_EX:
337 case REGION_CART2:
338 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
339 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
340 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
341 } else {
342 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
343 value = (address >> 1) & 0xFFFF; \
344 }
345 break;
346 case REGION_CART2_EX:
347 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
348 if (memory->savedata.type == SAVEDATA_EEPROM) {
349 value = GBASavedataReadEEPROM(&memory->savedata);
350 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
351 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
352 } else {
353 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
354 value = (address >> 1) & 0xFFFF; \
355 }
356 break;
357 case REGION_CART_SRAM:
358 case REGION_CART_SRAM_MIRROR:
359 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
360 value = GBALoad8(cpu, address, 0);
361 value |= value << 8;
362 break;
363 default:
364 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
365 if (cpu->cycles >= cpu->nextEvent) {
366 value = gba->bus;
367 } else {
368 value = cpu->prefetch[1];
369 }
370 break;
371 }
372
373 if (cycleCounter) {
374 *cycleCounter += 2 + wait;
375 }
376 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
377 int rotate = (address & 1) << 3;
378 return ROR(value, rotate);
379}
380
381uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
382 struct GBA* gba = (struct GBA*) cpu->master;
383 struct GBAMemory* memory = &gba->memory;
384 uint8_t value = 0;
385 int wait = 0;
386
387 switch (address >> BASE_OFFSET) {
388 case REGION_BIOS:
389 if (address < SIZE_BIOS) {
390 if (memory->activeRegion == REGION_BIOS) {
391 value = ((int8_t*) memory->bios)[address];
392 } else {
393 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
394 value = memory->biosPrefetch;
395 }
396 } else {
397 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
398 if (cpu->cycles >= cpu->nextEvent) {
399 value = gba->bus;
400 } else {
401 value = cpu->prefetch[1];
402 }
403 }
404 break;
405 case REGION_WORKING_RAM:
406 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
407 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
408 break;
409 case REGION_WORKING_IRAM:
410 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
411 break;
412 case REGION_IO:
413 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
414 break;
415 case REGION_PALETTE_RAM:
416 value = ((int8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
417 break;
418 case REGION_VRAM:
419 if ((address & 0x0001FFFF) < SIZE_VRAM) {
420 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
421 } else {
422 value = ((int8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
423 }
424 break;
425 case REGION_OAM:
426 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
427 break;
428 case REGION_CART0:
429 case REGION_CART0_EX:
430 case REGION_CART1:
431 case REGION_CART1_EX:
432 case REGION_CART2:
433 case REGION_CART2_EX:
434 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
435 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
436 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
437 } else {
438 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
439 value = (address >> 1) & 0xFF; \
440 }
441 break;
442 case REGION_CART_SRAM:
443 case REGION_CART_SRAM_MIRROR:
444 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
445 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
446 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
447 GBASavedataInitSRAM(&memory->savedata);
448 }
449 if (memory->savedata.type == SAVEDATA_SRAM) {
450 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
451 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
452 value = GBASavedataReadFlash(&memory->savedata, address);
453 } else if (memory->gpio.gpioDevices & GPIO_TILT) {
454 value = GBAGPIOTiltRead(&memory->gpio, address & OFFSET_MASK);
455 } else {
456 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
457 value = 0xFF;
458 }
459 break;
460 default:
461 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
462 if (cpu->cycles >= cpu->nextEvent) {
463 value = gba->bus;
464 } else {
465 value = cpu->prefetch[1];
466 }
467 break;
468 }
469
470 if (cycleCounter) {
471 *cycleCounter += 2 + wait;
472 }
473 return value;
474}
475
476#define STORE_WORKING_RAM \
477 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
478 wait += waitstatesRegion[REGION_WORKING_RAM];
479
480#define STORE_WORKING_IRAM \
481 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
482
483#define STORE_IO \
484 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
485
486#define STORE_PALETTE_RAM \
487 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
488 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
489 ++wait; \
490 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
491
492#define STORE_VRAM \
493 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
494 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
495 } else { \
496 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
497 } \
498 ++wait;
499
500#define STORE_OAM \
501 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
502 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
503 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
504
505#define STORE_CART \
506 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
507
508#define STORE_SRAM \
509 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
510
511#define STORE_BAD \
512 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
513
514void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
515 struct GBA* gba = (struct GBA*) cpu->master;
516 struct GBAMemory* memory = &gba->memory;
517 int wait = 0;
518 char* waitstatesRegion = memory->waitstatesNonseq32;
519
520 switch (address >> BASE_OFFSET) {
521 case REGION_WORKING_RAM:
522 STORE_WORKING_RAM;
523 break;
524 case REGION_WORKING_IRAM:
525 STORE_WORKING_IRAM
526 break;
527 case REGION_IO:
528 STORE_IO;
529 break;
530 case REGION_PALETTE_RAM:
531 STORE_PALETTE_RAM;
532 break;
533 case REGION_VRAM:
534 STORE_VRAM;
535 break;
536 case REGION_OAM:
537 STORE_OAM;
538 break;
539 case REGION_CART0:
540 case REGION_CART0_EX:
541 case REGION_CART1:
542 case REGION_CART1_EX:
543 case REGION_CART2:
544 case REGION_CART2_EX:
545 STORE_CART;
546 break;
547 case REGION_CART_SRAM:
548 case REGION_CART_SRAM_MIRROR:
549 STORE_SRAM;
550 break;
551 default:
552 STORE_BAD;
553 break;
554 }
555
556 if (cycleCounter) {
557 *cycleCounter += 1 + wait;
558 }
559}
560
561void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
562 struct GBA* gba = (struct GBA*) cpu->master;
563 struct GBAMemory* memory = &gba->memory;
564 int wait = 0;
565
566 switch (address >> BASE_OFFSET) {
567 case REGION_WORKING_RAM:
568 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
569 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
570 break;
571 case REGION_WORKING_IRAM:
572 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
573 break;
574 case REGION_IO:
575 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
576 break;
577 case REGION_PALETTE_RAM:
578 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
579 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
580 break;
581 case REGION_VRAM:
582 if ((address & 0x0001FFFF) < SIZE_VRAM) {
583 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
584 } else {
585 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
586 }
587 break;
588 case REGION_OAM:
589 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
590 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
591 break;
592 case REGION_CART0:
593 if (memory->gpio.gpioDevices != GPIO_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
594 uint32_t reg = address & 0xFFFFFF;
595 GBAGPIOWrite(&memory->gpio, reg, value);
596 } else {
597 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
598 }
599 break;
600 case REGION_CART2_EX:
601 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
602 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
603 GBASavedataInitEEPROM(&memory->savedata);
604 }
605 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
606 break;
607 case REGION_CART_SRAM:
608 case REGION_CART_SRAM_MIRROR:
609 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
610 break;
611 default:
612 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
613 break;
614 }
615
616 if (cycleCounter) {
617 *cycleCounter += 1 + wait;
618 }
619}
620
621void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
622 struct GBA* gba = (struct GBA*) cpu->master;
623 struct GBAMemory* memory = &gba->memory;
624 int wait = 0;
625
626 switch (address >> BASE_OFFSET) {
627 case REGION_WORKING_RAM:
628 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
629 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
630 break;
631 case REGION_WORKING_IRAM:
632 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
633 break;
634 case REGION_IO:
635 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
636 break;
637 case REGION_PALETTE_RAM:
638 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
639 break;
640 case REGION_VRAM:
641 if (address >= 0x06018000) {
642 // TODO: check BG mode
643 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
644 break;
645 }
646 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
647 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
648 break;
649 case REGION_OAM:
650 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
651 break;
652 case REGION_CART0:
653 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
654 break;
655 case REGION_CART_SRAM:
656 case REGION_CART_SRAM_MIRROR:
657 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
658 if (address == SAVEDATA_FLASH_BASE) {
659 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
660 GBASavedataInitFlash(&memory->savedata);
661 } else {
662 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
663 GBASavedataInitSRAM(&memory->savedata);
664 }
665 }
666 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
667 GBASavedataWriteFlash(&memory->savedata, address, value);
668 } else if (memory->savedata.type == SAVEDATA_SRAM) {
669 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
670 } else if (memory->gpio.gpioDevices & GPIO_TILT) {
671 GBAGPIOTiltWrite(&memory->gpio, address & OFFSET_MASK, value);
672 } else {
673 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
674 }
675 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
676 break;
677 default:
678 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
679 break;
680 }
681
682 if (cycleCounter) {
683 *cycleCounter += 1 + wait;
684 }
685}
686
687#define LDM_LOOP(LDM) \
688 for (i = 0; i < 16; i += 4) { \
689 if (UNLIKELY(mask & (1 << i))) { \
690 LDM; \
691 waitstatesRegion = memory->waitstatesSeq32; \
692 cpu->gprs[i] = value; \
693 ++wait; \
694 address += 4; \
695 } \
696 if (UNLIKELY(mask & (2 << i))) { \
697 LDM; \
698 waitstatesRegion = memory->waitstatesSeq32; \
699 cpu->gprs[i + 1] = value; \
700 ++wait; \
701 address += 4; \
702 } \
703 if (UNLIKELY(mask & (4 << i))) { \
704 LDM; \
705 waitstatesRegion = memory->waitstatesSeq32; \
706 cpu->gprs[i + 2] = value; \
707 ++wait; \
708 address += 4; \
709 } \
710 if (UNLIKELY(mask & (8 << i))) { \
711 LDM; \
712 waitstatesRegion = memory->waitstatesSeq32; \
713 cpu->gprs[i + 3] = value; \
714 ++wait; \
715 address += 4; \
716 } \
717 }
718
719uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
720 struct GBA* gba = (struct GBA*) cpu->master;
721 struct GBAMemory* memory = &gba->memory;
722 uint32_t value;
723 int wait = 0;
724 char* waitstatesRegion = memory->waitstatesNonseq32;
725
726 int i;
727 int offset = 4;
728 int popcount = 0;
729 if (direction & LSM_D) {
730 offset = -4;
731 popcount = _popcount32(mask);
732 address -= (popcount << 2) - 4;
733 }
734
735 if (direction & LSM_B) {
736 address += offset;
737 }
738
739 uint32_t addressMisalign = address & 0x3;
740 address &= 0xFFFFFFFC;
741
742 switch (address >> BASE_OFFSET) {
743 case REGION_BIOS:
744 LDM_LOOP(LOAD_BIOS);
745 break;
746 case REGION_WORKING_RAM:
747 LDM_LOOP(LOAD_WORKING_RAM);
748 break;
749 case REGION_WORKING_IRAM:
750 LDM_LOOP(LOAD_WORKING_IRAM);
751 break;
752 case REGION_IO:
753 LDM_LOOP(LOAD_IO);
754 break;
755 case REGION_PALETTE_RAM:
756 LDM_LOOP(LOAD_PALETTE_RAM);
757 break;
758 case REGION_VRAM:
759 LDM_LOOP(LOAD_VRAM);
760 break;
761 case REGION_OAM:
762 LDM_LOOP(LOAD_OAM);
763 break;
764 case REGION_CART0:
765 case REGION_CART0_EX:
766 case REGION_CART1:
767 case REGION_CART1_EX:
768 case REGION_CART2:
769 case REGION_CART2_EX:
770 LDM_LOOP(LOAD_CART);
771 break;
772 case REGION_CART_SRAM:
773 case REGION_CART_SRAM_MIRROR:
774 LDM_LOOP(LOAD_SRAM);
775 break;
776 default:
777 LDM_LOOP(LOAD_BAD);
778 break;
779 }
780
781 if (cycleCounter) {
782 *cycleCounter += wait;
783 }
784
785 if (direction & LSM_B) {
786 address -= offset;
787 }
788
789 if (direction & LSM_D) {
790 address -= (popcount << 2) + 4;
791 }
792
793 return address | addressMisalign;
794}
795
796#define STM_LOOP(STM) \
797 for (i = 0; i < 16; i += 4) { \
798 if (UNLIKELY(mask & (1 << i))) { \
799 value = cpu->gprs[i]; \
800 STM; \
801 waitstatesRegion = memory->waitstatesSeq32; \
802 ++wait; \
803 address += 4; \
804 } \
805 if (UNLIKELY(mask & (2 << i))) { \
806 value = cpu->gprs[i + 1]; \
807 STM; \
808 waitstatesRegion = memory->waitstatesSeq32; \
809 ++wait; \
810 address += 4; \
811 } \
812 if (UNLIKELY(mask & (4 << i))) { \
813 value = cpu->gprs[i + 2]; \
814 STM; \
815 waitstatesRegion = memory->waitstatesSeq32; \
816 ++wait; \
817 address += 4; \
818 } \
819 if (UNLIKELY(mask & (8 << i))) { \
820 value = cpu->gprs[i + 3]; \
821 STM; \
822 waitstatesRegion = memory->waitstatesSeq32; \
823 ++wait; \
824 address += 4; \
825 } \
826 }
827
828uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
829 struct GBA* gba = (struct GBA*) cpu->master;
830 struct GBAMemory* memory = &gba->memory;
831 uint32_t value;
832 int wait = 0;
833 char* waitstatesRegion = memory->waitstatesNonseq32;
834
835 int i;
836 int offset = 4;
837 int popcount = 0;
838 if (direction & LSM_D) {
839 offset = -4;
840 popcount = _popcount32(mask);
841 address -= (popcount << 2) - 4;
842 }
843
844 if (direction & LSM_B) {
845 address += offset;
846 }
847
848 uint32_t addressMisalign = address & 0x3;
849 address &= 0xFFFFFFFC;
850
851 switch (address >> BASE_OFFSET) {
852 case REGION_WORKING_RAM:
853 STM_LOOP(STORE_WORKING_RAM);
854 break;
855 case REGION_WORKING_IRAM:
856 STM_LOOP(STORE_WORKING_IRAM);
857 break;
858 case REGION_IO:
859 STM_LOOP(STORE_IO);
860 break;
861 case REGION_PALETTE_RAM:
862 STM_LOOP(STORE_PALETTE_RAM);
863 break;
864 case REGION_VRAM:
865 STM_LOOP(STORE_VRAM);
866 break;
867 case REGION_OAM:
868 STM_LOOP(STORE_OAM);
869 break;
870 case REGION_CART0:
871 case REGION_CART0_EX:
872 case REGION_CART1:
873 case REGION_CART1_EX:
874 case REGION_CART2:
875 case REGION_CART2_EX:
876 STM_LOOP(STORE_CART);
877 break;
878 case REGION_CART_SRAM:
879 case REGION_CART_SRAM_MIRROR:
880 STM_LOOP(STORE_SRAM);
881 break;
882 default:
883 STM_LOOP(STORE_BAD);
884 break;
885 }
886
887 if (cycleCounter) {
888 *cycleCounter += wait;
889 }
890
891 if (direction & LSM_B) {
892 address -= offset;
893 }
894
895 if (direction & LSM_D) {
896 address -= (popcount << 2) + 4;
897 }
898
899 return address | addressMisalign;
900}
901
902void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
903 struct GBAMemory* memory = &gba->memory;
904 struct ARMCore* cpu = gba->cpu;
905 int sram = parameters & 0x0003;
906 int ws0 = (parameters & 0x000C) >> 2;
907 int ws0seq = (parameters & 0x0010) >> 4;
908 int ws1 = (parameters & 0x0060) >> 5;
909 int ws1seq = (parameters & 0x0080) >> 7;
910 int ws2 = (parameters & 0x0300) >> 8;
911 int ws2seq = (parameters & 0x0400) >> 10;
912 int prefetch = parameters & 0x4000;
913
914 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
915 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
916 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
917 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
918
919 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
920 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
921 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
922
923 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
924 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
925 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
926
927 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
928 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
929 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
930
931 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
932 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
933 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
934
935 if (!prefetch) {
936 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
937 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
938 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
939
940 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
941 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
942 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
943
944 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
945 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
946 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
947
948 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
949 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
950 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
951 } else {
952 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
953 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
954 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
955
956 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
957 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
958 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
959
960 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
961 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
962 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
963
964 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
965 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
966 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
967 }
968
969 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
970 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
971
972 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
973 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
974
975 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
976 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
977}
978
979void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
980 struct GBAMemory* memory = &gba->memory;
981 memory->dma[dma].source = address & 0x0FFFFFFE;
982}
983
984void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
985 struct GBAMemory* memory = &gba->memory;
986 memory->dma[dma].dest = address & 0x0FFFFFFE;
987}
988
989void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
990 struct GBAMemory* memory = &gba->memory;
991 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
992}
993
994uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
995 struct GBAMemory* memory = &gba->memory;
996 struct GBADMA* currentDma = &memory->dma[dma];
997 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
998 currentDma->reg = control;
999
1000 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1001 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1002 }
1003
1004 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1005 currentDma->nextSource = currentDma->source;
1006 currentDma->nextDest = currentDma->dest;
1007 currentDma->nextCount = currentDma->count;
1008 GBAMemoryScheduleDMA(gba, dma, currentDma);
1009 }
1010 // If the DMA has already occurred, this value might have changed since the function started
1011 return currentDma->reg;
1012};
1013
1014void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1015 struct ARMCore* cpu = gba->cpu;
1016 switch (GBADMARegisterGetTiming(info->reg)) {
1017 case DMA_TIMING_NOW:
1018 info->nextEvent = cpu->cycles;
1019 GBAMemoryUpdateDMAs(gba, 0);
1020 break;
1021 case DMA_TIMING_HBLANK:
1022 // Handled implicitly
1023 info->nextEvent = INT_MAX;
1024 break;
1025 case DMA_TIMING_VBLANK:
1026 // Handled implicitly
1027 info->nextEvent = INT_MAX;
1028 break;
1029 case DMA_TIMING_CUSTOM:
1030 info->nextEvent = INT_MAX;
1031 switch (number) {
1032 case 0:
1033 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1034 break;
1035 case 1:
1036 case 2:
1037 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1038 break;
1039 case 3:
1040 // GBAVideoScheduleVCaptureDma(dma, info);
1041 break;
1042 }
1043 }
1044}
1045
1046void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1047 struct GBAMemory* memory = &gba->memory;
1048 struct GBADMA* dma;
1049 int i;
1050 for (i = 0; i < 4; ++i) {
1051 dma = &memory->dma[i];
1052 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1053 dma->nextEvent = cycles;
1054 }
1055 }
1056 GBAMemoryUpdateDMAs(gba, 0);
1057}
1058
1059void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1060 struct GBAMemory* memory = &gba->memory;
1061 struct GBADMA* dma;
1062 int i;
1063 for (i = 0; i < 4; ++i) {
1064 dma = &memory->dma[i];
1065 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1066 dma->nextEvent = cycles;
1067 }
1068 }
1069 GBAMemoryUpdateDMAs(gba, 0);
1070}
1071
1072int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1073 struct GBAMemory* memory = &gba->memory;
1074 if (memory->nextDMA == INT_MAX) {
1075 return INT_MAX;
1076 }
1077 memory->nextDMA -= cycles;
1078 memory->eventDiff += cycles;
1079 if (memory->nextDMA <= 0) {
1080 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1081 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1082 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1083 memory->eventDiff = 0;
1084 }
1085 return memory->nextDMA;
1086}
1087
1088void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1089 int i;
1090 struct GBAMemory* memory = &gba->memory;
1091 struct ARMCore* cpu = gba->cpu;
1092 memory->activeDMA = -1;
1093 memory->nextDMA = INT_MAX;
1094 for (i = 3; i >= 0; --i) {
1095 struct GBADMA* dma = &memory->dma[i];
1096 if (dma->nextEvent != INT_MAX) {
1097 dma->nextEvent -= cycles;
1098 if (GBADMARegisterIsEnable(dma->reg)) {
1099 memory->activeDMA = i;
1100 memory->nextDMA = dma->nextEvent;
1101 }
1102 }
1103 }
1104 if (memory->nextDMA < cpu->nextEvent) {
1105 cpu->nextEvent = memory->nextDMA;
1106 }
1107}
1108
1109void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1110 struct GBAMemory* memory = &gba->memory;
1111 struct ARMCore* cpu = gba->cpu;
1112 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1113 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1114 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1115 int32_t wordsRemaining = info->nextCount;
1116 uint32_t source = info->nextSource;
1117 uint32_t dest = info->nextDest;
1118 uint32_t sourceRegion = source >> BASE_OFFSET;
1119 uint32_t destRegion = dest >> BASE_OFFSET;
1120 int32_t cycles = 2;
1121
1122 if (source == info->source) {
1123 // TODO: support 4 cycles for ROM access
1124 cycles += 2;
1125 if (width == 4) {
1126 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1127 source &= 0xFFFFFFFC;
1128 dest &= 0xFFFFFFFC;
1129 } else {
1130 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1131 }
1132 } else {
1133 if (width == 4) {
1134 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1135 } else {
1136 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1137 }
1138 }
1139
1140 int32_t word;
1141 if (width == 4) {
1142 word = cpu->memory.load32(cpu, source, 0);
1143 gba->bus = word;
1144 cpu->memory.store32(cpu, dest, word, 0);
1145 source += sourceOffset;
1146 dest += destOffset;
1147 --wordsRemaining;
1148 } else {
1149 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1150 word = GBASavedataReadEEPROM(&memory->savedata);
1151 gba->bus = word | (word << 16);
1152 cpu->memory.store16(cpu, dest, word, 0);
1153 source += sourceOffset;
1154 dest += destOffset;
1155 --wordsRemaining;
1156 } else if (destRegion == REGION_CART2_EX) {
1157 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1158 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1159 GBASavedataInitEEPROM(&memory->savedata);
1160 }
1161 word = cpu->memory.load16(cpu, source, 0);
1162 gba->bus = word | (word << 16);
1163 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1164 source += sourceOffset;
1165 dest += destOffset;
1166 --wordsRemaining;
1167 } else {
1168 word = cpu->memory.load16(cpu, source, 0);
1169 gba->bus = word | (word << 16);
1170 cpu->memory.store16(cpu, dest, word, 0);
1171 source += sourceOffset;
1172 dest += destOffset;
1173 --wordsRemaining;
1174 }
1175 }
1176
1177 if (!wordsRemaining) {
1178 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1179 info->reg = GBADMARegisterClearEnable(info->reg);
1180 info->nextEvent = INT_MAX;
1181
1182 // Clear the enable bit in memory
1183 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1184 } else {
1185 info->nextCount = info->count;
1186 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1187 info->nextDest = info->dest;
1188 }
1189 GBAMemoryScheduleDMA(gba, number, info);
1190 }
1191 if (GBADMARegisterIsDoIRQ(info->reg)) {
1192 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1193 }
1194 } else {
1195 info->nextDest = dest;
1196 info->nextCount = wordsRemaining;
1197 }
1198 info->nextSource = source;
1199
1200 if (info->nextEvent != INT_MAX) {
1201 info->nextEvent += cycles;
1202 }
1203 cpu->cycles += cycles;
1204}
1205
1206void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
1207 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1208 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1209}
1210
1211void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
1212 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1213 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1214}
1215
1216uint32_t _popcount32(unsigned bits) {
1217 bits = bits - ((bits >> 1) & 0x55555555);
1218 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1219 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1220}