src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26
27static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
28static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
29static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
30
31enum {
32 DS7_SP_BASE = 0x380FD80,
33 DS7_SP_BASE_IRQ = 0x380FF80,
34 DS7_SP_BASE_SVC = 0x380FFC0,
35
36 DS9_SP_BASE = 0x3002F7C,
37 DS9_SP_BASE_IRQ = 0x3003F80,
38 DS9_SP_BASE_SVC = 0x3003FC0,
39};
40
41static void DSInit(void* cpu, struct mCPUComponent* component);
42
43static void DS7Reset(struct ARMCore* cpu);
44static void DS7TestIRQ(struct ARMCore* cpu);
45static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
46static void DS7ProcessEvents(struct ARMCore* cpu);
47
48static void DS9Reset(struct ARMCore* cpu);
49static void DS9TestIRQ(struct ARMCore* cpu);
50static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
51static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
52static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
53static void DS9ProcessEvents(struct ARMCore* cpu);
54
55static void DSProcessEvents(struct DSCommon* dscore);
56static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
57static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
58static void DSBreakpoint(struct ARMCore* cpu, int immediate);
59
60static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
61 UNUSED(cyclesLate);
62 struct DS* ds = context;
63 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
64 if (ds->activeCpu == ds->ds9.cpu) {
65 ds->activeCpu = ds->ds7.cpu;
66 ds->cycleDrift += cycles;
67 cycles = ds->cycleDrift >> 1;
68 timing = &ds->ds7.timing;
69 } else {
70 ds->activeCpu = ds->ds9.cpu;
71 ds->cycleDrift -= cycles << 1;
72 cycles = ds->cycleDrift + SLICE_CYCLES;
73 timing = &ds->ds9.timing;
74 }
75 mTimingSchedule(timing, &ds->slice, cycles);
76 ds->sliceStart = mTimingCurrentTime(timing);
77 ds->earlyExit = true;
78}
79
80static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
81 UNUSED(timing);
82 UNUSED(cyclesLate);
83 struct DS* ds = context;
84 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
85 int64_t numerator;
86 int64_t denominator;
87 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
88 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
89 bool max = false;
90 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
91 case 0:
92 numerator = (int64_t)(int32_t) numerator;
93 case 1:
94 case 3:
95 denominator = (int64_t)(int32_t) denominator;
96 break;
97 }
98 if (numerator == INT64_MIN) {
99 max = true;
100 }
101 if (!denominator) {
102 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
103 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
104 numerator >>= 63LL;
105 numerator = -numerator;
106 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
107 return;
108 }
109 if (denominator == -1LL && max) {
110 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
111 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
112 return;
113 }
114 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
115 int64_t result = numerator / denominator;
116 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
117 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
118 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
119}
120
121 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
122 UNUSED(timing);
123 UNUSED(cyclesLate);
124 struct DS* ds = context;
125 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
126 uint64_t param;
127 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
128 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
129 param &= 0xFFFFFFFFULL;
130 }
131
132 uint64_t result = 0;
133 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
134
135 // "bit" starts at the highest power of four <= the argument.
136 while (bit > param) {
137 bit >>= 2;
138 }
139
140 while (bit != 0) {
141 if (param >= param + bit) {
142 param -= param + bit;
143 param = (result >> 1) + bit;
144 } else {
145 param >>= 1;
146 }
147 bit >>= 2;
148 }
149 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
150}
151
152void DSCreate(struct DS* ds) {
153 ds->d.id = DS_COMPONENT_MAGIC;
154 ds->d.init = DSInit;
155 ds->d.deinit = NULL;
156 ds->ds7.p = ds;
157 ds->ds9.p = ds;
158 ds->ds7.cpu = NULL;
159 ds->ds9.cpu = NULL;
160 ds->ds7.ipc = &ds->ds9;
161 ds->ds9.ipc = &ds->ds7;
162}
163
164static void DSInit(void* cpu, struct mCPUComponent* component) {
165 struct DS* ds = (struct DS*) component;
166 struct ARMCore* core = cpu;
167 if (!ds->ds7.cpu) {
168 // The ARM7 must get initialized first
169 ds->ds7.cpu = core;
170 ds->debugger = 0;
171 ds->sync = 0;
172 return;
173 }
174 ds->ds9.cpu = cpu;
175 ds->activeCpu = NULL;
176
177 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
178
179 ds->slice.name = "DS CPU Time Slicing";
180 ds->slice.callback = _slice;
181 ds->slice.context = ds;
182 ds->slice.priority = UINT_MAX;
183
184 CircleBufferInit(&ds->ds7.fifo, 64);
185 CircleBufferInit(&ds->ds9.fifo, 64);
186
187 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
188 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
189 DSMemoryInit(ds);
190 DSDMAInit(ds);
191
192 DSVideoInit(&ds->video);
193 ds->video.p = ds;
194
195 ds->ds7.springIRQ = 0;
196 ds->ds9.springIRQ = 0;
197 DSTimerInit(ds);
198 ds->keySource = NULL;
199 ds->rtcSource = NULL;
200 ds->rumble = NULL;
201
202 ds->romVf = NULL;
203
204 ds->keyCallback = NULL;
205
206 ds->divEvent.name = "DS Hardware Divide";
207 ds->divEvent.callback = _divide;
208 ds->divEvent.context = ds;
209 ds->divEvent.priority = 0x50;
210
211 ds->sqrtEvent.name = "DS Hardware Sqrt";
212 ds->sqrtEvent.callback = _sqrt;
213 ds->sqrtEvent.context = ds;
214 ds->sqrtEvent.priority = 0x51;
215
216 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
217 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
218}
219
220void DSUnloadROM(struct DS* ds) {
221 if (ds->romVf) {
222 ds->romVf->close(ds->romVf);
223 ds->romVf = NULL;
224 }
225}
226
227void DSDestroy(struct DS* ds) {
228 CircleBufferDeinit(&ds->ds7.fifo);
229 CircleBufferDeinit(&ds->ds9.fifo);
230 DSUnloadROM(ds);
231 DSMemoryDeinit(ds);
232 mTimingDeinit(&ds->ds7.timing);
233 mTimingDeinit(&ds->ds9.timing);
234}
235
236void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
237 irqh->reset = DS7Reset;
238 irqh->processEvents = DS7ProcessEvents;
239 irqh->swi16 = DS7Swi16;
240 irqh->swi32 = DS7Swi32;
241 irqh->hitIllegal = DSIllegal;
242 irqh->readCPSR = DS7TestIRQ;
243 irqh->writeCP15 = NULL;
244 irqh->readCP15 = NULL;
245 irqh->hitStub = DSHitStub;
246 irqh->bkpt16 = DSBreakpoint;
247 irqh->bkpt32 = DSBreakpoint;
248}
249
250void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
251 irqh->reset = DS9Reset;
252 irqh->processEvents = DS9ProcessEvents;
253 irqh->swi16 = DS9Swi16;
254 irqh->swi32 = DS9Swi32;
255 irqh->hitIllegal = DSIllegal;
256 irqh->readCPSR = DS9TestIRQ;
257 irqh->writeCP15 = DS9WriteCP15;
258 irqh->readCP15 = DS9ReadCP15;
259 irqh->hitStub = DSHitStub;
260 irqh->bkpt16 = DSBreakpoint;
261 irqh->bkpt32 = DSBreakpoint;
262}
263
264void DS7Reset(struct ARMCore* cpu) {
265 ARMSetPrivilegeMode(cpu, MODE_IRQ);
266 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
267 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
268 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
269 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
270 cpu->gprs[ARM_SP] = DS7_SP_BASE;
271
272 struct DS* ds = (struct DS*) cpu->master;
273 mTimingClear(&ds->ds7.timing);
274 CircleBufferInit(&ds->ds7.fifo, 64);
275 DSMemoryReset(ds);
276 DSDMAReset(&ds->ds7);
277 DS7IOInit(ds);
278
279 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
280 if (header) {
281 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
282 DS7IOWrite32(ds, DS_REG_ROMCNT_LO, header->busTiming | 0x2700000);
283 // TODO: Error check
284 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
285 uint32_t base = header->arm7Base - DS_BASE_RAM;
286 uint32_t* basePointer = &ds->memory.ram[base >> 2];
287 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
288 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
289 }
290 cpu->gprs[12] = header->arm7Entry;
291 cpu->gprs[ARM_LR] = header->arm7Entry;
292 cpu->gprs[ARM_PC] = header->arm7Entry;
293 int currentCycles = 0;
294 ARM_WRITE_PC;
295
296 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
297 }
298}
299
300void DS9Reset(struct ARMCore* cpu) {
301 ARMSetPrivilegeMode(cpu, MODE_IRQ);
302 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
303 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
304 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
305 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
306 cpu->gprs[ARM_SP] = DS9_SP_BASE;
307
308 struct DS* ds = (struct DS*) cpu->master;
309 mTimingClear(&ds->ds9.timing);
310 CircleBufferInit(&ds->ds9.fifo, 64);
311 DSVideoReset(&ds->video);
312 DSDMAReset(&ds->ds9);
313 DS9IOInit(ds);
314
315 ds->activeCpu = cpu;
316 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
317 ds->cycleDrift = 0;
318 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
319
320 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
321 if (header) {
322 // TODO: Error check
323 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
324 uint32_t base = header->arm9Base - DS_BASE_RAM;
325 uint32_t* basePointer = &ds->memory.ram[base >> 2];
326 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
327 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
328 }
329 cpu->gprs[12] = header->arm9Entry;
330 cpu->gprs[ARM_LR] = header->arm9Entry;
331 cpu->gprs[ARM_PC] = header->arm9Entry;
332 int currentCycles = 0;
333 ARM_WRITE_PC;
334
335 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
336 }
337}
338
339static void DS7ProcessEvents(struct ARMCore* cpu) {
340 struct DS* ds = (struct DS*) cpu->master;
341 DSProcessEvents(&ds->ds7);
342}
343
344static void DS9ProcessEvents(struct ARMCore* cpu) {
345 struct DS* ds = (struct DS*) cpu->master;
346 DSProcessEvents(&ds->ds9);
347}
348
349static void DSProcessEvents(struct DSCommon* dscore) {
350 struct ARMCore* cpu = dscore->cpu;
351 struct DS* ds = dscore->p;
352 if (dscore->springIRQ && !cpu->cpsr.i) {
353 ARMRaiseIRQ(cpu);
354 dscore->springIRQ = 0;
355 }
356
357 int32_t nextEvent = cpu->nextEvent;
358 while (cpu->cycles >= nextEvent) {
359 int32_t cycles = cpu->cycles;
360
361 cpu->cycles = 0;
362 cpu->nextEvent = 0;
363
364#ifndef NDEBUG
365 if (cycles < 0) {
366 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
367 }
368#endif
369 nextEvent = cycles;
370 do {
371 nextEvent = mTimingTick(&dscore->timing, nextEvent);
372 } while (ds->cpuBlocked);
373
374 if (ds->earlyExit) {
375 ds->earlyExit = false;
376 break;
377 }
378
379 cpu->nextEvent = nextEvent;
380 if (cpu->halted) {
381 cpu->cycles = nextEvent;
382 }
383#ifndef NDEBUG
384 else if (nextEvent < 0) {
385 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
386 }
387#endif
388 }
389}
390
391void DSRunLoop(struct DS* ds) {
392 if (ds->activeCpu == ds->ds9.cpu) {
393 ARMv5RunLoop(ds->ds9.cpu);
394 } else {
395 ARMv4RunLoop(ds->ds7.cpu);
396 }
397}
398
399void DS7Step(struct DS* ds) {
400 int32_t pc = ds->ds7.cpu->gprs[ARM_PC];
401 do {
402 while (ds->activeCpu == ds->ds9.cpu) {
403 ARMv5RunLoop(ds->ds9.cpu);
404 }
405 ARMv4Run(ds->ds7.cpu);
406 } while (ds->ds7.cpu->halted || ds->ds7.cpu->gprs[ARM_PC] == pc);
407}
408
409void DS9Step(struct DS* ds) {
410 int32_t pc = ds->ds9.cpu->gprs[ARM_PC];
411 do {
412 while (ds->activeCpu == ds->ds7.cpu) {
413 ARMv4RunLoop(ds->ds7.cpu);
414 }
415 ARMv5Run(ds->ds9.cpu);
416 } while (ds->ds9.cpu->halted || ds->ds9.cpu->gprs[ARM_PC] == pc);
417}
418
419void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
420 ds->debugger = (struct ARMDebugger*) debugger->platform;
421 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
422 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
423 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
424 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
425}
426
427void DSDetachDebugger(struct DS* ds) {
428 ds->debugger = NULL;
429 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
430 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
431 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
432 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
433}
434
435bool DSLoadROM(struct DS* ds, struct VFile* vf) {
436 DSUnloadROM(ds);
437 ds->romVf = vf;
438 // TODO: error check
439 return true;
440}
441
442bool DSIsROM(struct VFile* vf) {
443 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
444 return false;
445 }
446 uint8_t signature[sizeof(DS_ROM_MAGIC)];
447 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
448 return false;
449 }
450 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
451}
452
453bool DSIsBIOS7(struct VFile* vf) {
454 size_t size = vf->size(vf);
455 void* data = NULL;
456 uint32_t crc;
457 if (size == DS7_SIZE_BIOS) {
458 data = vf->map(vf, size, MAP_READ);
459 }
460 if (!data) {
461 return false;
462 }
463 crc = doCrc32(data, size);
464 vf->unmap(vf, data, size);
465 return crc == DS7_BIOS_CHECKSUM;
466}
467
468bool DSIsBIOS9(struct VFile* vf) {
469 size_t size = vf->size(vf);
470 void* data = NULL;
471 uint32_t crc;
472 if (size == DS9_SIZE_BIOS) {
473 data = vf->map(vf, 0x1000, MAP_READ);
474 } else if (size == 0x1000) {
475 data = vf->map(vf, 0x1000, MAP_READ);
476 }
477 if (!data) {
478 return false;
479 }
480 crc = doCrc32(data, 0x1000);
481 vf->unmap(vf, data, 0x1000);
482 return crc == DS9_BIOS_CHECKSUM;
483}
484
485bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
486 size_t size = vf->size(vf);
487 void* data = NULL;
488 uint32_t crc;
489 if (size == DS7_SIZE_BIOS) {
490 data = vf->map(vf, size, MAP_READ);
491 } else if (size == 0x1000) {
492 data = calloc(DS9_SIZE_BIOS, 1);
493 vf->read(vf, data, size);
494 } else if (size == DS9_SIZE_BIOS) {
495 data = vf->map(vf, size, MAP_READ);
496 }
497 if (!data) {
498 return false;
499 }
500 crc = doCrc32(data, size);
501 if (crc == DS7_BIOS_CHECKSUM) {
502 ds->bios7Vf = vf;
503 ds->memory.bios7 = data;
504 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
505 } else if (crc == DS9_BIOS_CHECKSUM) {
506 ds->bios9Vf = vf;
507 ds->memory.bios9 = data;
508 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
509 } else {
510 mLOG(DS, WARN, "BIOS checksum incorrect");
511 vf->unmap(vf, data, size);
512 return false;
513 }
514 return true;
515}
516
517void DSGetGameCode(struct DS* ds, char* out) {
518 memset(out, 0, 8);
519 if (!ds->romVf) {
520 return;
521 }
522
523 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
524 // TODO: TWL-?
525 memcpy(out, "NTR-", 4);
526 memcpy(&out[4], &cart->id, 4);
527 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
528}
529
530void DSGetGameTitle(struct DS* ds, char* out) {
531 memset(out, 0, 12);
532 if (!ds->romVf) {
533 return;
534 }
535
536 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
537 memcpy(out, &cart->title, 12);
538 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
539}
540
541void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
542 struct DS* ds = (struct DS*) cpu->master;
543 if (ds->debugger) {
544 struct mDebuggerEntryInfo info = {
545 .address = _ARMPCAddress(cpu),
546 .opcode = opcode
547 };
548 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
549 }
550 // TODO: More sensible category?
551 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
552}
553
554void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
555 struct DS* ds = (struct DS*) cpu->master;
556 if ((opcode & 0xFFFF) == (redzoneInstruction & 0xFFFF)) {
557 int currentCycles = 0;
558 if (cpu->executionMode == MODE_THUMB) {
559 cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB * 2;
560 THUMB_WRITE_PC;
561 } else {
562 cpu->gprs[ARM_PC] -= WORD_SIZE_ARM * 2;
563 ARM_WRITE_PC;
564 }
565 } else if (ds->debugger) {
566 struct mDebuggerEntryInfo info = {
567 .address = _ARMPCAddress(cpu),
568 .opcode = opcode
569 };
570 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
571 } else {
572 ARMRaiseUndefined(cpu);
573 }
574}
575
576void DSBreakpoint(struct ARMCore* cpu, int immediate) {
577 struct DS* ds = (struct DS*) cpu->master;
578 if (immediate >= CPU_COMPONENT_MAX) {
579 return;
580 }
581 switch (immediate) {
582 case CPU_COMPONENT_DEBUGGER:
583 if (ds->debugger) {
584 struct mDebuggerEntryInfo info = {
585 .address = _ARMPCAddress(cpu)
586 };
587 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
588 }
589 break;
590 default:
591 break;
592 }
593}
594
595void DS7TestIRQ(struct ARMCore* cpu) {
596 struct DS* ds = (struct DS*) cpu->master;
597 if (!ds->memory.io7[DS_REG_IME >> 1]) {
598 return;
599 }
600 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
601 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
602 if (test) {
603 ds->ds7.springIRQ = test;
604 cpu->nextEvent = cpu->cycles;
605 }
606}
607
608void DS9TestIRQ(struct ARMCore* cpu) {
609 struct DS* ds = (struct DS*) cpu->master;
610 if (!ds->memory.io9[DS_REG_IME >> 1]) {
611 return;
612 }
613 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
614 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
615 if (test) {
616 ds->ds9.springIRQ = test;
617 cpu->nextEvent = cpu->cycles;
618 }
619}
620
621static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
622 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
623}
624
625static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
626 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
627 switch (opcode2) {
628 case 0:
629 cpu->cp15.r2.d = value;
630 break;
631 case 1:
632 cpu->cp15.r2.i = value;
633 break;
634 default:
635 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
636 break;
637 }
638}
639
640static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
641 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
642 switch (opcode2) {
643 case 0:
644 cpu->cp15.r3.d = value;
645 break;
646 default:
647 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
648 break;
649 }
650}
651
652static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
653 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
654}
655
656static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
657 cpu->cp15.r6.region[crm] = value;
658 uint32_t base = ARMProtectionGetBase(value) << 12;
659 uint32_t size = 2 << ARMProtectionGetSize(value);
660 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
661}
662
663static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
664 switch (crm) {
665 case 0:
666 if (opcode2 == 4) {
667 ARMHalt(cpu);
668 return;
669 }
670 break;
671 }
672 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
673}
674
675static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
676 uint32_t base = ARMTCMControlGetBase(value) << 12;
677 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
678 struct DS* ds = (struct DS*) cpu->master;
679 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
680 switch (opcode2) {
681 case 0:
682 cpu->cp15.r9.d = value;
683 ds->memory.dtcmBase = base;
684 ds->memory.dtcmSize = size;
685 break;
686 case 1:
687 cpu->cp15.r9.i = value;
688 ds->memory.itcmSize = size;
689 break;
690 default:
691 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
692 break;
693 }
694}
695
696void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
697 switch (crn) {
698 default:
699 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
700 break;
701 case 0:
702 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
703 ARMRaiseUndefined(cpu);
704 break;
705 case 1:
706 _writeSysControl(cpu, crm, opcode2, value);
707 break;
708 case 2:
709 _writeCacheControl(cpu, crm, opcode2, value);
710 break;
711 case 3:
712 _writeWriteBufferControl(cpu, crm, opcode2, value);
713 break;
714 case 5:
715 _writeAccessControl(cpu, crm, opcode2, value);
716 break;
717 case 6:
718 _writeRegionConfiguration(cpu, crm, opcode2, value);
719 break;
720 case 7:
721 _writeCache(cpu, crm, opcode2, value);
722 break;
723 case 9:
724 _writeTCMControl(cpu, crm, opcode2, value);
725 break;
726 }
727}
728
729static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
730 switch (opcode2) {
731 case 0:
732 return cpu->cp15.r9.d;
733 case 1:
734 return cpu->cp15.r9.i;
735 default:
736 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
737 return 0;
738 }
739}
740
741uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
742 switch (crn) {
743 default:
744 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
745 return 0;
746 case 9:
747 return _readTCMControl(cpu, crm, opcode2);
748 }
749}
750
751void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
752 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
753 ARMRaiseIRQ(cpu);
754 }
755}
756void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
757 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
758 ARMRaiseIRQ(cpu);
759 }
760}
761
762void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
763 if (irq < 16) {
764 io[DS_REG_IF_LO >> 1] |= 1 << irq;
765 } else {
766 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
767 }
768
769 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
770 cpu->halted = 0;
771 if (io[DS_REG_IME >> 1]) {
772 ARMRaiseIRQ(cpu);
773 }
774 }
775}
776
777void DSFrameStarted(struct DS* ds) {
778 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
779 if (callbacks && callbacks->videoFrameStarted) {
780 callbacks->videoFrameStarted(callbacks->context);
781 }
782}
783
784void DSFrameEnded(struct DS* ds) {
785 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
786 if (callbacks && callbacks->videoFrameEnded) {
787 callbacks->videoFrameEnded(callbacks->context);
788 }
789}