src/ds/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/memory.h>
7
8#include <mgba/internal/arm/macros.h>
9
10#include <mgba/internal/ds/ds.h>
11#include <mgba/internal/ds/io.h>
12#include <mgba-util/math.h>
13#include <mgba-util/memory.h>
14
15mLOG_DEFINE_CATEGORY(DS_MEM, "DS Memory", "ds.memory");
16
17static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
18const uint32_t redzoneInstruction = 0xE7F0DEF0;
19
20static const uint32_t _vramMask[9] = {
21 0x1FFFF,
22 0x1FFFF,
23 0x1FFFF,
24 0x1FFFF,
25 0x0FFFF,
26 0x03FFF,
27 0x03FFF,
28 0x07FFF,
29 0x03FFF
30};
31
32static void DS7SetActiveRegion(struct ARMCore* cpu, uint32_t region);
33static void DS9SetActiveRegion(struct ARMCore* cpu, uint32_t region);
34static int32_t DSMemoryStall(struct ARMCore* cpu, int32_t wait);
35
36static unsigned _selectVRAM(struct DSMemory* memory, uint32_t offset);
37
38static const char DS7_BASE_WAITSTATES[16] = { 0, 0, 8, 0, 0, 0, 0, 0 };
39static const char DS7_BASE_WAITSTATES_32[16] = { 0, 0, 9, 0, 0, 1, 1, 0 };
40static const char DS7_BASE_WAITSTATES_SEQ[16] = { 0, 0, 1, 0, 0, 0, 0, 0 };
41static const char DS7_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 2, 0, 0, 1, 1, 0 };
42
43static const char DS9_BASE_WAITSTATES[16] = { 0, 0, 2, 6, 6, 7, 7, 6 };
44static const char DS9_BASE_WAITSTATES_32[16] = { 0, 0, 4, 6, 6, 9, 9, 6 };
45static const char DS9_BASE_WAITSTATES_SEQ[16] = { 0, 0, 1, 1, 1, 2, 2, 1 };
46static const char DS9_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 2, 1, 1, 4, 4, 1 };
47
48void DSMemoryInit(struct DS* ds) {
49 struct ARMCore* arm7 = ds->ds7.cpu;
50 arm7->memory.load32 = DS7Load32;
51 arm7->memory.load16 = DS7Load16;
52 arm7->memory.load8 = DS7Load8;
53 arm7->memory.loadMultiple = DS7LoadMultiple;
54 arm7->memory.store32 = DS7Store32;
55 arm7->memory.store16 = DS7Store16;
56 arm7->memory.store8 = DS7Store8;
57 arm7->memory.storeMultiple = DS7StoreMultiple;
58 arm7->memory.stall = DSMemoryStall;
59
60 struct ARMCore* arm9 = ds->ds9.cpu;
61 arm9->memory.load32 = DS9Load32;
62 arm9->memory.load16 = DS9Load16;
63 arm9->memory.load8 = DS9Load8;
64 arm9->memory.loadMultiple = DS9LoadMultiple;
65 arm9->memory.store32 = DS9Store32;
66 arm9->memory.store16 = DS9Store16;
67 arm9->memory.store8 = DS9Store8;
68 arm9->memory.storeMultiple = DS9StoreMultiple;
69 arm9->memory.stall = DSMemoryStall;
70
71 int i;
72 for (i = 0; i < 8; ++i) {
73 // TODO: Formalize
74 ds->ds7.memory.waitstatesNonseq16[i] = DS7_BASE_WAITSTATES[i];
75 ds->ds7.memory.waitstatesSeq16[i] = DS7_BASE_WAITSTATES_SEQ[i];
76 ds->ds7.memory.waitstatesPrefetchNonseq16[i] = DS7_BASE_WAITSTATES[i];
77 ds->ds7.memory.waitstatesPrefetchSeq16[i] = DS7_BASE_WAITSTATES_SEQ[i];
78 ds->ds7.memory.waitstatesNonseq32[i] = DS7_BASE_WAITSTATES_32[i];
79 ds->ds7.memory.waitstatesSeq32[i] = DS7_BASE_WAITSTATES_SEQ_32[i];
80 ds->ds7.memory.waitstatesPrefetchNonseq32[i] = DS7_BASE_WAITSTATES_32[i];
81 ds->ds7.memory.waitstatesPrefetchSeq32[i] = DS7_BASE_WAITSTATES_SEQ_32[i];
82
83 ds->ds9.memory.waitstatesNonseq16[i] = DS9_BASE_WAITSTATES[i];
84 ds->ds9.memory.waitstatesSeq16[i] = DS9_BASE_WAITSTATES_SEQ[i];
85 ds->ds9.memory.waitstatesPrefetchNonseq16[i] = DS9_BASE_WAITSTATES[i];
86 ds->ds9.memory.waitstatesPrefetchSeq16[i] = DS9_BASE_WAITSTATES[i];
87 ds->ds9.memory.waitstatesNonseq32[i] = DS9_BASE_WAITSTATES_32[i];
88 ds->ds9.memory.waitstatesSeq32[i] = DS9_BASE_WAITSTATES_SEQ_32[i];
89 ds->ds9.memory.waitstatesPrefetchNonseq32[i] = DS9_BASE_WAITSTATES_32[i];
90 ds->ds9.memory.waitstatesPrefetchSeq32[i] = DS9_BASE_WAITSTATES_32[i];
91 }
92
93 ds->ds9.memory.waitstatesPrefetchNonseq16[2] = 0;
94 ds->ds9.memory.waitstatesPrefetchSeq16[2] = 0;
95 ds->ds9.memory.waitstatesPrefetchNonseq32[2] = 0;
96 ds->ds9.memory.waitstatesPrefetchSeq32[2] = 0;
97
98 for (; i < 256; ++i) {
99 ds->ds7.memory.waitstatesNonseq16[i] = 0;
100 ds->ds7.memory.waitstatesSeq16[i] = 0;
101 ds->ds7.memory.waitstatesNonseq32[i] = 0;
102 ds->ds7.memory.waitstatesSeq32[i] = 0;
103
104 ds->ds9.memory.waitstatesNonseq16[i] = 0;
105 ds->ds9.memory.waitstatesSeq16[i] = 0;
106 ds->ds9.memory.waitstatesNonseq32[i] = 0;
107 ds->ds9.memory.waitstatesSeq32[i] = 0;
108 }
109
110 ds->memory.bios7 = NULL;
111 ds->memory.bios9 = NULL;
112 ds->memory.wramBase = NULL;
113 ds->memory.wram7 = NULL;
114 ds->memory.ram = NULL;
115 ds->memory.itcm = NULL;
116 ds->memory.dtcm = NULL;
117 ds->memory.rom = NULL;
118
119 ds->ds7.memory.activeRegion = -1;
120 ds->ds9.memory.activeRegion = -1;
121 ds->ds7.memory.io = ds->memory.io7;
122 ds->ds9.memory.io = ds->memory.io9;
123
124 arm7->memory.activeRegion = 0;
125 arm7->memory.activeMask = 0;
126 arm7->memory.setActiveRegion = DS7SetActiveRegion;
127 arm7->memory.activeSeqCycles32 = 0;
128 arm7->memory.activeSeqCycles16 = 0;
129 arm7->memory.activeNonseqCycles32 = 0;
130 arm7->memory.activeNonseqCycles16 = 0;
131
132 arm9->memory.activeRegion = 0;
133 arm9->memory.activeMask = 0;
134 arm9->memory.setActiveRegion = DS9SetActiveRegion;
135 arm9->memory.activeSeqCycles32 = 0;
136 arm9->memory.activeSeqCycles16 = 0;
137 arm9->memory.activeNonseqCycles32 = 0;
138 arm9->memory.activeNonseqCycles16 = 0;
139}
140
141void DSMemoryDeinit(struct DS* ds) {
142 mappedMemoryFree(ds->memory.wram, DS_SIZE_WORKING_RAM);
143 mappedMemoryFree(ds->memory.wram7, DS7_SIZE_WORKING_RAM);
144 mappedMemoryFree(ds->memory.ram, DS_SIZE_RAM);
145 mappedMemoryFree(ds->memory.itcm, DS9_SIZE_ITCM);
146 mappedMemoryFree(ds->memory.dtcm, DS9_SIZE_DTCM);
147}
148
149void DSMemoryReset(struct DS* ds) {
150 if (ds->memory.wram) {
151 mappedMemoryFree(ds->memory.wramBase, DS_SIZE_WORKING_RAM * 2 + 12);
152 }
153 // XXX: This hack lets you roll over the end of the WRAM block without
154 // looping back to the beginning. It works by placing an undefined
155 // instruction in a redzone at the very beginning and end of the buffer.
156 // Using clever masking tricks, the ARM loop will mask the offset so that
157 // either the middle of the passed-in buffer is the actual buffer, and
158 // when the loop rolls over, it hits the redzone at the beginning, or the
159 // start of the passed-in buffer matches the actual buffer, causing the
160 // redzone at the end to be hit. This requires a lot of dead space in
161 // the middle, and a fake (too large) mask, but it is very fast.
162 ds->memory.wram = anonymousMemoryMap(DS_SIZE_WORKING_RAM * 2 + 12);
163 ds->memory.wram[0] = redzoneInstruction;
164 ds->memory.wram[1] = redzoneInstruction;
165 ds->memory.wram[2] = redzoneInstruction;
166 ds->memory.wram[DS_SIZE_WORKING_RAM >> 1] = redzoneInstruction;
167 ds->memory.wram[(DS_SIZE_WORKING_RAM >> 1) + 1] = redzoneInstruction;
168 ds->memory.wram[(DS_SIZE_WORKING_RAM >> 1) + 2] = redzoneInstruction;
169 ds->memory.wramBase = &ds->memory.wram[DS_SIZE_WORKING_RAM >> 2];
170
171 if (ds->memory.wram7) {
172 mappedMemoryFree(ds->memory.wram7, DS7_SIZE_WORKING_RAM);
173 }
174 ds->memory.wram7 = anonymousMemoryMap(DS7_SIZE_WORKING_RAM);
175
176 if (ds->memory.ram) {
177 mappedMemoryFree(ds->memory.ram, DS_SIZE_RAM);
178 }
179 ds->memory.ram = anonymousMemoryMap(DS_SIZE_RAM);
180
181 if (ds->memory.itcm) {
182 mappedMemoryFree(ds->memory.itcm, DS9_SIZE_ITCM);
183 }
184 ds->memory.itcm = anonymousMemoryMap(DS9_SIZE_ITCM);
185
186 if (ds->memory.dtcm) {
187 mappedMemoryFree(ds->memory.dtcm, DS9_SIZE_DTCM);
188 }
189 ds->memory.dtcm = anonymousMemoryMap(DS9_SIZE_DTCM);
190
191 memset(ds->ds7.memory.dma, 0, sizeof(ds->ds7.memory.dma));
192 memset(ds->ds9.memory.dma, 0, sizeof(ds->ds9.memory.dma));
193 ds->ds7.memory.activeDMA = -1;
194 ds->ds9.memory.activeDMA = -1;
195
196 // TODO: Correct size
197 ds->memory.wramSize7 = 0x8000;
198 ds->memory.wramBase7 = ds->memory.wram;
199 ds->memory.wramSize9 = 0;
200 ds->memory.wramBase9 = NULL;
201
202 ds->memory.slot1Owner = true;
203 ds->memory.slot2Owner = true;
204 ds->memory.slot1.savedataType = DS_SAVEDATA_AUTODETECT;
205 ds->ds7.memory.slot1Access = true;
206 ds->ds9.memory.slot1Access = false;
207
208 DSSPIReset(ds);
209 DSSlot1Reset(ds);
210
211 DSVideoConfigureVRAM(ds, 0, 0, 1);
212 DSVideoConfigureVRAM(ds, 1, 0, 1);
213 DSVideoConfigureVRAM(ds, 2, 0, 1);
214 DSVideoConfigureVRAM(ds, 3, 0, 1);
215 DSVideoConfigureVRAM(ds, 4, 0, 1);
216 DSVideoConfigureVRAM(ds, 5, 0, 1);
217 DSVideoConfigureVRAM(ds, 6, 0, 1);
218 DSVideoConfigureVRAM(ds, 7, 0, 1);
219 DSVideoConfigureVRAM(ds, 8, 0, 1);
220 DSConfigureWRAM(&ds->memory, 3);
221
222 if (!ds->memory.wram || !ds->memory.wram7 || !ds->memory.ram || !ds->memory.itcm || !ds->memory.dtcm) {
223 DSMemoryDeinit(ds);
224 mLOG(DS_MEM, FATAL, "Could not map memory");
225 }
226}
227
228static void DS7SetActiveRegion(struct ARMCore* cpu, uint32_t address) {
229 struct DS* ds = (struct DS*) cpu->master;
230 struct DSCoreMemory* memory = &ds->ds7.memory;
231
232 int newRegion = address >> DS_BASE_OFFSET;
233
234 memory->activeRegion = newRegion;
235 switch (newRegion) {
236 case DS_REGION_WORKING_RAM:
237 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
238 cpu->memory.activeRegion = ds->memory.wram7;
239 cpu->memory.activeMask = DS7_SIZE_WORKING_RAM - 1;
240 } else if (ds->memory.wramSize7 == DS_SIZE_WORKING_RAM) {
241 if (address & DS_SIZE_WORKING_RAM) {
242 cpu->memory.activeRegion = ds->memory.wram;
243 } else {
244 cpu->memory.activeRegion = ds->memory.wramBase;
245 }
246 cpu->memory.activeMask = (ds->memory.wramSize7 << 1) - 1;
247 } else {
248 cpu->memory.activeRegion = ds->memory.wramBase;
249 cpu->memory.activeMask = (ds->memory.wramSize7 - 1);
250 }
251 break;
252 case DS7_REGION_BIOS:
253 if (ds->memory.bios7) {
254 cpu->memory.activeRegion = ds->memory.bios7;
255 cpu->memory.activeMask = DS9_SIZE_BIOS - 1;
256 } else {
257 cpu->memory.activeRegion = _deadbeef;
258 cpu->memory.activeMask = 0;
259 }
260 break;
261 case DS_REGION_RAM:
262 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
263 cpu->memory.activeRegion = ds->memory.ram;
264 cpu->memory.activeMask = DS_SIZE_RAM - 1;
265 break;
266 }
267 goto jump_error;
268 case DS_REGION_VRAM:
269 if (address < 0x06040000 && ds->memory.vram7[(address & 0x3FFFF) >> 17]) {
270 // TODO: redzones
271 cpu->memory.activeRegion = (uint32_t*) ds->memory.vram7[(address & 0x3FFFF) >> 17];
272 cpu->memory.activeMask = 0x1FFFF;
273 break;
274 }
275 // Fall through
276 default:
277 jump_error:
278 memory->activeRegion = -1;
279 cpu->memory.activeRegion = _deadbeef;
280 cpu->memory.activeMask = 0;
281 mLOG(DS_MEM, FATAL, "Jumped to invalid address: %08X", address);
282 break;
283 }
284 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
285 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
286 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
287 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
288}
289
290uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
291 struct DS* ds = (struct DS*) cpu->master;
292 struct DSMemory* memory = &ds->memory;
293 uint32_t value = 0;
294 int wait = ds->ds7.memory.waitstatesNonseq32[address >> DS_BASE_OFFSET];
295
296 switch (address >> DS_BASE_OFFSET) {
297 case DS7_REGION_BIOS:
298 LOAD_32(value, address & (DS7_SIZE_BIOS - 4), memory->bios7);
299 break;
300 case DS_REGION_WORKING_RAM:
301 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
302 LOAD_32(value, address & (DS7_SIZE_WORKING_RAM - 4), memory->wram7);
303 } else {
304 LOAD_32(value, address & (ds->memory.wramSize7 - 4), memory->wramBase7);
305 }
306 break;
307 case DS_REGION_RAM:
308 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
309 LOAD_32(value, address & (DS_SIZE_RAM - 4), memory->ram);
310 break;
311 }
312 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
313 break;
314 case DS_REGION_IO:
315 value = DS7IORead32(ds, address & 0x00FFFFFC);
316 break;
317 case DS_REGION_VRAM:
318 if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
319 LOAD_32(value, address & 0x1FFFC, memory->vram7[(address & 0x3FFFF) >> 17]);
320 break;
321 }
322 // Fall through
323 default:
324 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
325 break;
326 }
327
328 if (cycleCounter) {
329 wait += 2;
330 *cycleCounter += wait;
331 }
332 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
333 int rotate = (address & 3) << 3;
334 return ROR(value, rotate);
335}
336
337uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
338 struct DS* ds = (struct DS*) cpu->master;
339 struct DSMemory* memory = &ds->memory;
340 uint32_t value = 0;
341 int wait = ds->ds7.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
342
343 switch (address >> DS_BASE_OFFSET) {
344 case DS7_REGION_BIOS:
345 LOAD_16(value, address & (DS7_SIZE_BIOS - 2), memory->bios7);
346 break;
347 case DS_REGION_WORKING_RAM:
348 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
349 LOAD_16(value, address & (DS7_SIZE_WORKING_RAM - 2), memory->wram7);
350 } else {
351 LOAD_16(value, address & (ds->memory.wramSize7 - 2), memory->wramBase7);
352 }
353 break;
354 case DS_REGION_RAM:
355 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
356 LOAD_16(value, address & (DS_SIZE_RAM - 1), memory->ram);
357 break;
358 }
359 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load16: %08X", address);
360 case DS_REGION_IO:
361 value = DS7IORead(ds, address & DS_OFFSET_MASK);
362 break;
363 case DS_REGION_VRAM:
364 if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
365 LOAD_16(value, address & 0x1FFFE, memory->vram7[(address & 0x3FFFF) >> 17]);
366 break;
367 }
368 // Fall through
369 default:
370 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load16: %08X", address);
371 break;
372 }
373
374 if (cycleCounter) {
375 wait += 2;
376 *cycleCounter += wait;
377 }
378 // Unaligned 16-bit loads are "unpredictable", TODO: See what DS does
379 int rotate = (address & 1) << 3;
380 return ROR(value, rotate);
381}
382
383uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
384 struct DS* ds = (struct DS*) cpu->master;
385 struct DSMemory* memory = &ds->memory;
386 uint32_t value = 0;
387 int wait = ds->ds7.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
388
389 switch (address >> DS_BASE_OFFSET) {
390 case DS_REGION_WORKING_RAM:
391 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
392 value = ((uint8_t*) memory->wram7)[address & (DS7_SIZE_WORKING_RAM - 1)];
393 } else {
394 value = ((uint8_t*) memory->wramBase7)[address & (ds->memory.wramSize7 - 1)];
395 }
396 break;
397 case DS_REGION_RAM:
398 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
399 value = ((uint8_t*) memory->ram)[address & (DS_SIZE_RAM - 1)];
400 break;
401 }
402 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load8: %08X", address);
403 break;
404 case DS_REGION_IO:
405 value = (DS7IORead(ds, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
406 break;
407 default:
408 mLOG(DS_MEM, STUB, "Unimplemented DS7 Load8: %08X", address);
409 break;
410 }
411
412 if (cycleCounter) {
413 wait += 2;
414 *cycleCounter += wait;
415 }
416 return value;
417}
418
419void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
420 struct DS* ds = (struct DS*) cpu->master;
421 struct DSMemory* memory = &ds->memory;
422 int wait = ds->ds7.memory.waitstatesNonseq32[address >> DS_BASE_OFFSET];
423
424 switch (address >> DS_BASE_OFFSET) {
425 case DS_REGION_WORKING_RAM:
426 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
427 STORE_32(value, address & (DS7_SIZE_WORKING_RAM - 4), memory->wram7);
428 } else {
429 STORE_32(value, address & (ds->memory.wramSize7 - 4), memory->wramBase7);
430 }
431 break;
432 case DS_REGION_RAM:
433 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
434 STORE_32(value, address & (DS_SIZE_RAM - 4), memory->ram);
435 break;
436 }
437 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store32: %08X:%08X", address, value);
438 break;
439 case DS_REGION_IO:
440 DS7IOWrite32(ds, address & DS_OFFSET_MASK, value);
441 break;
442 case DS_REGION_VRAM:
443 if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
444 STORE_32(value, address & 0x1FFFC, memory->vram7[(address & 0x3FFFF) >> 17]);
445 break;
446 }
447 // Fall through
448 default:
449 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store32: %08X:%08X", address, value);
450 break;
451 }
452
453 if (cycleCounter) {
454 ++wait;
455 *cycleCounter += wait;
456 }
457}
458
459void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
460 struct DS* ds = (struct DS*) cpu->master;
461 struct DSMemory* memory = &ds->memory;
462 int wait = ds->ds7.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
463
464 switch (address >> DS_BASE_OFFSET) {
465 case DS_REGION_WORKING_RAM:
466 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
467 STORE_16(value, address & (DS7_SIZE_WORKING_RAM - 2), memory->wram7);
468 } else {
469 STORE_16(value, address & (ds->memory.wramSize7 - 2), memory->wramBase7);
470 }
471 break;
472 case DS_REGION_RAM:
473 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
474 STORE_16(value, address & (DS_SIZE_RAM - 2), memory->ram);
475 break;
476 }
477 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store16: %08X:%04X", address, value);
478 break;
479 case DS_REGION_IO:
480 DS7IOWrite(ds, address & DS_OFFSET_MASK, value);
481 break;
482 case DS_REGION_VRAM:
483 if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
484 STORE_16(value, address & 0x1FFFE, memory->vram7[(address & 0x3FFFF) >> 17]);
485 break;
486 }
487 // Fall through
488 default:
489 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store16: %08X:%04X", address, value);
490 break;
491 }
492
493 if (cycleCounter) {
494 ++wait;
495 *cycleCounter += wait;
496 }
497}
498
499void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
500 struct DS* ds = (struct DS*) cpu->master;
501 struct DSMemory* memory = &ds->memory;
502 int wait = ds->ds7.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
503
504 switch (address >> DS_BASE_OFFSET) {
505 case DS_REGION_WORKING_RAM:
506 if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
507 ((uint8_t*) memory->wram7)[address & (DS7_SIZE_WORKING_RAM - 1)] = value;
508 } else {
509 ((uint8_t*) memory->wramBase7)[address & (ds->memory.wramSize7 - 1)] = value;
510 }
511 break;
512 case DS_REGION_RAM:
513 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
514 ((uint8_t*) memory->ram)[address & (DS_SIZE_RAM - 1)] = value;
515 break;
516 }
517 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store8: %08X:%02X", address, value);
518 case DS_REGION_IO:
519 DS7IOWrite8(ds, address & DS_OFFSET_MASK, value);
520 break;
521 default:
522 mLOG(DS_MEM, STUB, "Unimplemented DS7 Store8: %08X:%02X", address, value);
523 break;
524 }
525
526 if (cycleCounter) {
527 ++wait;
528 *cycleCounter += wait;
529 }
530}
531
532#define LDM_LOOP(LDM) \
533 for (i = 0; i < 16; i += 4) { \
534 if (UNLIKELY(mask & (1 << i))) { \
535 LDM; \
536 cpu->gprs[i] = value; \
537 ++wait; \
538 wait += ws32[address >> DS_BASE_OFFSET]; \
539 address += 4; \
540 } \
541 if (UNLIKELY(mask & (2 << i))) { \
542 LDM; \
543 cpu->gprs[i + 1] = value; \
544 ++wait; \
545 wait += ws32[address >> DS_BASE_OFFSET]; \
546 address += 4; \
547 } \
548 if (UNLIKELY(mask & (4 << i))) { \
549 LDM; \
550 cpu->gprs[i + 2] = value; \
551 ++wait; \
552 wait += ws32[address >> DS_BASE_OFFSET]; \
553 address += 4; \
554 } \
555 if (UNLIKELY(mask & (8 << i))) { \
556 LDM; \
557 cpu->gprs[i + 3] = value; \
558 ++wait; \
559 wait += ws32[address >> DS_BASE_OFFSET]; \
560 address += 4; \
561 } \
562 }
563
564#define STM_LOOP(STM) \
565 for (i = 0; i < 16; i += 4) { \
566 if (UNLIKELY(mask & (1 << i))) { \
567 value = cpu->gprs[i]; \
568 STM; \
569 ++wait; \
570 wait += ws32[address >> DS_BASE_OFFSET]; \
571 address += 4; \
572 } \
573 if (UNLIKELY(mask & (2 << i))) { \
574 value = cpu->gprs[i + 1]; \
575 STM; \
576 ++wait; \
577 wait += ws32[address >> DS_BASE_OFFSET]; \
578 address += 4; \
579 } \
580 if (UNLIKELY(mask & (4 << i))) { \
581 value = cpu->gprs[i + 2]; \
582 STM; \
583 ++wait; \
584 wait += ws32[address >> DS_BASE_OFFSET]; \
585 address += 4; \
586 } \
587 if (UNLIKELY(mask & (8 << i))) { \
588 value = cpu->gprs[i + 3]; \
589 STM; \
590 ++wait; \
591 wait += ws32[address >> DS_BASE_OFFSET]; \
592 address += 4; \
593 } \
594 }
595
596uint32_t DS7LoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
597 struct DS* ds = (struct DS*) cpu->master;
598 struct DSMemory* memory = &ds->memory;
599 char* ws32 = ds->ds7.memory.waitstatesNonseq32;
600 uint32_t value;
601 int wait = 0;
602
603 int i;
604 int offset = 4;
605 int popcount = 0;
606 if (direction & LSM_D) {
607 offset = -4;
608 popcount = popcount32(mask);
609 address -= (popcount << 2) - 4;
610 }
611
612 if (direction & LSM_B) {
613 address += offset;
614 }
615
616 uint32_t addressMisalign = address & 0x3;
617 address &= 0xFFFFFFFC;
618
619 switch (address >> DS_BASE_OFFSET) {
620 case DS_REGION_WORKING_RAM:
621 LDM_LOOP(if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
622 LOAD_32(value, address & (DS7_SIZE_WORKING_RAM - 1), memory->wram7);
623 } else {
624 LOAD_32(value, address & (ds->memory.wramSize7 - 1), memory->wramBase7);
625 });
626 break;
627 case DS_REGION_RAM:
628 LDM_LOOP(if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
629 LOAD_32(value, address & (DS_SIZE_RAM - 1), memory->ram);
630 } else {
631 mLOG(DS_MEM, STUB, "Unimplemented DS7 LDM: %08X", address);
632 });
633 break;
634 case DS_REGION_IO:
635 LDM_LOOP(value = DS7IORead32(ds, address));
636 break;
637 case DS_REGION_VRAM:
638 LDM_LOOP(if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
639 LOAD_32(value, address & 0x1FFFF, memory->vram7[(address & 0x3FFFF) >> 17]);
640 } else {
641 mLOG(DS_MEM, STUB, "Unimplemented DS7 LDM: %08X", address);
642 });
643 break;
644 default:
645 mLOG(DS_MEM, STUB, "Unimplemented DS7 LDM: %08X", address);
646 LDM_LOOP(value = 0);
647 }
648
649 if (cycleCounter) {
650 ++wait;
651 *cycleCounter += wait;
652 }
653
654 if (direction & LSM_B) {
655 address -= offset;
656 }
657
658 if (direction & LSM_D) {
659 address -= (popcount << 2) + 4;
660 }
661
662 return address | addressMisalign;
663}
664
665uint32_t DS7StoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
666 struct DS* ds = (struct DS*) cpu->master;
667 struct DSMemory* memory = &ds->memory;
668 char* ws32 = ds->ds7.memory.waitstatesNonseq32;
669 uint32_t value;
670 int wait = 0;
671
672 int i;
673 int offset = 4;
674 int popcount = 0;
675 if (direction & LSM_D) {
676 offset = -4;
677 popcount = popcount32(mask);
678 address -= (popcount << 2) - 4;
679 }
680
681 if (direction & LSM_B) {
682 address += offset;
683 }
684
685 uint32_t addressMisalign = address & 0x3;
686 address &= 0xFFFFFFFC;
687
688 switch (address >> DS_BASE_OFFSET) {
689 case DS_REGION_WORKING_RAM:
690 STM_LOOP(if (address >= DS7_BASE_WORKING_RAM || !ds->memory.wramSize7) {
691 STORE_32(value, address & (DS7_SIZE_WORKING_RAM - 1), memory->wram7);
692 } else {
693 STORE_32(value, address & (ds->memory.wramSize7 - 1), memory->wramBase7);
694 });
695 break;
696 case DS_REGION_RAM:
697 STM_LOOP(if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
698 STORE_32(value, address & (DS_SIZE_RAM - 1), memory->ram);
699 } else {
700 mLOG(DS_MEM, STUB, "Unimplemented DS9 STM: %08X", address);
701 });
702 break;
703 case DS_REGION_VRAM:
704 STM_LOOP(if (address < 0x06040000 && memory->vram7[(address & 0x3FFFF) >> 17]) {
705 STORE_32(value, address & 0x1FFFF, memory->vram7[(address & 0x3FFFF) >> 17]);
706 } else {
707 mLOG(DS_MEM, STUB, "Unimplemented DS7 STM: %08X", address);
708 });
709 break;
710 default:
711 mLOG(DS_MEM, STUB, "Unimplemented DS9 STM: %08X", address);
712 STM_LOOP();
713 break;
714 }
715
716 if (cycleCounter) {
717 *cycleCounter += wait;
718 }
719
720 if (direction & LSM_B) {
721 address -= offset;
722 }
723
724 if (direction & LSM_D) {
725 address -= (popcount << 2) + 4;
726 }
727
728 return address | addressMisalign;
729}
730
731static void DS9SetActiveRegion(struct ARMCore* cpu, uint32_t address) {
732 struct DS* ds = (struct DS*) cpu->master;
733 struct DSCoreMemory* memory = &ds->ds9.memory;
734
735 int newRegion = address >> DS_BASE_OFFSET;
736
737 memory->activeRegion = newRegion;
738 switch (newRegion) {
739 case DS9_REGION_ITCM:
740 case DS9_REGION_ITCM_MIRROR:
741 if (address < ds->memory.itcmSize) {
742 cpu->memory.activeRegion = ds->memory.itcm;
743 cpu->memory.activeMask = DS9_SIZE_ITCM - 1;
744 break;
745 }
746 goto jump_error;
747 case DS_REGION_RAM:
748 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
749 cpu->memory.activeRegion = ds->memory.ram;
750 cpu->memory.activeMask = DS_SIZE_RAM - 1;
751 break;
752 }
753 goto jump_error;
754 case DS9_REGION_BIOS:
755 // TODO: Mask properly
756 if (ds->memory.bios9) {
757 cpu->memory.activeRegion = ds->memory.bios9;
758 cpu->memory.activeMask = DS9_SIZE_BIOS - 1;
759 } else {
760 cpu->memory.activeRegion = _deadbeef;
761 cpu->memory.activeMask = 0;
762 }
763 cpu->memory.activeSeqCycles32 = 0;
764 cpu->memory.activeSeqCycles16 = 0;
765 cpu->memory.activeNonseqCycles32 = 0;
766 cpu->memory.activeNonseqCycles16 = 0;
767 return;
768 default:
769 jump_error:
770 memory->activeRegion = -1;
771 cpu->memory.activeRegion = _deadbeef;
772 cpu->memory.activeMask = 0;
773 mLOG(DS_MEM, FATAL, "Jumped to invalid address: %08X", address);
774 return;
775 }
776 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
777 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
778 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
779 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
780}
781
782uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
783 struct DS* ds = (struct DS*) cpu->master;
784 struct DSMemory* memory = &ds->memory;
785 uint32_t value = 0;
786 int wait = ds->ds9.memory.waitstatesNonseq32[address >> DS_BASE_OFFSET];
787
788 switch (address >> DS_BASE_OFFSET) {
789 case DS9_REGION_ITCM:
790 case DS9_REGION_ITCM_MIRROR:
791 if (address < memory->itcmSize) {
792 LOAD_32(value, address & (DS9_SIZE_ITCM - 4), memory->itcm);
793 break;
794 }
795 mLOG(DS_MEM, STUB, "Bad DS9 Load32: %08X", address);
796 break;
797 case DS_REGION_WORKING_RAM:
798 if (ds->memory.wramSize9) {
799 LOAD_32(value, address & (ds->memory.wramSize9 - 4), memory->wramBase9);
800 break;
801 }
802 mLOG(DS_MEM, STUB, "Bad DS9 Load32: %08X", address);
803 break;
804 case DS_REGION_RAM:
805 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
806 LOAD_32(value, address & (DS9_SIZE_DTCM - 4), memory->dtcm);
807 break;
808 }
809 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
810 LOAD_32(value, address & (DS_SIZE_RAM - 4), memory->ram);
811 break;
812 }
813 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load32: %08X", address);
814 break;
815 case DS_REGION_IO:
816 value = DS9IORead32(ds, address & 0x00FFFFFC);
817 break;
818 case DS9_REGION_PALETTE_RAM:
819 LOAD_32(value, address & (DS9_SIZE_PALETTE_RAM - 4), ds->video.palette);
820 break;
821 case DS_REGION_VRAM: {
822 unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
823 int i = 0;
824 for (i = 0; i < 9; ++i) {
825 if (mask & (1 << i)) {
826 uint32_t newValue;
827 LOAD_32(newValue, address & _vramMask[i], memory->vramBank[i]);
828 value |= newValue;
829 }
830 }
831 break;
832 }
833 case DS9_REGION_OAM:
834 LOAD_32(value, address & (DS9_SIZE_OAM - 4), ds->video.oam.raw);
835 break;
836 case DS9_REGION_BIOS:
837 // TODO: Fix undersized BIOS
838 // TODO: Fix masking
839 LOAD_32(value, address & (DS9_SIZE_BIOS - 4), memory->bios9);
840 break;
841 default:
842 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
843 LOAD_32(value, address & (DS9_SIZE_DTCM - 4), memory->dtcm);
844 break;
845 }
846 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load32: %08X", address);
847 break;
848 }
849
850 if (cycleCounter) {
851 wait += 2;
852 *cycleCounter += wait;
853 }
854 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
855 int rotate = (address & 3) << 3;
856 return ROR(value, rotate);
857}
858
859uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
860 struct DS* ds = (struct DS*) cpu->master;
861 struct DSMemory* memory = &ds->memory;
862 uint32_t value = 0;
863 int wait = ds->ds9.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
864
865 switch (address >> DS_BASE_OFFSET) {
866 case DS9_REGION_ITCM:
867 case DS9_REGION_ITCM_MIRROR:
868 if (address < memory->itcmSize) {
869 LOAD_16(value, address & (DS9_SIZE_ITCM - 2), memory->itcm);
870 break;
871 }
872 mLOG(DS_MEM, STUB, "Bad DS9 Load16: %08X", address);
873 break;
874 case DS_REGION_WORKING_RAM:
875 if (ds->memory.wramSize9) {
876 LOAD_16(value, address & (ds->memory.wramSize9 - 2), memory->wramBase9);
877 break;
878 }
879 mLOG(DS_MEM, STUB, "Bad DS9 Load16: %08X", address);
880 break;
881 case DS_REGION_RAM:
882 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
883 LOAD_16(value, address & (DS9_SIZE_DTCM - 2), memory->dtcm);
884 break;
885 }
886 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
887 LOAD_16(value, address & (DS_SIZE_RAM - 2), memory->ram);
888 break;
889 }
890 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load16: %08X", address);
891 case DS_REGION_IO:
892 value = DS9IORead(ds, address & DS_OFFSET_MASK);
893 break;
894 case DS9_REGION_PALETTE_RAM:
895 LOAD_16(value, address & (DS9_SIZE_PALETTE_RAM - 2), ds->video.palette);
896 break;
897 case DS_REGION_VRAM: {
898 unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
899 int i = 0;
900 for (i = 0; i < 9; ++i) {
901 if (mask & (1 << i)) {
902 uint32_t newValue;
903 LOAD_16(newValue, address & _vramMask[i], memory->vramBank[i]);
904 value |= newValue;
905 }
906 }
907 break;
908 }
909 case DS9_REGION_OAM:
910 LOAD_16(value, address & (DS9_SIZE_OAM - 2), ds->video.oam.raw);
911 break;
912 case DS9_REGION_BIOS:
913 // TODO: Fix undersized BIOS
914 // TODO: Fix masking
915 LOAD_16(value, address & (DS9_SIZE_BIOS - 2), memory->bios9);
916 break;
917 default:
918 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
919 LOAD_16(value, address & (DS9_SIZE_DTCM - 2), memory->dtcm);
920 break;
921 }
922 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load16: %08X", address);
923 break;
924 }
925
926 if (cycleCounter) {
927 wait += 2;
928 *cycleCounter += wait;
929 }
930 // Unaligned 16-bit loads are "unpredictable", TODO: See what DS does
931 int rotate = (address & 1) << 3;
932 return ROR(value, rotate);
933}
934
935uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
936 struct DS* ds = (struct DS*) cpu->master;
937 struct DSMemory* memory = &ds->memory;
938 uint32_t value = 0;
939 int wait = ds->ds9.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
940
941 switch (address >> DS_BASE_OFFSET) {
942 case DS9_REGION_ITCM:
943 case DS9_REGION_ITCM_MIRROR:
944 if (address < memory->itcmSize) {
945 value = ((uint8_t*) memory->itcm)[address & (DS9_SIZE_ITCM - 1)];
946 break;
947 }
948 mLOG(DS_MEM, STUB, "Bad DS9 Load8: %08X", address);
949 break;
950 case DS_REGION_WORKING_RAM:
951 if (ds->memory.wramSize9) {
952 value = ((uint8_t*) memory->wramBase9)[address & (memory->wramSize9 - 1)];
953 break;
954 }
955 mLOG(DS_MEM, STUB, "Bad DS9 Load8: %08X", address);
956 break;
957 case DS_REGION_RAM:
958 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
959 value = ((uint8_t*) memory->dtcm)[address & (DS9_SIZE_DTCM - 1)];
960 break;
961 }
962 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
963 value = ((uint8_t*) memory->ram)[address & (DS_SIZE_RAM - 1)];
964 break;
965 }
966 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load8: %08X", address);
967 case DS_REGION_IO:
968 value = (DS9IORead(ds, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
969 break;
970 case DS_REGION_VRAM: {
971 unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
972 int i = 0;
973 for (i = 0; i < 9; ++i) {
974 if (mask & (1 << i)) {
975 value |= ((uint8_t*) memory->vramBank[i])[address & _vramMask[i]];
976 }
977 }
978 break;
979 }
980 case DS9_REGION_BIOS:
981 // TODO: Fix undersized BIOS
982 // TODO: Fix masking
983 value = ((uint8_t*) memory->bios9)[address & (DS9_SIZE_BIOS - 1)];
984 break;
985 default:
986 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
987 value = ((uint8_t*) memory->dtcm)[address & (DS9_SIZE_DTCM - 1)];
988 break;
989 }
990 mLOG(DS_MEM, STUB, "Unimplemented DS9 Load8: %08X", address);
991 break;
992 }
993
994 if (cycleCounter) {
995 wait += 2;
996 *cycleCounter += wait;
997 }
998 return value;
999}
1000
1001void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
1002 struct DS* ds = (struct DS*) cpu->master;
1003 struct DSMemory* memory = &ds->memory;
1004 int wait = ds->ds9.memory.waitstatesNonseq32[address >> DS_BASE_OFFSET];
1005
1006 switch (address >> DS_BASE_OFFSET) {
1007 case DS9_REGION_ITCM:
1008 case DS9_REGION_ITCM_MIRROR:
1009 if (address < memory->itcmSize) {
1010 STORE_32(value, address & (DS9_SIZE_ITCM - 4), memory->itcm);
1011 break;
1012 }
1013 mLOG(DS_MEM, STUB, "Bad DS9 Store32: %08X:%08X", address, value);
1014 break;
1015 case DS_REGION_WORKING_RAM:
1016 if (ds->memory.wramSize9) {
1017 STORE_32(value, address & (ds->memory.wramSize9 - 4), memory->wramBase9);
1018 break;
1019 }
1020 mLOG(DS_MEM, STUB, "Bad DS9 Store32: %08X:%08X", address, value);
1021 break;
1022 case DS_REGION_RAM:
1023 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1024 STORE_32(value, address & (DS9_SIZE_DTCM - 4), memory->dtcm);
1025 break;
1026 }
1027 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
1028 STORE_32(value, address & (DS_SIZE_RAM - 4), memory->ram);
1029 break;
1030 }
1031 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store32: %08X:%08X", address, value);
1032 break;
1033 case DS_REGION_IO:
1034 DS9IOWrite32(ds, address & DS_OFFSET_MASK, value);
1035 break;
1036 case DS9_REGION_PALETTE_RAM:
1037 STORE_32(value, address & (DS9_SIZE_PALETTE_RAM - 4), ds->video.palette);
1038 ds->video.renderer->writePalette(ds->video.renderer, (address & (DS9_SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
1039 ds->video.renderer->writePalette(ds->video.renderer, address & (DS9_SIZE_PALETTE_RAM - 4), value);
1040 break;
1041 case DS_REGION_VRAM: {
1042 unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
1043 int i = 0;
1044 for (i = 0; i < 9; ++i) {
1045 if (mask & (1 << i)) {
1046 STORE_32(value, address & _vramMask[i], memory->vramBank[i]);
1047 }
1048 }
1049 break;
1050 }
1051 case DS9_REGION_OAM:
1052 STORE_32(value, address & (DS9_SIZE_OAM - 4), ds->video.oam.raw);
1053 ds->video.renderer->writeOAM(ds->video.renderer, (address & (DS9_SIZE_OAM - 4)) >> 1);
1054 ds->video.renderer->writeOAM(ds->video.renderer, ((address & (DS9_SIZE_OAM - 4)) >> 1) + 1);
1055 break;
1056 default:
1057 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1058 STORE_32(value, address & (DS9_SIZE_DTCM - 4), memory->dtcm);
1059 break;
1060 }
1061 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store32: %08X:%08X", address, value);
1062 break;
1063 }
1064
1065 if (cycleCounter) {
1066 ++wait;
1067 *cycleCounter += wait;
1068 }
1069}
1070
1071void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
1072 struct DS* ds = (struct DS*) cpu->master;
1073 struct DSMemory* memory = &ds->memory;
1074 int wait = ds->ds9.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
1075
1076 switch (address >> DS_BASE_OFFSET) {
1077 case DS9_REGION_ITCM:
1078 case DS9_REGION_ITCM_MIRROR:
1079 if (address < memory->itcmSize) {
1080 STORE_16(value, address & (DS9_SIZE_ITCM - 2), memory->itcm);
1081 break;
1082 }
1083 mLOG(DS_MEM, STUB, "Bad DS9 Store16: %08X:%04X", address, value);
1084 break;
1085 case DS_REGION_WORKING_RAM:
1086 if (ds->memory.wramSize9) {
1087 STORE_16(value, address & (ds->memory.wramSize9 - 2), memory->wramBase9);
1088 break;
1089 }
1090 mLOG(DS_MEM, STUB, "Bad DS9 Store16: %08X:%04X", address, value);
1091 break;
1092 case DS_REGION_RAM:
1093 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1094 STORE_16(value, address & (DS9_SIZE_DTCM - 2), memory->dtcm);
1095 break;
1096 }
1097 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
1098 STORE_16(value, address & (DS_SIZE_RAM - 2), memory->ram);
1099 break;
1100 }
1101 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store16: %08X:%04X", address, value);
1102 break;
1103 case DS_REGION_IO:
1104 DS9IOWrite(ds, address & DS_OFFSET_MASK, value);
1105 break;
1106 case DS9_REGION_PALETTE_RAM:
1107 STORE_16(value, address & (DS9_SIZE_PALETTE_RAM - 2), ds->video.palette);
1108 ds->video.renderer->writePalette(ds->video.renderer, address & (DS9_SIZE_PALETTE_RAM - 2), value);
1109 break;
1110 case DS_REGION_VRAM: {
1111 unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
1112 int i = 0;
1113 for (i = 0; i < 9; ++i) {
1114 if (mask & (1 << i)) {
1115 STORE_16(value, address & _vramMask[i], memory->vramBank[i]);
1116 }
1117 }
1118 break;
1119 }
1120 case DS9_REGION_OAM:
1121 STORE_16(value, address & (DS9_SIZE_OAM - 2), ds->video.oam.raw);
1122 ds->video.renderer->writeOAM(ds->video.renderer, (address & (DS9_SIZE_OAM - 2)) >> 1);
1123 break;
1124 default:
1125 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1126 STORE_16(value, address & (DS9_SIZE_DTCM - 1), memory->dtcm);
1127 break;
1128 }
1129 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store16: %08X:%04X", address, value);
1130 break;
1131 }
1132
1133 if (cycleCounter) {
1134 ++wait;
1135 *cycleCounter += wait;
1136 }
1137}
1138
1139void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
1140 struct DS* ds = (struct DS*) cpu->master;
1141 struct DSMemory* memory = &ds->memory;
1142 int wait = ds->ds9.memory.waitstatesNonseq16[address >> DS_BASE_OFFSET];
1143
1144 switch (address >> DS_BASE_OFFSET) {
1145 case DS9_REGION_ITCM:
1146 case DS9_REGION_ITCM_MIRROR:
1147 if (address < memory->itcmSize) {
1148 ((uint8_t*) memory->itcm)[address & (DS9_SIZE_ITCM - 1)] = value;
1149 break;
1150 }
1151 mLOG(DS_MEM, STUB, "Bad DS9 Store8: %08X:%02X", address, value);
1152 break;
1153 case DS_REGION_WORKING_RAM:
1154 if (ds->memory.wramSize9) {
1155 ((uint8_t*) memory->wramBase9)[address & (ds->memory.wramSize9 - 1)] = value;
1156 break;
1157 }
1158 mLOG(DS_MEM, STUB, "Bad DS9 Store8: %08X:%02X", address, value);
1159 break;
1160 case DS_REGION_RAM:
1161 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1162 ((uint8_t*) memory->dtcm)[address & (DS9_SIZE_DTCM - 1)] = value;
1163 break;
1164 }
1165 if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
1166 ((uint8_t*) memory->ram)[address & (DS_SIZE_RAM - 1)] = value;
1167 break;
1168 }
1169 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store8: %08X:%02X", address, value);
1170 case DS_REGION_IO:
1171 DS9IOWrite8(ds, address & DS_OFFSET_MASK, value);
1172 break;
1173 default:
1174 if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1175 ((uint8_t*) memory->dtcm)[address & (DS9_SIZE_DTCM - 1)] = value;
1176 break;
1177 }
1178 mLOG(DS_MEM, STUB, "Unimplemented DS9 Store8: %08X:%02X", address, value);
1179 break;
1180 }
1181
1182 if (cycleCounter) {
1183 ++wait;
1184 *cycleCounter += wait;
1185 }
1186}
1187
1188uint32_t DS9LoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1189 struct DS* ds = (struct DS*) cpu->master;
1190 struct DSMemory* memory = &ds->memory;
1191 char* ws32 = ds->ds9.memory.waitstatesNonseq32;
1192 uint32_t value;
1193 int wait = 0;
1194
1195 int i;
1196 int offset = 4;
1197 int popcount = 0;
1198 if (direction & LSM_D) {
1199 offset = -4;
1200 popcount = popcount32(mask);
1201 address -= (popcount << 2) - 4;
1202 }
1203
1204 if (direction & LSM_B) {
1205 address += offset;
1206 }
1207
1208 uint32_t addressMisalign = address & 0x3;
1209 address &= 0xFFFFFFFC;
1210
1211 switch (address >> DS_BASE_OFFSET) {
1212 case DS9_REGION_ITCM:
1213 case DS9_REGION_ITCM_MIRROR:
1214 LDM_LOOP(if (address < memory->itcmSize) {
1215 LOAD_32(value, address & (DS9_SIZE_ITCM - 1), memory->itcm);
1216 } else {
1217 mLOG(DS_MEM, STUB, "Bad DS9 LDM: %08X:%08X", address, value);
1218 });
1219 break;
1220 case DS_REGION_WORKING_RAM:
1221 LDM_LOOP(if (ds->memory.wramSize9) {
1222 LOAD_32(value, address & (ds->memory.wramSize9 - 4), memory->wramBase9);
1223 } else {
1224 mLOG(DS_MEM, STUB, "Bad DS9 LDM: %08X", address);
1225 });
1226 break;
1227 case DS_REGION_RAM:
1228 LDM_LOOP(if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1229 LOAD_32(value, address & (DS9_SIZE_DTCM - 1), memory->dtcm);
1230 } else if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
1231 LOAD_32(value, address & (DS_SIZE_RAM - 1), memory->ram);
1232 } else {
1233 mLOG(DS_MEM, STUB, "Unimplemented DS9 LDM: %08X", address);
1234 });
1235 break;
1236 case DS_REGION_IO:
1237 LDM_LOOP(value = DS9IORead32(ds, address));
1238 break;
1239 case DS9_REGION_PALETTE_RAM:
1240 LDM_LOOP(LOAD_32(value, address & (DS9_SIZE_PALETTE_RAM - 1), ds->video.palette));
1241 break;
1242 case DS_REGION_VRAM:
1243 LDM_LOOP(unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
1244 value = 0;
1245 int i = 0;
1246 for (i = 0; i < 9; ++i) {
1247 if (mask & (1 << i)) {
1248 uint32_t newValue;
1249 LOAD_32(newValue, address & _vramMask[i], memory->vramBank[i]);
1250 value |= newValue;
1251 }
1252 });
1253 break;
1254 case DS9_REGION_OAM:
1255 LDM_LOOP(LOAD_32(value, address & (DS9_SIZE_OAM - 1), ds->video.oam.raw));
1256 break;
1257 default:
1258 LDM_LOOP(if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1259 LOAD_32(value, address & (DS9_SIZE_DTCM - 1), memory->dtcm);
1260 } else {
1261 mLOG(DS_MEM, STUB, "Unimplemented DS9 LDM: %08X", address);
1262 });
1263 break;
1264 }
1265
1266 if (cycleCounter) {
1267 ++wait;
1268 *cycleCounter += wait;
1269 }
1270
1271 if (direction & LSM_B) {
1272 address -= offset;
1273 }
1274
1275 if (direction & LSM_D) {
1276 address -= (popcount << 2) + 4;
1277 }
1278
1279 return address | addressMisalign;
1280}
1281
1282
1283uint32_t DS9StoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1284 struct DS* ds = (struct DS*) cpu->master;
1285 struct DSMemory* memory = &ds->memory;
1286 char* ws32 = ds->ds9.memory.waitstatesNonseq32;
1287 uint32_t value;
1288 int wait = 0;
1289
1290 int i;
1291 int offset = 4;
1292 int popcount = 0;
1293 if (direction & LSM_D) {
1294 offset = -4;
1295 popcount = popcount32(mask);
1296 address -= (popcount << 2) - 4;
1297 }
1298
1299 if (direction & LSM_B) {
1300 address += offset;
1301 }
1302
1303 uint32_t addressMisalign = address & 0x3;
1304 address &= 0xFFFFFFFC;
1305
1306 switch (address >> DS_BASE_OFFSET) {
1307 case DS9_REGION_ITCM:
1308 case DS9_REGION_ITCM_MIRROR:
1309 STM_LOOP(if (address < memory->itcmSize) {
1310 STORE_32(value, address & (DS9_SIZE_ITCM - 1), memory->itcm);
1311 } else {
1312 mLOG(DS_MEM, STUB, "Bad DS9 STM: %08X:%08X", address, value);
1313 });
1314 break;
1315 case DS_REGION_WORKING_RAM:
1316 STM_LOOP(if (ds->memory.wramSize9) {
1317 STORE_32(value, address & (ds->memory.wramSize9 - 4), memory->wramBase9);
1318 } else {
1319 mLOG(DS_MEM, STUB, "Bad DS9 STM: %08X", address);
1320 });
1321 break;
1322 case DS_REGION_RAM:
1323 STM_LOOP(if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1324 STORE_32(value, address & (DS9_SIZE_DTCM - 1), memory->dtcm);
1325 } else if ((address & (DS_SIZE_RAM - 1)) < DS_SIZE_RAM) {
1326 STORE_32(value, address & (DS_SIZE_RAM - 1), memory->ram);
1327 } else {
1328 mLOG(DS_MEM, STUB, "Unimplemented DS9 STM: %08X", address);
1329 });
1330 break;
1331 case DS_REGION_IO:
1332 STM_LOOP(DS9IOWrite32(ds, address & DS_OFFSET_MASK, value));
1333 break;
1334 case DS9_REGION_PALETTE_RAM:
1335 STM_LOOP(STORE_32(value, address & (DS9_SIZE_PALETTE_RAM - 1), ds->video.palette);
1336 ds->video.renderer->writePalette(ds->video.renderer, (address & (DS9_SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
1337 ds->video.renderer->writePalette(ds->video.renderer, address & (DS9_SIZE_PALETTE_RAM - 4), value));
1338 break;
1339 case DS_REGION_VRAM:
1340 STM_LOOP(unsigned mask = _selectVRAM(memory, address >> DS_VRAM_OFFSET);
1341 int i = 0;
1342 for (i = 0; i < 9; ++i) {
1343 if (mask & (1 << i)) {
1344 STORE_32(value, address & _vramMask[i], memory->vramBank[i]);
1345 }
1346 });
1347 break;
1348 case DS9_REGION_OAM:
1349 STM_LOOP(STORE_32(value, address & (DS9_SIZE_OAM - 1), ds->video.oam.raw);
1350 ds->video.renderer->writeOAM(ds->video.renderer, (address & (DS9_SIZE_OAM - 4)) >> 1);
1351 ds->video.renderer->writeOAM(ds->video.renderer, ((address & (DS9_SIZE_OAM - 4)) >> 1) + 1));
1352 break;
1353 default:
1354 STM_LOOP(if ((address & ~(DS9_SIZE_DTCM - 1)) == memory->dtcmBase) {
1355 STORE_32(value, address & (DS9_SIZE_DTCM - 1), memory->dtcm);
1356 } else {
1357 mLOG(DS_MEM, STUB, "Unimplemented DS9 STM: %08X", address);
1358 });
1359 break;
1360 }
1361
1362 if (cycleCounter) {
1363 *cycleCounter += wait;
1364 }
1365
1366 if (direction & LSM_B) {
1367 address -= offset;
1368 }
1369
1370 if (direction & LSM_D) {
1371 address -= (popcount << 2) + 4;
1372 }
1373
1374 return address | addressMisalign;
1375}
1376
1377int32_t DSMemoryStall(struct ARMCore* cpu, int32_t wait) {
1378 return wait;
1379}
1380
1381void DSConfigureWRAM(struct DSMemory* memory, uint8_t config) {
1382 switch (config & 3) {
1383 case 0:
1384 memory->wramSize7 = 0;
1385 memory->wramBase7 = NULL;
1386 memory->wramSize9 = DS_SIZE_WORKING_RAM;
1387 memory->wramBase9 = memory->wramBase;
1388 break;
1389 case 1:
1390 memory->wramSize7 = DS_SIZE_WORKING_RAM >> 1;
1391 memory->wramBase7 = memory->wram;
1392 memory->wramSize9 = DS_SIZE_WORKING_RAM >> 1;
1393 memory->wramBase9 = &memory->wramBase[DS_SIZE_WORKING_RAM >> 3];
1394 break;
1395 case 2:
1396 memory->wramSize7 = DS_SIZE_WORKING_RAM >> 1;
1397 memory->wramBase7 = &memory->wram[DS_SIZE_WORKING_RAM >> 3];
1398 memory->wramSize9 = DS_SIZE_WORKING_RAM >> 1;
1399 memory->wramBase9 = memory->wramBase;
1400 break;
1401 case 3:
1402 memory->wramSize7 = DS_SIZE_WORKING_RAM;
1403 memory->wramBase7 = memory->wramBase;
1404 memory->wramSize9 = 0;
1405 memory->wramBase9 = NULL;
1406 break;
1407 }
1408}
1409
1410void DSConfigureExternalMemory(struct DS* ds, uint16_t config) {
1411 // TODO: GBA params
1412 ds->memory.slot1Owner = config & 0x0800;
1413 ds->memory.slot2Owner = config & 0x0080;
1414 ds->memory.io7[DS7_REG_EXMEMSTAT >> 1] = config;
1415
1416 ds->ds7.memory.slot1Access = ds->memory.slot1Owner;
1417 ds->ds9.memory.slot1Access = !ds->memory.slot1Owner;
1418}
1419
1420static unsigned _selectVRAM(struct DSMemory* memory, uint32_t offset) {
1421 unsigned mask = 0;
1422 offset &= 0x3FF;
1423 mask |= memory->vramMirror[0][offset & 0x3F] & memory->vramMode[0][offset >> 7];
1424 mask |= memory->vramMirror[1][offset & 0x3F] & memory->vramMode[1][offset >> 7];
1425 mask |= memory->vramMirror[2][offset & 0x3F] & memory->vramMode[2][offset >> 7];
1426 mask |= memory->vramMirror[3][offset & 0x3F] & memory->vramMode[3][offset >> 7];
1427 mask |= memory->vramMirror[4][offset & 0x3F] & memory->vramMode[4][offset >> 7];
1428 mask |= memory->vramMirror[5][offset & 0x3F] & memory->vramMode[5][offset >> 7];
1429 mask |= memory->vramMirror[6][offset & 0x3F] & memory->vramMode[6][offset >> 7];
1430 mask |= memory->vramMirror[7][offset & 0x3F] & memory->vramMode[7][offset >> 7];
1431 mask |= memory->vramMirror[8][offset & 0x3F] & memory->vramMode[8][offset >> 7];
1432 return mask;
1433}