src/ds/slot1.c (view raw)
1/* Copyright (c) 2013-2017 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/slot1.h>
7
8#include <mgba/internal/arm/macros.h>
9#include <mgba/internal/ds/ds.h>
10#include <mgba/internal/ds/dma.h>
11#include <mgba-util/math.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(DS_SLOT1, "DS Slot-1", "ds.slot1");
15
16static void _slot1SPI(struct mTiming*, void* context, uint32_t cyclesLate);
17static void _transferEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
18static bool _slot1GuaranteeSize(struct DSSlot1*);
19
20void DSSlot1SPIInit(struct DS* ds, struct VFile* vf) {
21 ds->memory.slot1.spiEvent.name = "DS Slot-1 SPI";
22 ds->memory.slot1.spiEvent.priority = 0x70;
23 ds->memory.slot1.spiEvent.context = NULL;
24 ds->memory.slot1.spiEvent.callback = _slot1SPI;
25 ds->memory.slot1.transferEvent.name = "DS Slot-1 Transfer";
26 ds->memory.slot1.transferEvent.priority = 0x71;
27 ds->memory.slot1.transferEvent.context = ds;
28 ds->memory.slot1.transferEvent.callback = _transferEvent;
29 ds->memory.slot1.savedataType = DS_SAVEDATA_AUTODETECT;
30 ds->memory.slot1.spiVf = vf;
31 ds->memory.slot1.spiRealVf = vf;
32 ds->memory.slot1.spiData = NULL;
33}
34
35void DSSlot1Reset(struct DS* ds) {
36 ds->memory.slot1.statusReg = 0;
37 ds->memory.slot1.spiCommand = 0;
38 ds->memory.slot1.spiHoldEnabled = 0;
39 ds->memory.slot1.dmaSource = -1;
40}
41
42static void _scheduleTransfer(struct DS* ds, struct mTiming* timing, uint32_t cyclesLate) {
43 DSSlot1ROMCNT romcnt = ds->memory.io7[DS_REG_ROMCNT_HI >> 1] << 16;
44 uint32_t cycles;
45 if (DSSlot1ROMCNTIsTransferRate(romcnt)) {
46 cycles = 8;
47 } else {
48 cycles = 5;
49 }
50 if (!ds->ds7.memory.slot1Access) {
51 cycles <<= 1;
52 }
53 cycles -= cyclesLate;
54 mTimingDeschedule(timing, &ds->memory.slot1.transferEvent);
55 mTimingSchedule(timing, &ds->memory.slot1.transferEvent, cycles);
56}
57
58static void _transferEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
59 struct DS* ds = context;
60 DSSlot1ROMCNT romcnt;
61 // TODO: Big endian
62 LOAD_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io7);
63
64 struct DSCommon* dscore;
65 if (ds->ds7.memory.slot1Access) {
66 dscore = &ds->ds7;
67 } else {
68 dscore = &ds->ds9;
69 }
70
71 struct GBADMA* dma = NULL;
72 if (ds->memory.slot1.dmaSource >= 0) {
73 dma = &dscore->memory.dma[ds->memory.slot1.dmaSource];
74 }
75 bool hasDMA = false;
76 if (dma) {
77 if (ds->ds7.memory.slot1Access && GBADMARegisterGetTiming(dma->reg) == DS7_DMA_TIMING_SLOT1) {
78 hasDMA = true;
79 }
80 if (ds->ds9.memory.slot1Access && GBADMARegisterGetTiming9(dma->reg) == DS9_DMA_TIMING_SLOT1) {
81 hasDMA = true;
82 }
83 if (!GBADMARegisterIsEnable(dma->reg)) {
84 hasDMA = false;
85 }
86 }
87 if (!hasDMA) {
88 ds->memory.slot1.dmaSource = -1;
89 }
90
91 if (ds->memory.slot1.transferRemaining) {
92 ds->romVf->read(ds->romVf, ds->memory.slot1.readBuffer, 4);
93 // TODO: Error check
94 ds->memory.slot1.address += 4;
95 ds->memory.slot1.transferRemaining -= 4;
96 romcnt = DSSlot1ROMCNTFillWordReady(romcnt);
97
98 if (hasDMA) {
99 dma->when = mTimingCurrentTime(timing);
100 dma->nextCount = 1;
101 DSDMAUpdate(dscore);
102 }
103 } else {
104 DSSlot1AUXSPICNT config = ds->memory.io7[DS_REG_AUXSPICNT >> 1];
105 memset(ds->memory.slot1.readBuffer, 0, 4);
106 romcnt = DSSlot1ROMCNTClearWordReady(romcnt);
107 romcnt = DSSlot1ROMCNTClearBlockBusy(romcnt);
108 if (DSSlot1AUXSPICNTIsDoIRQ(config)) {
109 DSRaiseIRQ(dscore->cpu, dscore->memory.io, DS_IRQ_SLOT1_TRANS);
110 }
111 if (hasDMA) {
112 dma->reg = GBADMARegisterClearEnable(dma->reg);
113 dma->reg = GBADMARegisterClearRepeat(dma->reg);
114 dscore->memory.io[(DS_REG_DMA0CNT_HI + ds->memory.slot1.dmaSource * (DS_REG_DMA1CNT_HI - DS_REG_DMA0CNT_HI)) >> 1] = dma->reg;
115 }
116 }
117 STORE_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io7);
118 STORE_32(romcnt, DS_REG_ROMCNT_LO, ds->memory.io9);
119}
120
121static void DSSlot1StartTransfer(struct DS* ds) {
122 size_t i;
123 for (i = 0; i < 8; i += 2) {
124 uint16_t bytes;
125 LOAD_16(bytes, DS_REG_ROMCMD_0 + i, ds->memory.io7);
126 ds->memory.slot1.command[i] = bytes & 0xFF;
127 ds->memory.slot1.command[i + 1] = bytes >> 8;
128 }
129 switch (ds->memory.slot1.command[0]) {
130 case 0xB7:
131 ds->memory.slot1.address = ds->memory.slot1.command[1] << 24;
132 ds->memory.slot1.address |= ds->memory.slot1.command[2] << 16;
133 ds->memory.slot1.address |= ds->memory.slot1.command[3] << 8;
134 ds->memory.slot1.address |= ds->memory.slot1.command[4];
135 if (ds->romVf) {
136 ds->romVf->seek(ds->romVf, ds->memory.slot1.address, SEEK_SET);
137 }
138 ds->memory.slot1.transferRemaining = ds->memory.slot1.transferSize;
139 if (ds->ds7.memory.slot1Access) {
140 _scheduleTransfer(ds, &ds->ds7.timing, 0);
141 } else {
142 _scheduleTransfer(ds, &ds->ds9.timing, 0);
143 }
144 break;
145 case 0xB8:
146 memcpy(ds->memory.slot1.readBuffer, DS_CHIP_ID, 4);
147 ds->memory.slot1.transferRemaining = 0;
148 break;
149 default:
150 mLOG(DS_SLOT1, STUB, "Unimplemented card command: %02X%02X%02X%02X%02X%02X%02X%02X",
151 ds->memory.slot1.command[0], ds->memory.slot1.command[1],
152 ds->memory.slot1.command[2], ds->memory.slot1.command[3],
153 ds->memory.slot1.command[4], ds->memory.slot1.command[5],
154 ds->memory.slot1.command[6], ds->memory.slot1.command[7]);
155 break;
156 }
157}
158
159DSSlot1AUXSPICNT DSSlot1Configure(struct DS* ds, DSSlot1AUXSPICNT config) {
160 if (DSSlot1AUXSPICNTIsSPIMode(config)) {
161 if (!ds->memory.slot1.spiHoldEnabled) {
162 ds->memory.slot1.spiCommand = 0;
163 }
164 ds->memory.slot1.spiHoldEnabled = DSSlot1AUXSPICNTIsCSHold(config);
165 }
166 return config;
167}
168
169DSSlot1ROMCNT DSSlot1Control(struct DS* ds, DSSlot1ROMCNT control) {
170 ds->memory.slot1.transferSize = DSSlot1ROMCNTGetBlockSize(control);
171 if (ds->memory.slot1.transferSize != 0 && ds->memory.slot1.transferSize != 7) {
172 ds->memory.slot1.transferSize = 0x100 << ds->memory.slot1.transferSize;
173 }
174
175 DSSlot1AUXSPICNT config = ds->memory.io7[DS_REG_AUXSPICNT >> 1];
176 if (DSSlot1AUXSPICNTIsSPIMode(config)) {
177 mLOG(DS_SLOT1, STUB, "Bad ROMCNT?");
178 return control;
179 }
180 if (DSSlot1ROMCNTIsBlockBusy(control)) {
181 DSSlot1StartTransfer(ds);
182 // TODO: timing
183 control = DSSlot1ROMCNTFillWordReady(control);
184 }
185 return control;
186}
187
188uint32_t DSSlot1Read(struct DS* ds) {
189 uint32_t result;
190 LOAD_32(result, 0, ds->memory.slot1.readBuffer);
191 if (ds->ds7.memory.slot1Access) {
192 _scheduleTransfer(ds, &ds->ds7.timing, 0);
193 } else {
194 _scheduleTransfer(ds, &ds->ds9.timing, 0);
195 }
196 return result;
197}
198
199void DSSlot1WriteSPI(struct DSCommon* dscore, uint8_t datum) {
200 UNUSED(datum);
201 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
202 if (!DSSlot1AUXSPICNTIsSPIMode(control) || !DSSlot1AUXSPICNTIsEnable(control)) {
203 return;
204 }
205 uint32_t baud = 19 - DSSlot1AUXSPICNTGetBaud(control);
206 baud = DS_ARM7TDMI_FREQUENCY >> baud; // TODO: Right frequency for ARM9
207 control = DSSlot1AUXSPICNTFillBusy(control);
208 mTimingDeschedule(&dscore->timing, &dscore->p->memory.slot1.spiEvent);
209 mTimingSchedule(&dscore->timing, &dscore->p->memory.slot1.spiEvent, baud);
210 dscore->p->memory.slot1.spiEvent.context = dscore;
211 dscore->memory.io[DS_REG_AUXSPICNT >> 1] = control;
212 dscore->ipc->memory.io[DS_REG_AUXSPICNT >> 1] = control;
213}
214
215static uint8_t _slot1SPIAutodetect(struct DSCommon* dscore, uint8_t datum) {
216 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
217 mLOG(DS_SLOT1, STUB, "Unimplemented SPI write: %04X:%02X:%02X", control, dscore->p->memory.slot1.spiCommand, datum);
218
219 if (dscore->p->memory.slot1.spiAddressingRemaining) {
220 dscore->p->memory.slot1.spiAddress <<= 8;
221 dscore->p->memory.slot1.spiAddress |= datum;
222 dscore->p->memory.slot1.spiAddressingRemaining -= 8;
223 if (dscore->p->memory.slot1.spiAddressingPc >= 0) {
224 dscore->p->memory.slot1.spiAddressingPc = dscore->cpu->gprs[ARM_PC];
225 }
226 return 0xFF;
227 } else if (dscore->cpu->gprs[ARM_PC] == dscore->p->memory.slot1.spiAddressingPc) {
228 dscore->p->memory.slot1.spiAddress <<= 8;
229 dscore->p->memory.slot1.spiAddress |= datum;
230 dscore->p->memory.slot1.savedataType = DS_SAVEDATA_FLASH;
231 return 0xFF;
232 } else {
233 if (dscore->p->memory.slot1.spiAddress) {
234 // Cease autodetection
235 dscore->p->memory.slot1.spiAddressingPc = -1;
236 }
237 if (!_slot1GuaranteeSize(&dscore->p->memory.slot1)) {
238 return 0xFF;
239 }
240 }
241
242 switch (dscore->p->memory.slot1.spiCommand) {
243 case 0x03: // RD
244 return dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress++];
245 case 0x02: // WR
246 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
247 ++dscore->p->memory.slot1.spiAddress;
248 break;
249 }
250 return 0xFF;
251}
252
253static uint8_t _slot1SPIFlash(struct DSCommon* dscore, uint8_t datum) {
254 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
255
256 if (dscore->p->memory.slot1.spiAddressingRemaining) {
257 dscore->p->memory.slot1.spiAddress <<= 8;
258 dscore->p->memory.slot1.spiAddress |= datum;
259 dscore->p->memory.slot1.spiAddressingRemaining -= 8;
260 return 0xFF;
261 } else {
262 if (!_slot1GuaranteeSize(&dscore->p->memory.slot1)) {
263 return 0xFF;
264 }
265 }
266
267 uint8_t oldValue;
268 switch (dscore->p->memory.slot1.spiCommand) {
269 case 0x03: // RD
270 oldValue = dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress];
271 ++dscore->p->memory.slot1.spiAddress;
272 return oldValue;
273 case 0x02: // PP
274 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
275 ++dscore->p->memory.slot1.spiAddress;
276 break;
277 case 0x0A: // PW
278 oldValue = dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress];
279 dscore->p->memory.slot1.spiData[dscore->p->memory.slot1.spiAddress] = datum;
280 ++dscore->p->memory.slot1.spiAddress;
281 return oldValue;
282 default:
283 mLOG(DS_SLOT1, STUB, "Unimplemented SPI Flash write: %04X:%02X:%02X", control, dscore->p->memory.slot1.spiCommand, datum);
284 break;
285 }
286 return 0xFF;
287}
288
289static void _slot1SPI(struct mTiming* timing, void* context, uint32_t cyclesLate) {
290 UNUSED(timing);
291 UNUSED(cyclesLate);
292 struct DSCommon* dscore = context;
293 DSSlot1AUXSPICNT control = dscore->memory.io[DS_REG_AUXSPICNT >> 1];
294 uint8_t oldValue = dscore->memory.io[DS_REG_AUXSPIDATA >> 1];
295 uint8_t newValue = 0xFF;
296
297 if (!dscore->p->memory.slot1.spiCommand) {
298 dscore->p->memory.slot1.spiCommand = oldValue;
299 // Probably RDHI
300 if (oldValue == 0x0B && dscore->p->memory.slot1.savedataType == DS_SAVEDATA_AUTODETECT) {
301 dscore->p->memory.slot1.savedataType = DS_SAVEDATA_EEPROM512;
302 }
303 dscore->p->memory.slot1.spiAddress = 0;
304 switch (dscore->p->memory.slot1.savedataType) {
305 case DS_SAVEDATA_FLASH:
306 dscore->p->memory.slot1.spiAddressingRemaining = 24;
307 break;
308 default:
309 dscore->p->memory.slot1.spiAddressingRemaining = 16;
310 break;
311 }
312 } else {
313 switch (dscore->p->memory.slot1.spiCommand) {
314 case 0x04: // WRDI
315 dscore->p->memory.slot1.statusReg &= ~2;
316 break;
317 case 0x05: // RDSR
318 newValue = dscore->p->memory.slot1.statusReg;
319 break;
320 case 0x06: // WREN
321 dscore->p->memory.slot1.statusReg |= 2;
322 break;
323 default:
324 switch (dscore->p->memory.slot1.savedataType) {
325 case DS_SAVEDATA_AUTODETECT:
326 newValue = _slot1SPIAutodetect(dscore, oldValue);
327 break;
328 case DS_SAVEDATA_FLASH:
329 newValue = _slot1SPIFlash(dscore, oldValue);
330 break;
331 default:
332 mLOG(DS_SLOT1, STUB, "Unimplemented SPI write: %04X:%02X", control, oldValue);
333 break;
334 }
335 }
336 }
337
338 control = DSSlot1AUXSPICNTClearBusy(control);
339 dscore->memory.io[DS_REG_AUXSPIDATA >> 1] = newValue;
340 dscore->ipc->memory.io[DS_REG_AUXSPIDATA >> 1] = newValue;
341 dscore->memory.io[DS_REG_AUXSPICNT >> 1] = control;
342 dscore->ipc->memory.io[DS_REG_AUXSPICNT >> 1] = control;
343}
344
345static bool _slot1GuaranteeSize(struct DSSlot1* slot1) {
346 if (!slot1->spiVf) {
347 return false;
348 }
349 if (slot1->spiAddress >= slot1->spiVf->size(slot1->spiVf)) {
350 size_t size = toPow2(slot1->spiAddress + 1);
351 size_t oldSize = slot1->spiVf->size(slot1->spiVf);
352 if (slot1->spiData) {
353 slot1->spiVf->unmap(slot1->spiVf, slot1->spiData, oldSize);
354 slot1->spiData = NULL;
355 }
356 slot1->spiVf->truncate(slot1->spiVf, size);
357 slot1->spiVf->seek(slot1->spiVf, oldSize, SEEK_SET);
358 while (oldSize < size) {
359 static char buffer[1024];
360 memset(buffer, 0xFF, sizeof(buffer));
361 ssize_t written;
362 if (oldSize + sizeof(buffer) <= size) {
363 written = slot1->spiVf->write(slot1->spiVf, buffer, sizeof(buffer));
364 } else {
365 written = slot1->spiVf->write(slot1->spiVf, buffer, size - oldSize);
366 }
367 if (written >= 0) {
368 oldSize += written;
369 } else {
370 break;
371 }
372 }
373 }
374 if (!slot1->spiData) {
375 slot1->spiData = slot1->spiVf->map(slot1->spiVf, slot1->spiVf->size(slot1->spiVf), MAP_WRITE);
376 }
377 return slot1->spiData;
378}
379
380void DSSlot1ScheduleDMA(struct DSCommon* dscore, int number, struct GBADMA* info) {
381 UNUSED(info);
382 dscore->p->memory.slot1.dmaSource = number;
383}