src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12#define ARM_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles32)
13
14// Addressing mode 1
15static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
16 int rm = opcode & 0x0000000F;
17 int immediate = (opcode & 0x00000F80) >> 7;
18 if (!immediate) {
19 cpu->shifterOperand = cpu->gprs[rm];
20 cpu->shifterCarryOut = cpu->cpsr.c;
21 } else {
22 cpu->shifterOperand = cpu->gprs[rm] << immediate;
23 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
24 }
25}
26
27static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
28 int rm = opcode & 0x0000000F;
29 int rs = (opcode >> 8) & 0x0000000F;
30 ++cpu->cycles;
31 int shift = cpu->gprs[rs];
32 if (rs == ARM_PC) {
33 shift += 4;
34 }
35 shift &= 0xFF;
36 int32_t shiftVal = cpu->gprs[rm];
37 if (rm == ARM_PC) {
38 shiftVal += 4;
39 }
40 if (!shift) {
41 cpu->shifterOperand = shiftVal;
42 cpu->shifterCarryOut = cpu->cpsr.c;
43 } else if (shift < 32) {
44 cpu->shifterOperand = shiftVal << shift;
45 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
46 } else if (shift == 32) {
47 cpu->shifterOperand = 0;
48 cpu->shifterCarryOut = shiftVal & 1;
49 } else {
50 cpu->shifterOperand = 0;
51 cpu->shifterCarryOut = 0;
52 }
53}
54
55static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
56 int rm = opcode & 0x0000000F;
57 int immediate = (opcode & 0x00000F80) >> 7;
58 if (immediate) {
59 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
60 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
61 } else {
62 cpu->shifterOperand = 0;
63 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
64 }
65}
66
67static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
68 int rm = opcode & 0x0000000F;
69 int rs = (opcode >> 8) & 0x0000000F;
70 ++cpu->cycles;
71 int shift = cpu->gprs[rs];
72 if (rs == ARM_PC) {
73 shift += 4;
74 }
75 shift &= 0xFF;
76 uint32_t shiftVal = cpu->gprs[rm];
77 if (rm == ARM_PC) {
78 shiftVal += 4;
79 }
80 if (!shift) {
81 cpu->shifterOperand = shiftVal;
82 cpu->shifterCarryOut = cpu->cpsr.c;
83 } else if (shift < 32) {
84 cpu->shifterOperand = shiftVal >> shift;
85 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
86 } else if (shift == 32) {
87 cpu->shifterOperand = 0;
88 cpu->shifterCarryOut = shiftVal >> 31;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = 0;
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 int immediate = (opcode & 0x00000F80) >> 7;
98 if (immediate) {
99 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
100 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
101 } else {
102 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
103 cpu->shifterOperand = cpu->shifterCarryOut;
104 }
105}
106
107static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
108 int rm = opcode & 0x0000000F;
109 int rs = (opcode >> 8) & 0x0000000F;
110 ++cpu->cycles;
111 int shift = cpu->gprs[rs];
112 if (rs == ARM_PC) {
113 shift += 4;
114 }
115 shift &= 0xFF;
116 int shiftVal = cpu->gprs[rm];
117 if (rm == ARM_PC) {
118 shiftVal += 4;
119 }
120 if (!shift) {
121 cpu->shifterOperand = shiftVal;
122 cpu->shifterCarryOut = cpu->cpsr.c;
123 } else if (shift < 32) {
124 cpu->shifterOperand = shiftVal >> shift;
125 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
126 } else if (cpu->gprs[rm] >> 31) {
127 cpu->shifterOperand = 0xFFFFFFFF;
128 cpu->shifterCarryOut = 1;
129 } else {
130 cpu->shifterOperand = 0;
131 cpu->shifterCarryOut = 0;
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 int immediate = (opcode & 0x00000F80) >> 7;
138 if (immediate) {
139 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
140 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
141 } else {
142 // RRX
143 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
144 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
145 }
146}
147
148static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
149 int rm = opcode & 0x0000000F;
150 int rs = (opcode >> 8) & 0x0000000F;
151 ++cpu->cycles;
152 int shift = cpu->gprs[rs];
153 if (rs == ARM_PC) {
154 shift += 4;
155 }
156 shift &= 0xFF;
157 int shiftVal = cpu->gprs[rm];
158 if (rm == ARM_PC) {
159 shiftVal += 4;
160 }
161 int rotate = shift & 0x1F;
162 if (!shift) {
163 cpu->shifterOperand = shiftVal;
164 cpu->shifterCarryOut = cpu->cpsr.c;
165 } else if (rotate) {
166 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
167 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
168 } else {
169 cpu->shifterOperand = shiftVal;
170 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
171 }
172}
173
174static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
175 int rotate = (opcode & 0x00000F00) >> 7;
176 int immediate = opcode & 0x000000FF;
177 if (!rotate) {
178 cpu->shifterOperand = immediate;
179 cpu->shifterCarryOut = cpu->cpsr.c;
180 } else {
181 cpu->shifterOperand = ARM_ROR(immediate, rotate);
182 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
183 }
184}
185
186static const ARMInstruction _armTable[0x1000];
187
188static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
189 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
190 *opcodeOut = opcode;
191 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
192}
193
194void ARMStep(struct ARMCore* cpu) {
195 // TODO
196 uint32_t opcode;
197 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
198 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
199
200 int condition = opcode >> 28;
201 if (condition == 0xE) {
202 instruction(cpu, opcode);
203 return;
204 } else {
205 switch (condition) {
206 case 0x0:
207 if (!ARM_COND_EQ) {
208 cpu->cycles += ARM_PREFETCH_CYCLES;
209 return;
210 }
211 break;
212 case 0x1:
213 if (!ARM_COND_NE) {
214 cpu->cycles += ARM_PREFETCH_CYCLES;
215 return;
216 }
217 break;
218 case 0x2:
219 if (!ARM_COND_CS) {
220 cpu->cycles += ARM_PREFETCH_CYCLES;
221 return;
222 }
223 break;
224 case 0x3:
225 if (!ARM_COND_CC) {
226 cpu->cycles += ARM_PREFETCH_CYCLES;
227 return;
228 }
229 break;
230 case 0x4:
231 if (!ARM_COND_MI) {
232 cpu->cycles += ARM_PREFETCH_CYCLES;
233 return;
234 }
235 break;
236 case 0x5:
237 if (!ARM_COND_PL) {
238 cpu->cycles += ARM_PREFETCH_CYCLES;
239 return;
240 }
241 break;
242 case 0x6:
243 if (!ARM_COND_VS) {
244 cpu->cycles += ARM_PREFETCH_CYCLES;
245 return;
246 }
247 break;
248 case 0x7:
249 if (!ARM_COND_VC) {
250 cpu->cycles += ARM_PREFETCH_CYCLES;
251 return;
252 }
253 break;
254 case 0x8:
255 if (!ARM_COND_HI) {
256 cpu->cycles += ARM_PREFETCH_CYCLES;
257 return;
258 }
259 break;
260 case 0x9:
261 if (!ARM_COND_LS) {
262 cpu->cycles += ARM_PREFETCH_CYCLES;
263 return;
264 }
265 break;
266 case 0xA:
267 if (!ARM_COND_GE) {
268 cpu->cycles += ARM_PREFETCH_CYCLES;
269 return;
270 }
271 break;
272 case 0xB:
273 if (!ARM_COND_LT) {
274 cpu->cycles += ARM_PREFETCH_CYCLES;
275 return;
276 }
277 break;
278 case 0xC:
279 if (!ARM_COND_GT) {
280 cpu->cycles += ARM_PREFETCH_CYCLES;
281 return;
282 }
283 break;
284 case 0xD:
285 if (!ARM_COND_LE) {
286 cpu->cycles += ARM_PREFETCH_CYCLES;
287 return;
288 }
289 break;
290 default:
291 break;
292 }
293 }
294 instruction(cpu, opcode);
295}
296
297// Instruction definitions
298// Beware pre-processor antics
299
300#define ARM_ADDITION_S(M, N, D) \
301 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
302 cpu->cpsr = cpu->spsr; \
303 _ARMReadCPSR(cpu); \
304 } else { \
305 cpu->cpsr.n = ARM_SIGN(D); \
306 cpu->cpsr.z = !(D); \
307 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
308 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
309 }
310
311#define ARM_SUBTRACTION_S(M, N, D) \
312 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
313 cpu->cpsr = cpu->spsr; \
314 _ARMReadCPSR(cpu); \
315 } else { \
316 cpu->cpsr.n = ARM_SIGN(D); \
317 cpu->cpsr.z = !(D); \
318 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
319 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
320 }
321
322#define ARM_NEUTRAL_S(M, N, D) \
323 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
324 cpu->cpsr = cpu->spsr; \
325 _ARMReadCPSR(cpu); \
326 } else { \
327 cpu->cpsr.n = ARM_SIGN(D); \
328 cpu->cpsr.z = !(D); \
329 cpu->cpsr.c = cpu->shifterCarryOut; \
330 }
331
332#define ARM_NEUTRAL_HI_S(DLO, DHI) \
333 cpu->cpsr.n = ARM_SIGN(DHI); \
334 cpu->cpsr.z = !((DHI) | (DLO));
335
336#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
337#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
338#define ADDR_MODE_2_ADDRESS (address)
339#define ADDR_MODE_2_RN (cpu->gprs[rn])
340#define ADDR_MODE_2_RM (cpu->gprs[rm])
341#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
342#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
343#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
344#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
345#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
346#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
347#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
348
349#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
350#define ADDR_MODE_3_RN ADDR_MODE_2_RN
351#define ADDR_MODE_3_RM ADDR_MODE_2_RM
352#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
353#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
354#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
355
356#define ARM_LOAD_POST_BODY \
357 if (rd == ARM_PC) { \
358 ARM_WRITE_PC; \
359 }
360
361#define ARM_STORE_POST_BODY \
362 currentCycles -= ARM_PREFETCH_CYCLES; \
363 currentCycles += 1 + cpu->memory->activeNonseqCycles32;
364
365#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
366 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
367 int currentCycles = ARM_PREFETCH_CYCLES; \
368 BODY; \
369 cpu->cycles += currentCycles; \
370 }
371
372#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
373 DEFINE_INSTRUCTION_ARM(NAME, \
374 int rd = (opcode >> 12) & 0xF; \
375 int rn = (opcode >> 16) & 0xF; \
376 UNUSED(rn); \
377 SHIFTER(cpu, opcode); \
378 BODY; \
379 S_BODY; \
380 if (rd == ARM_PC) { \
381 if (cpu->executionMode == MODE_ARM) { \
382 ARM_WRITE_PC; \
383 } else { \
384 THUMB_WRITE_PC; \
385 } \
386 })
387
388#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
389 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
390 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
391 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
392 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
393 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
394 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
395 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
396 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
397 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
398 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
399 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
400 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
401 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
402 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
403 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
404 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
405 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
406 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
407
408#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
409 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
410 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
411 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
412 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
413 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
414 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
415 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
416 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
417 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
418
419#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
420 DEFINE_INSTRUCTION_ARM(NAME, \
421 int rd = (opcode >> 12) & 0xF; \
422 int rdHi = (opcode >> 16) & 0xF; \
423 int rs = (opcode >> 8) & 0xF; \
424 int rm = opcode & 0xF; \
425 UNUSED(rdHi); \
426 ARM_WAIT_MUL(cpu->gprs[rs]); \
427 BODY; \
428 S_BODY; \
429 if (rd == ARM_PC) { \
430 ARM_WRITE_PC; \
431 })
432
433#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
434 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
435 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
436
437#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
438 DEFINE_INSTRUCTION_ARM(NAME, \
439 uint32_t address; \
440 int rn = (opcode >> 16) & 0xF; \
441 int rd = (opcode >> 12) & 0xF; \
442 int rm = opcode & 0xF; \
443 UNUSED(rm); \
444 address = ADDRESS; \
445 BODY; \
446 WRITEBACK;)
447
448#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
455
456#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
459 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
460 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
467
468#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
473 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
474 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
479 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
480 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
481
482#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
483 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
485
486#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
487 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
488 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
489 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
490 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
491 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
492 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
493
494#define ARM_MS_PRE \
495 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
496 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
497
498#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
499
500#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
501#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
502#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
503#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
504#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
505#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
506#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
507#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
508
509#define ARM_M_INCREMENT(BODY) \
510 for (m = rs, i = 0; m; m >>= 1, ++i) { \
511 if (m & 1) { \
512 BODY; \
513 addr += 4; \
514 total += 1; \
515 } \
516 }
517
518#define ARM_M_DECREMENT(BODY) \
519 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
520 if (rs & m) { \
521 BODY; \
522 addr -= 4; \
523 total += 1; \
524 } \
525 }
526
527#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
528 DEFINE_INSTRUCTION_ARM(NAME, \
529 int rn = (opcode >> 16) & 0xF; \
530 int rs = opcode & 0x0000FFFF; \
531 int m; \
532 int i; \
533 int total = 0; \
534 ADDRESS; \
535 S_PRE; \
536 LOOP(BODY); \
537 S_POST; \
538 WRITEBACK; \
539 currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
540 POST_BODY;)
541
542
543#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
544 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
545 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
546 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
547 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
548 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
549 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
550 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
551 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
552 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
553 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
554 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
555 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
556 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
557 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
558 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
559 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
560
561// Begin ALU definitions
562
563DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
564 int32_t n = cpu->gprs[rn];
565 cpu->gprs[rd] = n + cpu->shifterOperand;)
566
567DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
568 int32_t n = cpu->gprs[rn];
569 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
570 cpu->gprs[rd] = n + shifterOperand;)
571
572DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
573 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
574
575DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
576 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
577
578DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
579 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
580
581DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
582 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
583
584DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
585 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
586
587DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
588 cpu->gprs[rd] = cpu->shifterOperand;)
589
590DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
591 cpu->gprs[rd] = ~cpu->shifterOperand;)
592
593DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
594 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
595
596DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
597 int32_t n = cpu->gprs[rn];
598 cpu->gprs[rd] = cpu->shifterOperand - n;)
599
600DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
601 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
602 cpu->gprs[rd] = cpu->shifterOperand - n;)
603
604DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
605 int32_t n = cpu->gprs[rn];
606 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
607 cpu->gprs[rd] = n - shifterOperand;)
608
609DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
610 int32_t n = cpu->gprs[rn];
611 cpu->gprs[rd] = n - cpu->shifterOperand;)
612
613DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
614 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
615
616DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
617 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
618
619// End ALU definitions
620
621// Begin multiply definitions
622
623DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
624DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
625
626DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
627 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
628 int32_t dm = cpu->gprs[rd];
629 int32_t dn = d;
630 cpu->gprs[rd] = dm + dn;
631 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
632 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
633
634DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
635 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
636 cpu->gprs[rd] = d;
637 cpu->gprs[rdHi] = d >> 32;,
638 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
639
640DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
641 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
642 int32_t dm = cpu->gprs[rd];
643 int32_t dn = d;
644 cpu->gprs[rd] = dm + dn;
645 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
646 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
647
648DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
649 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
650 cpu->gprs[rd] = d;
651 cpu->gprs[rdHi] = d >> 32;,
652 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
653
654// End multiply definitions
655
656// Begin load/store definitions
657
658DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
659DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
660DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
661DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
662DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
663DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
664DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
665DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
666
667DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
668 enum PrivilegeMode priv = cpu->privilegeMode;
669 ARMSetPrivilegeMode(cpu, MODE_USER);
670 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles);
671 ARMSetPrivilegeMode(cpu, priv);
672 ARM_LOAD_POST_BODY;)
673
674DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
675 enum PrivilegeMode priv = cpu->privilegeMode;
676 ARMSetPrivilegeMode(cpu, MODE_USER);
677 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles);
678 ARMSetPrivilegeMode(cpu, priv);
679 ARM_LOAD_POST_BODY;)
680
681DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
682 enum PrivilegeMode priv = cpu->privilegeMode;
683 ARMSetPrivilegeMode(cpu, MODE_USER);
684 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
685 ARMSetPrivilegeMode(cpu, priv);
686 ARM_STORE_POST_BODY;)
687
688DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
689 enum PrivilegeMode priv = cpu->privilegeMode;
690 ARMSetPrivilegeMode(cpu, MODE_USER);
691 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
692 ARMSetPrivilegeMode(cpu, priv);
693 ARM_STORE_POST_BODY;)
694
695DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
696 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr, 0);,
697 ++currentCycles;
698 if (rs & 0x8000) {
699 ARM_WRITE_PC;
700 })
701
702DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
703 cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
704 currentCycles -= ARM_PREFETCH_CYCLES)
705
706DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
707DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
708
709// End load/store definitions
710
711// Begin branch definitions
712
713DEFINE_INSTRUCTION_ARM(B,
714 int32_t offset = opcode << 8;
715 offset >>= 6;
716 cpu->gprs[ARM_PC] += offset;
717 ARM_WRITE_PC;)
718
719DEFINE_INSTRUCTION_ARM(BL,
720 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
721 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
722 cpu->gprs[ARM_PC] += immediate >> 6;
723 ARM_WRITE_PC;)
724
725DEFINE_INSTRUCTION_ARM(BX,
726 int rm = opcode & 0x0000000F;
727 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
728 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
729 if (cpu->executionMode == MODE_THUMB) {
730 THUMB_WRITE_PC;
731 } else {
732 ARM_WRITE_PC;
733 })
734
735// End branch definitions
736
737// Begin miscellaneous definitions
738
739DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
740DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
741
742DEFINE_INSTRUCTION_ARM(MSR,
743 int c = opcode & 0x00010000;
744 int f = opcode & 0x00080000;
745 int32_t operand = cpu->gprs[opcode & 0x0000000F];
746 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
747 if (mask & PSR_USER_MASK) {
748 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
749 }
750 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
751 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
752 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
753 })
754
755DEFINE_INSTRUCTION_ARM(MSRR,
756 int c = opcode & 0x00010000;
757 int f = opcode & 0x00080000;
758 int32_t operand = cpu->gprs[opcode & 0x0000000F];
759 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
760 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
761 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
762
763DEFINE_INSTRUCTION_ARM(MRS, \
764 int rd = (opcode >> 12) & 0xF; \
765 cpu->gprs[rd] = cpu->cpsr.packed;)
766
767DEFINE_INSTRUCTION_ARM(MRSR, \
768 int rd = (opcode >> 12) & 0xF; \
769 cpu->gprs[rd] = cpu->spsr.packed;)
770
771DEFINE_INSTRUCTION_ARM(MSRI,
772 int c = opcode & 0x00010000;
773 int f = opcode & 0x00080000;
774 int rotate = (opcode & 0x00000F00) >> 8;
775 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
776 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
777 if (mask & PSR_USER_MASK) {
778 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
779 }
780 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
781 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
782 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
783 })
784
785DEFINE_INSTRUCTION_ARM(MSRRI,
786 int c = opcode & 0x00010000;
787 int f = opcode & 0x00080000;
788 int rotate = (opcode & 0x00000F00) >> 8;
789 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
790 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
791 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
792 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
793
794DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
795
796#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
797 EMITTER ## NAME
798
799#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
800 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
801 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
802
803#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
804 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
805 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
806 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
807 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
808 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
809 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
820
821#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
822 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
823 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
824
825#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
826 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
829 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
831 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
832 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
833 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
834 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
842
843#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
844 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
845 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
846
847#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
848 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
849
850// TODO: Support coprocessors
851#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
852 DO_8(0), \
853 DO_8(0)
854
855#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
856 DO_8(DO_8(DO_INTERLACE(0, 0))), \
857 DO_8(DO_8(DO_INTERLACE(0, 0)))
858
859#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
860 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
861
862#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
863 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
864 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
865 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
866 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
867 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
868 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
869 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
870 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
871 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
872 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
873 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
874 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
875 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
876 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
877 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
878 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
879 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
880 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
881 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
882 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
883 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
884 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
885 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
886 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
887 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
888 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
889 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
890 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
891 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
892 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
893 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
894 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
895 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
896 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
897 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
898 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
899 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
900 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
901 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
902 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
903 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
904 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
905 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
906 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
907 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
908 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
909 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
910 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
911 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
912 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
913 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
914 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
915 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
916 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
917 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
918 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
919 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
920 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
921 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
922 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
923 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
924 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
925 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
926 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
927 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
928 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
929 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
930 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
931 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
932 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
933 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
934 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
935 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
936 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
937 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
938 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
939 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
940 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
941 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
942 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
943 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
944 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
945 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
946 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
947 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
948 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
949 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
950 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
951 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
952 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
953 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
954 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
955 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
956 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
957 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
958 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
959 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
960 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
961 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
962 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
963 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
964 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
965 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
966 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
967 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
968 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
969 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
970 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
971 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
972 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
973 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
974 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
975 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
976 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
977 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
978 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
979 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
980 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
981 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
982 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
983 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
984 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
985 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
986 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
987 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
988 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
989 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
990 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
991 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
992 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
993 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
994 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
995 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
996 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
997 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
998 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
999 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
1000 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
1001 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
1002 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
1003 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
1004 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
1005 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
1006 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
1007 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
1008 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
1009 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
1010 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
1011 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
1012 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
1013 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
1014 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
1015 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
1016 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
1017 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
1018 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
1019 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
1020 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
1021 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
1022 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
1023 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
1024 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
1025 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
1026 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
1027 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
1028 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
1029 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
1030 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
1031 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
1032 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
1033 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
1034 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
1035 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
1036 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
1037 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
1038 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
1039 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
1040 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
1041 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
1042 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
1043 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
1044 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
1045 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
1046 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
1047 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
1048 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
1049 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
1050 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
1051 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
1052 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
1053 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
1054 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
1055 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
1056 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
1057 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
1058 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
1059 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
1060 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
1061 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
1062 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
1063 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
1064 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
1065 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
1066 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
1067 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
1068 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
1069 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
1070 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
1071 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
1072 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
1073 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
1074 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
1075 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
1076 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
1077 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
1078 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
1079 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
1080 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
1081 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
1082 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
1083 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
1084 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
1085 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
1086 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
1087 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
1088 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1089 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1090 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1091 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1092 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1093 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1094 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1095 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1096 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1097 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1098 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1099 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1100 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1101 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1102 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1103 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1104 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1105 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1106 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1107 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1108 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1109 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1110 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1111 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1112 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1113 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1114 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1115 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1116 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1117 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1118 DECLARE_ARM_SWI_BLOCK(EMITTER)
1119
1120static const ARMInstruction _armTable[0x1000] = {
1121 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1122};