src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "emitter-arm.h"
5#include "isa-inlines.h"
6
7#define PSR_USER_MASK 0xF0000000
8#define PSR_PRIV_MASK 0x000000CF
9#define PSR_STATE_MASK 0x00000020
10
11// Addressing mode 1
12static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
13 int rm = opcode & 0x0000000F;
14 int immediate = (opcode & 0x00000F80) >> 7;
15 if (!immediate) {
16 cpu->shifterOperand = cpu->gprs[rm];
17 cpu->shifterCarryOut = cpu->cpsr.c;
18 } else {
19 cpu->shifterOperand = cpu->gprs[rm] << immediate;
20 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
21 }
22}
23
24static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
25 int rm = opcode & 0x0000000F;
26 int rs = (opcode >> 8) & 0x0000000F;
27 ++cpu->cycles;
28 int shift = cpu->gprs[rs];
29 if (rs == ARM_PC) {
30 shift += 4;
31 }
32 shift &= 0xFF;
33 int32_t shiftVal = cpu->gprs[rm];
34 if (rm == ARM_PC) {
35 shiftVal += 4;
36 }
37 if (!shift) {
38 cpu->shifterOperand = shiftVal;
39 cpu->shifterCarryOut = cpu->cpsr.c;
40 } else if (shift < 32) {
41 cpu->shifterOperand = shiftVal << shift;
42 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
43 } else if (shift == 32) {
44 cpu->shifterOperand = 0;
45 cpu->shifterCarryOut = shiftVal & 1;
46 } else {
47 cpu->shifterOperand = 0;
48 cpu->shifterCarryOut = 0;
49 }
50}
51
52static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
53 int rm = opcode & 0x0000000F;
54 int immediate = (opcode & 0x00000F80) >> 7;
55 if (immediate) {
56 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
57 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
58 } else {
59 cpu->shifterOperand = 0;
60 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
61 }
62}
63
64static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int rs = (opcode >> 8) & 0x0000000F;
67 ++cpu->cycles;
68 int shift = cpu->gprs[rs];
69 if (rs == ARM_PC) {
70 shift += 4;
71 }
72 shift &= 0xFF;
73 uint32_t shiftVal = cpu->gprs[rm];
74 if (rm == ARM_PC) {
75 shiftVal += 4;
76 }
77 if (!shift) {
78 cpu->shifterOperand = shiftVal;
79 cpu->shifterCarryOut = cpu->cpsr.c;
80 } else if (shift < 32) {
81 cpu->shifterOperand = shiftVal >> shift;
82 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
83 } else if (shift == 32) {
84 cpu->shifterOperand = 0;
85 cpu->shifterCarryOut = shiftVal >> 31;
86 } else {
87 cpu->shifterOperand = 0;
88 cpu->shifterCarryOut = 0;
89 }
90}
91
92static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
93 int rm = opcode & 0x0000000F;
94 int immediate = (opcode & 0x00000F80) >> 7;
95 if (immediate) {
96 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
97 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
98 } else {
99 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
100 cpu->shifterOperand = cpu->shifterCarryOut;
101 }
102}
103
104static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
105 int rm = opcode & 0x0000000F;
106 int rs = (opcode >> 8) & 0x0000000F;
107 ++cpu->cycles;
108 int shift = cpu->gprs[rs];
109 if (rs == ARM_PC) {
110 shift += 4;
111 }
112 shift &= 0xFF;
113 int shiftVal = cpu->gprs[rm];
114 if (rm == ARM_PC) {
115 shiftVal += 4;
116 }
117 if (!shift) {
118 cpu->shifterOperand = shiftVal;
119 cpu->shifterCarryOut = cpu->cpsr.c;
120 } else if (shift < 32) {
121 cpu->shifterOperand = shiftVal >> shift;
122 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
123 } else if (cpu->gprs[rm] >> 31) {
124 cpu->shifterOperand = 0xFFFFFFFF;
125 cpu->shifterCarryOut = 1;
126 } else {
127 cpu->shifterOperand = 0;
128 cpu->shifterCarryOut = 0;
129 }
130}
131
132static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
133 int rm = opcode & 0x0000000F;
134 int immediate = (opcode & 0x00000F80) >> 7;
135 if (immediate) {
136 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
137 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
138 } else {
139 // RRX
140 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
141 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
142 }
143}
144
145static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
146 int rm = opcode & 0x0000000F;
147 int rs = (opcode >> 8) & 0x0000000F;
148 ++cpu->cycles;
149 int shift = cpu->gprs[rs];
150 if (rs == ARM_PC) {
151 shift += 4;
152 }
153 shift &= 0xFF;
154 int shiftVal = cpu->gprs[rm];
155 if (rm == ARM_PC) {
156 shiftVal += 4;
157 }
158 int rotate = shift & 0x1F;
159 if (!shift) {
160 cpu->shifterOperand = shiftVal;
161 cpu->shifterCarryOut = cpu->cpsr.c;
162 } else if (rotate) {
163 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
164 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
165 } else {
166 cpu->shifterOperand = shiftVal;
167 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
168 }
169}
170
171static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
172 int rotate = (opcode & 0x00000F00) >> 7;
173 int immediate = opcode & 0x000000FF;
174 if (!rotate) {
175 cpu->shifterOperand = immediate;
176 cpu->shifterCarryOut = cpu->cpsr.c;
177 } else {
178 cpu->shifterOperand = ARM_ROR(immediate, rotate);
179 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
180 }
181}
182
183// Instruction definitions
184// Beware pre-processor antics
185
186#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_NEUTRAL_S(M, N, D) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = cpu->shifterCarryOut; \
218 }
219
220#define ARM_NEUTRAL_HI_S(DLO, DHI) \
221 cpu->cpsr.n = ARM_SIGN(DHI); \
222 cpu->cpsr.z = !((DHI) | (DLO));
223
224#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
225#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
226#define ADDR_MODE_2_ADDRESS (address)
227#define ADDR_MODE_2_RN (cpu->gprs[rn])
228#define ADDR_MODE_2_RM (cpu->gprs[rm])
229#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
230#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
231#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
232#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
233#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
234#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
235#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
236
237#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
238#define ADDR_MODE_3_RN ADDR_MODE_2_RN
239#define ADDR_MODE_3_RM ADDR_MODE_2_RM
240#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
241#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
242#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
243
244#define ARM_LOAD_POST_BODY \
245 ++currentCycles; \
246 if (rd == ARM_PC) { \
247 ARM_WRITE_PC; \
248 }
249
250#define ARM_STORE_POST_BODY \
251 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
252
253#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
254 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
255 int currentCycles = ARM_PREFETCH_CYCLES; \
256 BODY; \
257 cpu->cycles += currentCycles; \
258 }
259
260#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
261 DEFINE_INSTRUCTION_ARM(NAME, \
262 int rd = (opcode >> 12) & 0xF; \
263 int rn = (opcode >> 16) & 0xF; \
264 UNUSED(rn); \
265 SHIFTER(cpu, opcode); \
266 BODY; \
267 S_BODY; \
268 if (rd == ARM_PC) { \
269 if (cpu->executionMode == MODE_ARM) { \
270 ARM_WRITE_PC; \
271 } else { \
272 THUMB_WRITE_PC; \
273 } \
274 })
275
276#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
277 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
278 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
295
296#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
306
307#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
308 DEFINE_INSTRUCTION_ARM(NAME, \
309 int rd = (opcode >> 12) & 0xF; \
310 int rdHi = (opcode >> 16) & 0xF; \
311 int rs = (opcode >> 8) & 0xF; \
312 int rm = opcode & 0xF; \
313 UNUSED(rdHi); \
314 ARM_WAIT_MUL(cpu->gprs[rs]); \
315 BODY; \
316 S_BODY; \
317 if (rd == ARM_PC) { \
318 ARM_WRITE_PC; \
319 })
320
321#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
322 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
323 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
324
325#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
326 DEFINE_INSTRUCTION_ARM(NAME, \
327 uint32_t address; \
328 int rn = (opcode >> 16) & 0xF; \
329 int rd = (opcode >> 12) & 0xF; \
330 int rm = opcode & 0xF; \
331 UNUSED(rm); \
332 address = ADDRESS; \
333 WRITEBACK; \
334 BODY;)
335
336#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
337 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
338 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
343
344#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
345 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
346 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
355
356#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
369
370#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
373
374#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
375 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
376 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
377 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
378 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
381
382#define ARM_MS_PRE \
383 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
384 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
385
386#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
387
388#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
389#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
390#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
391#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
392#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
393#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
394#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
395#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
396
397#define ARM_M_INCREMENT(BODY) \
398 for (m = rs, i = 0; m; m >>= 1, ++i) { \
399 if (m & 1) { \
400 BODY; \
401 addr += 4; \
402 total += 1; \
403 } \
404 }
405
406#define ARM_M_DECREMENT(BODY) \
407 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
408 if (rs & m) { \
409 BODY; \
410 addr -= 4; \
411 total += 1; \
412 } \
413 }
414
415#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
416 DEFINE_INSTRUCTION_ARM(NAME, \
417 int rn = (opcode >> 16) & 0xF; \
418 int rs = opcode & 0x0000FFFF; \
419 int m; \
420 int i; \
421 int total = 0; \
422 ADDRESS; \
423 S_PRE; \
424 LOOP(BODY); \
425 S_POST; \
426 currentCycles += cpu->memory.waitMultiple(cpu, addr, total); \
427 POST_BODY; \
428 WRITEBACK;)
429
430
431#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
432 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
433 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
434 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
435 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
436 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
437 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
438 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
439 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
448
449// Begin ALU definitions
450
451DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
452 int32_t n = cpu->gprs[rn];
453 cpu->gprs[rd] = n + cpu->shifterOperand;)
454
455DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
456 int32_t n = cpu->gprs[rn];
457 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
458
459DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
460 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
461
462DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
463 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
464
465DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
466 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
467
468DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
469 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
470
471DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
472 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
473
474DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
475 cpu->gprs[rd] = cpu->shifterOperand;)
476
477DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
478 cpu->gprs[rd] = ~cpu->shifterOperand;)
479
480DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
481 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
482
483DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
484 int32_t n = cpu->gprs[rn];
485 cpu->gprs[rd] = cpu->shifterOperand - n;)
486
487DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
488 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
489 cpu->gprs[rd] = cpu->shifterOperand - n;)
490
491DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
492 int32_t n = cpu->gprs[rn];
493 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
494 cpu->gprs[rd] = n - shifterOperand;)
495
496DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
497 int32_t n = cpu->gprs[rn];
498 cpu->gprs[rd] = n - cpu->shifterOperand;)
499
500DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
501 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
502
503DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
504 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
505
506// End ALU definitions
507
508// Begin multiply definitions
509
510DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
511DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
512
513DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
514 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
515 int32_t dm = cpu->gprs[rd];
516 int32_t dn = d;
517 cpu->gprs[rd] = dm + dn;
518 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
519 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
520
521DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
522 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
523 cpu->gprs[rd] = d;
524 cpu->gprs[rdHi] = d >> 32;,
525 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
526
527DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
528 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
529 int32_t dm = cpu->gprs[rd];
530 int32_t dn = d;
531 cpu->gprs[rd] = dm + dn;
532 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
533 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
534
535DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
536 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
537 cpu->gprs[rd] = d;
538 cpu->gprs[rdHi] = d >> 32;,
539 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
540
541// End multiply definitions
542
543// Begin load/store definitions
544
545DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
546DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.loadU8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
547DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.loadU16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
548DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
549DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
550DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
551DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
552DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
553
554DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
555 enum PrivilegeMode priv = cpu->privilegeMode;
556 ARMSetPrivilegeMode(cpu, MODE_USER);
557 cpu->gprs[rd] = cpu->memory.loadU8(cpu, address, ¤tCycles);
558 ARMSetPrivilegeMode(cpu, priv);
559 ARM_LOAD_POST_BODY;)
560
561DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
562 enum PrivilegeMode priv = cpu->privilegeMode;
563 ARMSetPrivilegeMode(cpu, MODE_USER);
564 cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles);
565 ARMSetPrivilegeMode(cpu, priv);
566 ARM_LOAD_POST_BODY;)
567
568DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
569 enum PrivilegeMode priv = cpu->privilegeMode;
570 ARMSetPrivilegeMode(cpu, MODE_USER);
571 cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles);
572 ARMSetPrivilegeMode(cpu, priv);
573 ARM_STORE_POST_BODY;)
574
575DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
576 enum PrivilegeMode priv = cpu->privilegeMode;
577 ARMSetPrivilegeMode(cpu, MODE_USER);
578 cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles);
579 ARMSetPrivilegeMode(cpu, priv);
580 ARM_STORE_POST_BODY;)
581
582DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
583 cpu->gprs[i] = cpu->memory.load32(cpu, addr & 0xFFFFFFFC, 0);,
584 ++currentCycles;
585 if (rs & 0x8000) {
586 ARM_WRITE_PC;
587 })
588
589DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
590 cpu->memory.store32(cpu, addr, cpu->gprs[i], 0);,
591 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
592
593DEFINE_INSTRUCTION_ARM(SWP,
594 int rm = opcode & 0xF;
595 int rd = (opcode >> 12) & 0xF;
596 int rn = (opcode >> 16) & 0xF;
597 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
598 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
599 cpu->gprs[rd] = d;)
600
601DEFINE_INSTRUCTION_ARM(SWPB,
602 int rm = opcode & 0xF;
603 int rd = (opcode >> 12) & 0xF;
604 int rn = (opcode >> 16) & 0xF;
605 int32_t d = cpu->memory.loadU8(cpu, cpu->gprs[rn], ¤tCycles);
606 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
607 cpu->gprs[rd] = d;)
608
609// End load/store definitions
610
611// Begin branch definitions
612
613DEFINE_INSTRUCTION_ARM(B,
614 int32_t offset = opcode << 8;
615 offset >>= 6;
616 cpu->gprs[ARM_PC] += offset;
617 ARM_WRITE_PC;)
618
619DEFINE_INSTRUCTION_ARM(BL,
620 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
621 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
622 cpu->gprs[ARM_PC] += immediate >> 6;
623 ARM_WRITE_PC;)
624
625DEFINE_INSTRUCTION_ARM(BX,
626 int rm = opcode & 0x0000000F;
627 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
628 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
629 if (cpu->executionMode == MODE_THUMB) {
630 THUMB_WRITE_PC;
631 } else {
632 ARM_WRITE_PC;
633 })
634
635// End branch definitions
636
637// Begin coprocessor definitions
638
639DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
640DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
641DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
642DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
643DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
644
645// Begin miscellaneous definitions
646
647DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
648DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
649
650DEFINE_INSTRUCTION_ARM(MSR,
651 int c = opcode & 0x00010000;
652 int f = opcode & 0x00080000;
653 int32_t operand = cpu->gprs[opcode & 0x0000000F];
654 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
655 if (mask & PSR_USER_MASK) {
656 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
657 }
658 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
659 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
660 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
661 }
662 _ARMReadCPSR(cpu);)
663
664DEFINE_INSTRUCTION_ARM(MSRR,
665 int c = opcode & 0x00010000;
666 int f = opcode & 0x00080000;
667 int32_t operand = cpu->gprs[opcode & 0x0000000F];
668 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
669 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
670 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
671
672DEFINE_INSTRUCTION_ARM(MRS, \
673 int rd = (opcode >> 12) & 0xF; \
674 cpu->gprs[rd] = cpu->cpsr.packed;)
675
676DEFINE_INSTRUCTION_ARM(MRSR, \
677 int rd = (opcode >> 12) & 0xF; \
678 cpu->gprs[rd] = cpu->spsr.packed;)
679
680DEFINE_INSTRUCTION_ARM(MSRI,
681 int c = opcode & 0x00010000;
682 int f = opcode & 0x00080000;
683 int rotate = (opcode & 0x00000F00) >> 7;
684 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
685 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
686 if (mask & PSR_USER_MASK) {
687 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
688 }
689 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
690 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
691 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
692 }
693 _ARMReadCPSR(cpu);)
694
695DEFINE_INSTRUCTION_ARM(MSRRI,
696 int c = opcode & 0x00010000;
697 int f = opcode & 0x00080000;
698 int rotate = (opcode & 0x00000F00) >> 7;
699 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
700 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
701 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
702 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
703
704DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
705
706const ARMInstruction _armTable[0x1000] = {
707 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
708};