src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-thumb.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/emitter-thumb.h>
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 cpu->cpsr.n = ARM_SIGN(D); \
16 cpu->cpsr.z = !(D); \
17 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
18 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
19
20#define THUMB_SUBTRACTION_S(M, N, D) \
21 cpu->cpsr.n = ARM_SIGN(D); \
22 cpu->cpsr.z = !(D); \
23 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
24 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
25
26#define THUMB_NEUTRAL_S(M, N, D) \
27 cpu->cpsr.n = ARM_SIGN(D); \
28 cpu->cpsr.z = !(D);
29
30#define THUMB_ADDITION(D, M, N) \
31 int n = N; \
32 int m = M; \
33 D = M + N; \
34 THUMB_ADDITION_S(m, n, D)
35
36#define THUMB_SUBTRACTION(D, M, N) \
37 int n = N; \
38 int m = M; \
39 D = M - N; \
40 THUMB_SUBTRACTION_S(m, n, D)
41
42#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
43
44#define THUMB_LOAD_POST_BODY \
45 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
46
47#define THUMB_STORE_POST_BODY \
48 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
49
50#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
51 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
52 int currentCycles = THUMB_PREFETCH_CYCLES; \
53 BODY; \
54 cpu->cycles += currentCycles; \
55 }
56
57#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
58 DEFINE_INSTRUCTION_THUMB(NAME, \
59 int immediate = (opcode >> 6) & 0x001F; \
60 int rd = opcode & 0x0007; \
61 int rm = (opcode >> 3) & 0x0007; \
62 BODY;)
63
64DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
65 if (!immediate) {
66 cpu->gprs[rd] = cpu->gprs[rm];
67 } else {
68 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
69 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
70 }
71 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
72
73DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
74 if (!immediate) {
75 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
76 cpu->gprs[rd] = 0;
77 } else {
78 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
79 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
80 }
81 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
82
83DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
84 if (!immediate) {
85 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
86 if (cpu->cpsr.c) {
87 cpu->gprs[rd] = 0xFFFFFFFF;
88 } else {
89 cpu->gprs[rd] = 0;
90 }
91 } else {
92 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
93 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
94 }
95 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
96
97DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
98DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
99DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
100DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
103
104#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
105 DEFINE_INSTRUCTION_THUMB(NAME, \
106 int rm = (opcode >> 6) & 0x0007; \
107 int rd = opcode & 0x0007; \
108 int rn = (opcode >> 3) & 0x0007; \
109 BODY;)
110
111DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
112DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
113
114#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
115 DEFINE_INSTRUCTION_THUMB(NAME, \
116 int immediate = (opcode >> 6) & 0x0007; \
117 int rd = opcode & 0x0007; \
118 int rn = (opcode >> 3) & 0x0007; \
119 BODY;)
120
121DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
122DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
123
124#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
125 DEFINE_INSTRUCTION_THUMB(NAME, \
126 int rd = (opcode >> 8) & 0x0007; \
127 int immediate = opcode & 0x00FF; \
128 BODY;)
129
130DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
131DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
132DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
133DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
134
135#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
136 DEFINE_INSTRUCTION_THUMB(NAME, \
137 int rd = opcode & 0x0007; \
138 int rn = (opcode >> 3) & 0x0007; \
139 BODY;)
140
141DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
142DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
143DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
144 int rs = cpu->gprs[rn] & 0xFF;
145 if (rs) {
146 if (rs < 32) {
147 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
148 cpu->gprs[rd] <<= rs;
149 } else {
150 if (rs > 32) {
151 cpu->cpsr.c = 0;
152 } else {
153 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
154 }
155 cpu->gprs[rd] = 0;
156 }
157 }
158 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
159
160DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
161 int rs = cpu->gprs[rn] & 0xFF;
162 if (rs) {
163 if (rs < 32) {
164 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
165 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
166 } else {
167 if (rs > 32) {
168 cpu->cpsr.c = 0;
169 } else {
170 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
171 }
172 cpu->gprs[rd] = 0;
173 }
174 }
175 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
176
177DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
178 int rs = cpu->gprs[rn] & 0xFF;
179 if (rs) {
180 if (rs < 32) {
181 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
182 cpu->gprs[rd] >>= rs;
183 } else {
184 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
185 if (cpu->cpsr.c) {
186 cpu->gprs[rd] = 0xFFFFFFFF;
187 } else {
188 cpu->gprs[rd] = 0;
189 }
190 }
191 }
192 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
193
194DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
195 int n = cpu->gprs[rn];
196 int d = cpu->gprs[rd];
197 cpu->gprs[rd] = d + n + cpu->cpsr.c;
198 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
199
200DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
201 int n = cpu->gprs[rn] + !cpu->cpsr.c;
202 int d = cpu->gprs[rd];
203 cpu->gprs[rd] = d - n;
204 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
206 int rs = cpu->gprs[rn] & 0xFF;
207 if (rs) {
208 int r4 = rs & 0x1F;
209 if (r4 > 0) {
210 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
211 cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
212 } else {
213 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
214 }
215 }
216 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
217DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
218DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
219DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
220DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
221DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
222DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
224DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
225
226#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
227 DEFINE_INSTRUCTION_THUMB(NAME, \
228 int rd = (opcode & 0x0007) | H1; \
229 int rm = ((opcode >> 3) & 0x0007) | H2; \
230 BODY;)
231
232#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
233 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
234 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
235 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
236 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
237
238DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
239 cpu->gprs[rd] += cpu->gprs[rm];
240 if (rd == ARM_PC) {
241 currentCycles += ThumbWritePC(cpu);
242 })
243
244DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
245DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
246 cpu->gprs[rd] = cpu->gprs[rm];
247 if (rd == ARM_PC) {
248 currentCycles += ThumbWritePC(cpu);
249 })
250
251#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
252 DEFINE_INSTRUCTION_THUMB(NAME, \
253 int rd = (opcode >> 8) & 0x0007; \
254 int immediate = (opcode & 0x00FF) << 2; \
255 BODY;)
256
257DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
258DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
259DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
260
261DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
262DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
263
264#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
265 DEFINE_INSTRUCTION_THUMB(NAME, \
266 int rm = (opcode >> 6) & 0x0007; \
267 int rd = opcode & 0x0007; \
268 int rn = (opcode >> 3) & 0x0007; \
269 BODY;)
270
271DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
272DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
273DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
274DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
275DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, rm = cpu->gprs[rn] + cpu->gprs[rm]; cpu->gprs[rd] = rm & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, rm, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, rm, ¤tCycles)); THUMB_LOAD_POST_BODY;)
276DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
277DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
278DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
279
280#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
281 DEFINE_INSTRUCTION_THUMB(NAME, \
282 int rn = RN; \
283 UNUSED(rn); \
284 int rs = opcode & 0xFF; \
285 int32_t address = cpu->gprs[RN]; \
286 PRE_BODY; \
287 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
288 WRITEBACK;)
289
290DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
291 (opcode >> 8) & 0x0007,
292 load,
293 IA,
294 ,
295 THUMB_LOAD_POST_BODY;
296 if (!((1 << rn) & rs)) {
297 cpu->gprs[rn] = address;
298 })
299
300DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
301 (opcode >> 8) & 0x0007,
302 store,
303 IA,
304 ,
305 THUMB_STORE_POST_BODY;
306 cpu->gprs[rn] = address;)
307
308#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
309 DEFINE_INSTRUCTION_THUMB(B ## COND, \
310 if (ARM_COND_ ## COND) { \
311 int8_t immediate = opcode; \
312 cpu->gprs[ARM_PC] += (int32_t) immediate << 1; \
313 currentCycles += ThumbWritePC(cpu); \
314 })
315
316DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
317DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
318DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
319DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
320DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
321DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
322DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
323DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
324DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
325DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
326DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
327DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
328DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
329DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
330
331DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
332DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
333
334DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
335 ARM_SP,
336 load,
337 IA,
338 ,
339 THUMB_LOAD_POST_BODY;
340 cpu->gprs[ARM_SP] = address)
341
342DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
343 ARM_SP,
344 load,
345 IA,
346 rs |= 1 << ARM_PC,
347 THUMB_LOAD_POST_BODY;
348 cpu->gprs[ARM_SP] = address;
349 currentCycles += ThumbWritePC(cpu);)
350
351DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
352 ARM_SP,
353 store,
354 DB,
355 ,
356 THUMB_STORE_POST_BODY;
357 cpu->gprs[ARM_SP] = address)
358
359DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
360 ARM_SP,
361 store,
362 DB,
363 rs |= 1 << ARM_LR,
364 THUMB_STORE_POST_BODY;
365 cpu->gprs[ARM_SP] = address)
366
367DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
368DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
369DEFINE_INSTRUCTION_THUMB(B,
370 int16_t immediate = (opcode & 0x07FF) << 5;
371 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
372 currentCycles += ThumbWritePC(cpu);)
373
374DEFINE_INSTRUCTION_THUMB(BL1,
375 int16_t immediate = (opcode & 0x07FF) << 5;
376 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
377
378DEFINE_INSTRUCTION_THUMB(BL2,
379 uint16_t immediate = (opcode & 0x07FF) << 1;
380 uint32_t pc = cpu->gprs[ARM_PC];
381 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
382 cpu->gprs[ARM_LR] = pc - 1;
383 currentCycles += ThumbWritePC(cpu);)
384
385DEFINE_INSTRUCTION_THUMB(BX,
386 int rm = (opcode >> 3) & 0xF;
387 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
388 int misalign = 0;
389 if (rm == ARM_PC) {
390 misalign = cpu->gprs[rm] & 0x00000002;
391 }
392 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
393 if (cpu->executionMode == MODE_THUMB) {
394 currentCycles += ThumbWritePC(cpu);
395 } else {
396 currentCycles += ARMWritePC(cpu);
397 })
398
399DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
400
401const ThumbInstruction _thumbTable[0x400] = {
402 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
403};