src/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
14 // TODO
15}
16
17static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
18 int rotate = (opcode & 0x00000F00) >> 7;
19 int immediate = opcode & 0x000000FF;
20 if (!rotate) {
21 cpu->shifterOperand = immediate;
22 cpu->shifterCarryOut = cpu->cpsr.c;
23 } else {
24 cpu->shifterOperand = ARM_ROR(immediate, rotate);
25 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
26 }
27}
28
29static const ARMInstruction _armTable[0x1000];
30
31static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
32 uint32_t opcode = memory->load32(memory, address);
33 *opcodeOut = opcode;
34 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
35}
36
37void ARMStep(struct ARMCore* cpu) {
38 // TODO
39 uint32_t opcode;
40 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
41 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
42
43 int condition = opcode >> 28;
44 if (condition == 0xE) {
45 instruction(cpu, opcode);
46 } else {
47 switch (condition) {
48 case 0x0:
49 if (!ARM_COND_EQ) {
50 return;
51 }
52 break;
53 case 0x1:
54 if (!ARM_COND_NE) {
55 return;
56 }
57 break;
58 case 0x2:
59 if (!ARM_COND_CS) {
60 return;
61 }
62 break;
63 case 0x3:
64 if (!ARM_COND_CC) {
65 return;
66 }
67 break;
68 case 0x4:
69 if (!ARM_COND_MI) {
70 return;
71 }
72 break;
73 case 0x5:
74 if (!ARM_COND_PL) {
75 return;
76 }
77 break;
78 case 0x6:
79 if (!ARM_COND_VS) {
80 return;
81 }
82 break;
83 case 0x7:
84 if (!ARM_COND_VC) {
85 return;
86 }
87 break;
88 case 0x8:
89 if (!ARM_COND_HI) {
90 return;
91 }
92 break;
93 case 0x9:
94 if (!ARM_COND_LS) {
95 return;
96 }
97 break;
98 case 0xA:
99 if (!ARM_COND_GE) {
100 return;
101 }
102 break;
103 case 0xB:
104 if (!ARM_COND_LT) {
105 return;
106 }
107 break;
108 case 0xC:
109 if (!ARM_COND_GT) {
110 return;
111 }
112 break;
113 case 0xD:
114 if (!ARM_COND_GE) {
115 return;
116 }
117 break;
118 default:
119 break;
120 }
121 }
122 instruction(cpu, opcode);
123}
124
125// Instruction definitions
126// Beware pre-processor antics
127
128#define ARM_WRITE_PC \
129 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM
130
131#define ARM_ADDITION_S(M, N, D) \
132 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
133 cpu->cpsr = cpu->spsr; \
134 _ARMReadCPSR(cpu); \
135 } else { \
136 cpu->cpsr.n = ARM_SIGN(D); \
137 cpu->cpsr.z = !(D); \
138 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
139 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
140 }
141
142#define ARM_SUBTRACTION_S(M, N, D) \
143 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
144 cpu->cpsr = cpu->spsr; \
145 _ARMReadCPSR(cpu); \
146 } else { \
147 cpu->cpsr.n = ARM_SIGN(D); \
148 cpu->cpsr.z = !(D); \
149 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
150 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
151 }
152
153#define ARM_NEUTRAL_S(M, N, D) \
154 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
155 cpu->cpsr = cpu->spsr; \
156 _ARMReadCPSR(cpu); \
157 } else { \
158 cpu->cpsr.n = ARM_SIGN(D); \
159 cpu->cpsr.z = !(D); \
160 cpu->cpsr.c = cpu->shifterCarryOut; \
161 }
162
163#define ADDR_MODE_2_ADDRESS (address)
164#define ADDR_MODE_2_RN (cpu->gprs[rn])
165#define ADDR_MODE_2_RM (cpu->gprs[rm])
166#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
167#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
168#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
169#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
170#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
171#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
172#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
173
174#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
175#define ADDR_MODE_3_RN ADDR_MODE_2_RN
176#define ADDR_MODE_3_RM ADDR_MODE_2_RM
177#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
178#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
179#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
180
181#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
182 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
183 BODY; \
184 }
185
186#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
187 DEFINE_INSTRUCTION_ARM(NAME, \
188 int rd = (opcode >> 12) & 0xF; \
189 int rn = (opcode >> 16) & 0xF; \
190 SHIFTER(cpu, opcode); \
191 BODY; \
192 S_BODY; \
193 POST_BODY; \
194 if (rd == ARM_PC) { \
195 ARM_WRITE_PC; \
196 })
197
198#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
199 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
200 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
201 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
202 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
203
204#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
205 DEFINE_INSTRUCTION_ARM(NAME, \
206 uint32_t address; \
207 int rn = (opcode >> 16) & 0xF; \
208 int rd = (opcode >> 12) & 0xF; \
209 int rm = opcode & 0xF; \
210 address = ADDRESS; \
211 BODY; \
212 WRITEBACK;)
213
214#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
215 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
216 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
217 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
218 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
219 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
220 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
221
222
223#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
224 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
225 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
226 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
227 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
228 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
229 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
230 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
231 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
232 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
233 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
234
235#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
236 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
237 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
238 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
239 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
240 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
241 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
242 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
243 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
244 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
245 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
246 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
247 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
248
249// TODO
250#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
251 DEFINE_INSTRUCTION_ARM(NAME, \
252 BODY;)
253
254#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
255 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
256 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
257 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
258 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
259 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
260 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
261 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
262 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
263 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
264 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
265 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
266 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
267 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
268 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
269 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
270 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
271
272// Begin ALU definitions
273
274DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
275 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
276
277DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
278 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
279 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
280
281DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
282 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
283
284DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
285 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
286
287DEFINE_ALU_INSTRUCTION_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
288 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
289
290DEFINE_ALU_INSTRUCTION_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
291 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
292
293DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
294 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
295
296DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
297 cpu->gprs[rd] = cpu->shifterOperand;, )
298
299DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
300 cpu->gprs[rd] = ~cpu->shifterOperand;, )
301
302DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
303 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
304
305DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
306 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
307
308DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
309 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
310 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
311
312DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
313 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
314 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
315
316DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
317 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
318
319DEFINE_ALU_INSTRUCTION_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
320 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
321
322DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
323 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
324
325// End ALU definitions
326
327// Begin multiply definitions
328
329DEFINE_INSTRUCTION_ARM(MLA,)
330DEFINE_INSTRUCTION_ARM(MLAS,)
331DEFINE_INSTRUCTION_ARM(MUL,)
332DEFINE_INSTRUCTION_ARM(MULS,)
333DEFINE_INSTRUCTION_ARM(SMLAL,)
334DEFINE_INSTRUCTION_ARM(SMLALS,)
335DEFINE_INSTRUCTION_ARM(SMULL,)
336DEFINE_INSTRUCTION_ARM(SMULLS,)
337DEFINE_INSTRUCTION_ARM(UMLAL,)
338DEFINE_INSTRUCTION_ARM(UMLALS,)
339DEFINE_INSTRUCTION_ARM(UMULL,)
340DEFINE_INSTRUCTION_ARM(UMULLS,)
341
342// End multiply definitions
343
344// Begin load/store definitions
345
346DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
347DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
348DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRBT,)
349DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
350DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
351DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
352DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRT,)
353DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
354DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
355DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRBT,)
356DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
357DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRT,)
358
359DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,)
360DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,)
361
362DEFINE_INSTRUCTION_ARM(SWP,)
363DEFINE_INSTRUCTION_ARM(SWPB,)
364
365// End load/store definitions
366
367// Begin branch definitions
368
369DEFINE_INSTRUCTION_ARM(B, \
370 int32_t offset = opcode << 8; \
371 offset >>= 6; \
372 cpu->gprs[ARM_PC] += offset; \
373 ARM_WRITE_PC;)
374
375DEFINE_INSTRUCTION_ARM(BL,)
376DEFINE_INSTRUCTION_ARM(BX,)
377
378// End branch definitions
379
380// TODO
381DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
382
383DEFINE_INSTRUCTION_ARM(MSR, \
384 int c = opcode & 0x00010000; \
385 int f = opcode & 0x00080000; \
386 int32_t operand; \
387 if (opcode & 0x02000000) { \
388 int rotate = (opcode & 0x00000F00) >> 8; \
389 operand = ARM_ROR(opcode & 0x000000FF, rotate); \
390 } else { \
391 operand = cpu->gprs[opcode & 0x0000000F]; \
392 } \
393 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \
394 if (opcode & 0x00400000) { \
395 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \
396 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \
397 } else { \
398 if (mask & PSR_USER_MASK) { \
399 cpu->cpsr.n = operand & 0x80000000; \
400 cpu->cpsr.z = operand & 0x40000000; \
401 cpu->cpsr.c = operand & 0x20000000; \
402 cpu->cpsr.v = operand & 0x10000000; \
403 } \
404 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \
405 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \
406 cpu->cpsr.i = operand & 0x00000080; \
407 cpu->cpsr.f = operand & 0x00000040; \
408 } \
409 })
410
411DEFINE_INSTRUCTION_ARM(MRS,)
412DEFINE_INSTRUCTION_ARM(MSRI,)
413DEFINE_INSTRUCTION_ARM(MRSI,)
414DEFINE_INSTRUCTION_ARM(SWI,)
415
416#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
417 EMITTER ## NAME
418
419#define DO_8(DIRECTIVE) \
420 DIRECTIVE, \
421 DIRECTIVE, \
422 DIRECTIVE, \
423 DIRECTIVE, \
424 DIRECTIVE, \
425 DIRECTIVE, \
426 DIRECTIVE, \
427 DIRECTIVE
428
429#define DO_256(DIRECTIVE) \
430 DO_8(DO_8(DIRECTIVE)), \
431 DO_8(DO_8(DIRECTIVE)), \
432 DO_8(DO_8(DIRECTIVE)), \
433 DO_8(DO_8(DIRECTIVE))
434
435#define DO_INTERLACE(LEFT, RIGHT) \
436 LEFT, \
437 RIGHT
438
439#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
440 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
441 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
442
443#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
444 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
445 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
446 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
447 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
448 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
449 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
450 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
451 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
452 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
453
454#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
455 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
456 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
457
458#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
459 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
460 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
461 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
462 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
463 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
464 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
465 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
466 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
467 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
468 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
469 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
470 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
471 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
472 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
473 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
474 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
475
476#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
477 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
478 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
479
480#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
481 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
482
483// TODO: Support coprocessors
484#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
485 DO_8(0), \
486 DO_8(0)
487
488#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
489 DO_8(DO_8(DO_INTERLACE(0, 0))), \
490 DO_8(DO_8(DO_INTERLACE(0, 0)))
491
492#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
493 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
494
495#define DECLARE_EMITTER_BLOCK(EMITTER) \
496 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
497 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
498 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
499 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
500 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
501 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
502 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
503 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
504 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
505 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
506 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
507 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
508 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
509 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
510 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
511 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
512 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
513 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
514 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
515 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
516 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
517 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
518 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
519 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
520 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
521 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
522 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
523 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
524 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
525 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
526 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
527 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
528 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
529 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
530 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
531 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
532 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
533 DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
534 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
535 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
536 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
537 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
538 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
539 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
540 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
541 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
542 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
543 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
544 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
545 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
546 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
547 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
548 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
549 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
550 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
551 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
552 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
553 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
554 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
555 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
556 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
557 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
558 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
559 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
560 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
561 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
562 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
563 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
564 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
565 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
566 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
567 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
568 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
569 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
570 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
571 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
572 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
573 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
574 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
575 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
576 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
577 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
578 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
579 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
580 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
581 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
582 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
583 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
584 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
585 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
586 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
587 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
588 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
589 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
590 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
591 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
592 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
593 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
594 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
595 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
596 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
597 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
598 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
599 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
600 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
601 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
602 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
603 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
604 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
605 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
606 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
607 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
608 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
609 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
610 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
611 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
612 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
613 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
614 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
615 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
616 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
617 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
618 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
619 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
620 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
621 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
622 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
623 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
624 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
625 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
626 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
627 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
628 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
629 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
630 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
631 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
632 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
633 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
634 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
635 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
636 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
637 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
638 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
639 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
640 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
641 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
642 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
643 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
644 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
645 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
646 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
647 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
648 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
649 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
650 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
651 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
652 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
653 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
654 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
655 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
656 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
657 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
658 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
659 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
660 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
661 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
662 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
663 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
664 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
665 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
666 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
667 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
668 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
669 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
670 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
671 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
672 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
673 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
674 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
675 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
676 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
677 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
678 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
679 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
680 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
681 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
682 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
683 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
684 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
685 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
686 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
687 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
688 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
689 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
690 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
691 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
692 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
693 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
694 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
695 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
696 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
697 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
698 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
699 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
700 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
701 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
702 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
703 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
704 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
705 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
706 DECLARE_ARM_SWI_BLOCK(EMITTER)
707
708static const ARMInstruction _armTable[0x1000] = {
709 DECLARE_EMITTER_BLOCK(_ARMInstruction)
710};