src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "util/memory.h"
8
9static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
10static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count);
11static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
12
13static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
14static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
17static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
18static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
19static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
20
21void GBAMemoryInit(struct GBA* gba) {
22 struct ARMCore* cpu = gba->cpu;
23 cpu->memory.load32 = GBALoad32;
24 cpu->memory.load16 = GBALoad16;
25 cpu->memory.loadU16 = GBALoadU16;
26 cpu->memory.load8 = GBALoad8;
27 cpu->memory.loadU8 = GBALoadU8;
28 cpu->memory.store32 = GBAStore32;
29 cpu->memory.store16 = GBAStore16;
30 cpu->memory.store8 = GBAStore8;
31
32 gba->memory.bios = (uint32_t*) hleBios;
33 gba->memory.fullBios = 0;
34 gba->memory.wram = 0;
35 gba->memory.iwram = 0;
36 gba->memory.rom = 0;
37 gba->memory.gpio.p = gba;
38
39 int i;
40 for (i = 0; i < 16; ++i) {
41 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
42 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
43 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
44 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
45 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
46 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
47 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
48 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
49 }
50 for (; i < 256; ++i) {
51 gba->memory.waitstatesNonseq16[i] = 0;
52 gba->memory.waitstatesSeq16[i] = 0;
53 gba->memory.waitstatesNonseq32[i] = 0;
54 gba->memory.waitstatesSeq32[i] = 0;
55 }
56
57 gba->memory.activeRegion = -1;
58 cpu->memory.activeRegion = 0;
59 cpu->memory.activeMask = 0;
60 cpu->memory.setActiveRegion = GBASetActiveRegion;
61 cpu->memory.activeSeqCycles32 = 0;
62 cpu->memory.activeSeqCycles16 = 0;
63 cpu->memory.activeNonseqCycles32 = 0;
64 cpu->memory.activeNonseqCycles16 = 0;
65 cpu->memory.activeUncachedCycles32 = 0;
66 cpu->memory.activeUncachedCycles16 = 0;
67 gba->memory.biosPrefetch = 0;
68 cpu->memory.waitMultiple = GBAWaitMultiple;
69}
70
71void GBAMemoryDeinit(struct GBA* gba) {
72 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
73 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
74 if (gba->memory.rom) {
75 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
76 }
77 GBASavedataDeinit(&gba->memory.savedata);
78}
79
80void GBAMemoryReset(struct GBA* gba) {
81 if (gba->memory.wram) {
82 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
83 }
84 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
85
86 if (gba->memory.iwram) {
87 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
88 }
89 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
90
91 memset(gba->memory.io, 0, sizeof(gba->memory.io));
92 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
93 int i;
94 for (i = 0; i < 4; ++i) {
95 gba->memory.dma[i].count = 0x10000;
96 gba->memory.dma[i].nextEvent = INT_MAX;
97 }
98 gba->memory.activeDMA = -1;
99 gba->memory.nextDMA = INT_MAX;
100 gba->memory.eventDiff = 0;
101
102 if (!gba->memory.wram || !gba->memory.iwram) {
103 GBAMemoryDeinit(gba);
104 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
105 }
106}
107
108static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
109 struct GBA* gba = (struct GBA*) cpu->master;
110 struct GBAMemory* memory = &gba->memory;
111
112 int newRegion = address >> BASE_OFFSET;
113 if (newRegion == memory->activeRegion) {
114 return;
115 }
116 if (memory->activeRegion == REGION_BIOS) {
117 memory->biosPrefetch = cpu->prefetch;
118 }
119 memory->activeRegion = newRegion;
120 switch (address & ~OFFSET_MASK) {
121 case BASE_BIOS:
122 cpu->memory.activeRegion = memory->bios;
123 cpu->memory.activeMask = SIZE_BIOS - 1;
124 break;
125 case BASE_WORKING_RAM:
126 cpu->memory.activeRegion = memory->wram;
127 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
128 break;
129 case BASE_WORKING_IRAM:
130 cpu->memory.activeRegion = memory->iwram;
131 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
132 break;
133 case BASE_CART0:
134 case BASE_CART0_EX:
135 case BASE_CART1:
136 case BASE_CART1_EX:
137 case BASE_CART2:
138 case BASE_CART2_EX:
139 cpu->memory.activeRegion = memory->rom;
140 cpu->memory.activeMask = SIZE_CART0 - 1;
141 break;
142 default:
143 cpu->memory.activeRegion = 0;
144 cpu->memory.activeMask = 0;
145 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
146 break;
147 }
148 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
149 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
150 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
151 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
152 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
153 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
154}
155
156int32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
157 struct GBA* gba = (struct GBA*) cpu->master;
158 struct GBAMemory* memory = &gba->memory;
159 uint32_t value = 0;
160 int wait = 0;
161
162 switch (address & ~OFFSET_MASK) {
163 case BASE_BIOS:
164 if (cpu->gprs[ARM_PC] >> BASE_OFFSET == REGION_BIOS) {
165 if (address < SIZE_BIOS) {
166 LOAD_32(value, address, memory->bios);
167 } else {
168 value = 0;
169 }
170 } else {
171 value = memory->biosPrefetch;
172 }
173 break;
174 case BASE_WORKING_RAM:
175 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
176 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
177 break;
178 case BASE_WORKING_IRAM:
179 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
180 break;
181 case BASE_IO:
182 value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
183 break;
184 case BASE_PALETTE_RAM:
185 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
186 break;
187 case BASE_VRAM:
188 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
189 break;
190 case BASE_OAM:
191 LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
192 break;
193 case BASE_CART0:
194 case BASE_CART0_EX:
195 case BASE_CART1:
196 case BASE_CART1_EX:
197 case BASE_CART2:
198 case BASE_CART2_EX:
199 wait = memory->waitstatesNonseq32[address >> BASE_OFFSET];
200 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
201 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom);
202 }
203 break;
204 case BASE_CART_SRAM:
205 case BASE_CART_SRAM_MIRROR:
206 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
207 break;
208 default:
209 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
210 value = cpu->prefetch;
211 if (cpu->executionMode == MODE_THUMB) {
212 value |= value << 16;
213 }
214 break;
215 }
216
217
218 if (cycleCounter) {
219 *cycleCounter += 2 + wait;
220 }
221 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
222 int rotate = (address & 3) << 3;
223 return (value >> rotate) | (value << (32 - rotate));
224}
225
226uint16_t GBALoadU16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
227 return GBALoad16(cpu, address, cycleCounter);
228}
229
230int16_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
231 struct GBA* gba = (struct GBA*) cpu->master;
232 struct GBAMemory* memory = &gba->memory;
233 uint16_t value = 0;
234 int wait = 0;
235
236 switch (address & ~OFFSET_MASK) {
237 case BASE_BIOS:
238 if (cpu->gprs[ARM_PC] >> BASE_OFFSET == REGION_BIOS) {
239 if (address < SIZE_BIOS) {
240 LOAD_16(value, address, memory->bios);
241 } else {
242 value = 0;
243 }
244 } else {
245 value = memory->biosPrefetch;
246 }
247 break;
248 case BASE_WORKING_RAM:
249 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
250 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
251 break;
252 case BASE_WORKING_IRAM:
253 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
254 break;
255 case BASE_IO:
256 value = GBAIORead(gba, address & (SIZE_IO - 1));
257 break;
258 case BASE_PALETTE_RAM:
259 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
260 break;
261 case BASE_VRAM:
262 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
263 break;
264 case BASE_OAM:
265 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
266 break;
267 case BASE_CART0:
268 case BASE_CART0_EX:
269 case BASE_CART1:
270 case BASE_CART1_EX:
271 case BASE_CART2:
272 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
273 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
274 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
275 }
276 break;
277 case BASE_CART2_EX:
278 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
279 if (memory->savedata.type == SAVEDATA_EEPROM) {
280 value = GBASavedataReadEEPROM(&memory->savedata);
281 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
282 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
283 }
284 break;
285 case BASE_CART_SRAM:
286 case BASE_CART_SRAM_MIRROR:
287 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
288 break;
289 default:
290 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
291 value = cpu->prefetch;
292 break;
293 }
294
295 if (cycleCounter) {
296 *cycleCounter += 2 + wait;
297 }
298 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
299 int rotate = (address & 1) << 3;
300 return (value >> rotate) | (value << (16 - rotate));
301}
302
303uint8_t GBALoadU8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
304 return GBALoad8(cpu, address, cycleCounter);
305}
306
307int8_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
308 struct GBA* gba = (struct GBA*) cpu->master;
309 struct GBAMemory* memory = &gba->memory;
310 int8_t value = 0;
311 int wait = 0;
312
313 switch (address & ~OFFSET_MASK) {
314 case BASE_BIOS:
315 if (cpu->gprs[ARM_PC] >> BASE_OFFSET == REGION_BIOS) {
316 if (address < SIZE_BIOS) {
317 value = ((int8_t*) memory->bios)[address];
318 } else {
319 value = 0;
320 }
321 } else {
322 value = memory->biosPrefetch;
323 }
324 break;
325 case BASE_WORKING_RAM:
326 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
327 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
328 break;
329 case BASE_WORKING_IRAM:
330 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
331 break;
332 case BASE_IO:
333 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
334 break;
335 case BASE_PALETTE_RAM:
336 value = ((int8_t*) gba->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
337 break;
338 case BASE_VRAM:
339 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
340 break;
341 case BASE_OAM:
342 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
343 break;
344 case BASE_CART0:
345 case BASE_CART0_EX:
346 case BASE_CART1:
347 case BASE_CART1_EX:
348 case BASE_CART2:
349 case BASE_CART2_EX:
350 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
351 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
352 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
353 }
354 break;
355 case BASE_CART_SRAM:
356 case BASE_CART_SRAM_MIRROR:
357 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
358 if (memory->savedata.type == SAVEDATA_NONE) {
359 GBASavedataInitSRAM(&memory->savedata);
360 }
361 if (memory->savedata.type == SAVEDATA_SRAM) {
362 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
363 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
364 value = GBASavedataReadFlash(&memory->savedata, address);
365 }
366 break;
367 default:
368 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
369 value = cpu->prefetch & 0xFF;
370 break;
371 }
372
373 if (cycleCounter) {
374 *cycleCounter += 2 + wait;
375 }
376 return value;
377}
378
379void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
380 struct GBA* gba = (struct GBA*) cpu->master;
381 struct GBAMemory* memory = &gba->memory;
382 int wait = 0;
383
384 switch (address & ~OFFSET_MASK) {
385 case BASE_WORKING_RAM:
386 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
387 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
388 break;
389 case BASE_WORKING_IRAM:
390 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
391 break;
392 case BASE_IO:
393 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
394 break;
395 case BASE_PALETTE_RAM:
396 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
397 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
398 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
399 break;
400 case BASE_VRAM:
401 if ((address & OFFSET_MASK) < SIZE_VRAM) {
402 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
403 } else if ((address & OFFSET_MASK) < 0x00020000) {
404 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
405 }
406 break;
407 case BASE_OAM:
408 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
409 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
410 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
411 break;
412 case BASE_CART0:
413 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
414 break;
415 case BASE_CART_SRAM:
416 case BASE_CART_SRAM_MIRROR:
417 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
418 break;
419 default:
420 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
421 break;
422 }
423
424 if (cycleCounter) {
425 *cycleCounter += 1 + wait;
426 }
427}
428
429void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
430 struct GBA* gba = (struct GBA*) cpu->master;
431 struct GBAMemory* memory = &gba->memory;
432 int wait = 0;
433
434 switch (address & ~OFFSET_MASK) {
435 case BASE_WORKING_RAM:
436 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
437 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
438 break;
439 case BASE_WORKING_IRAM:
440 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
441 break;
442 case BASE_IO:
443 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
444 break;
445 case BASE_PALETTE_RAM:
446 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
447 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
448 break;
449 case BASE_VRAM:
450 if ((address & OFFSET_MASK) < SIZE_VRAM) {
451 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
452 } else if ((address & OFFSET_MASK) < 0x00020000) {
453 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
454 }
455 break;
456 case BASE_OAM:
457 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
458 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
459 break;
460 case BASE_CART0:
461 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
462 uint32_t reg = address & 0xFFFFFF;
463 GBAGPIOWrite(&memory->gpio, reg, value);
464 } else {
465 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
466 }
467 break;
468 case BASE_CART2_EX:
469 if (memory->savedata.type == SAVEDATA_NONE) {
470 GBASavedataInitEEPROM(&memory->savedata);
471 }
472 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
473 break;
474 case BASE_CART_SRAM:
475 case BASE_CART_SRAM_MIRROR:
476 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
477 break;
478 default:
479 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
480 break;
481 }
482
483 if (cycleCounter) {
484 *cycleCounter += 1 + wait;
485 }
486}
487
488void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
489 struct GBA* gba = (struct GBA*) cpu->master;
490 struct GBAMemory* memory = &gba->memory;
491 int wait = 0;
492
493 switch (address & ~OFFSET_MASK) {
494 case BASE_WORKING_RAM:
495 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
496 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
497 break;
498 case BASE_WORKING_IRAM:
499 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
500 break;
501 case BASE_IO:
502 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
503 break;
504 case BASE_PALETTE_RAM:
505 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
506 break;
507 case BASE_VRAM:
508 if (address >= 0x06018000) {
509 // TODO: check BG mode
510 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
511 break;
512 }
513 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
514 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
515 break;
516 case BASE_OAM:
517 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
518 break;
519 case BASE_CART0:
520 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
521 break;
522 case BASE_CART_SRAM:
523 case BASE_CART_SRAM_MIRROR:
524 if (memory->savedata.type == SAVEDATA_NONE) {
525 if (address == SAVEDATA_FLASH_BASE) {
526 GBASavedataInitFlash(&memory->savedata);
527 } else {
528 GBASavedataInitSRAM(&memory->savedata);
529 }
530 }
531 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
532 GBASavedataWriteFlash(&memory->savedata, address, value);
533 } else if (memory->savedata.type == SAVEDATA_SRAM) {
534 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
535 }
536 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
537 break;
538 default:
539 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
540 break;
541 }
542
543 if (cycleCounter) {
544 *cycleCounter += 1 + wait;
545 }
546}
547
548static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count) {
549 struct GBA* gba = (struct GBA*) cpu->master;
550 struct GBAMemory* memory = &gba->memory;
551 int wait = 1 + memory->waitstatesNonseq32[startAddress >> BASE_OFFSET];
552 wait += (1 + memory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
553 return wait;
554}
555
556void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
557 struct GBAMemory* memory = &gba->memory;
558 struct ARMCore* cpu = gba->cpu;
559 int sram = parameters & 0x0003;
560 int ws0 = (parameters & 0x000C) >> 2;
561 int ws0seq = (parameters & 0x0010) >> 4;
562 int ws1 = (parameters & 0x0060) >> 5;
563 int ws1seq = (parameters & 0x0080) >> 7;
564 int ws2 = (parameters & 0x0300) >> 8;
565 int ws2seq = (parameters & 0x0400) >> 10;
566 int prefetch = parameters & 0x4000;
567
568 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
569 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
570 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
571 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
572
573 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
574 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
575 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
576
577 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
578 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
579 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
580
581 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
582 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
583 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
584
585 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
586 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
587 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
588
589 if (!prefetch) {
590 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
591 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
592 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
593
594 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
595 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
596 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
597
598 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
599 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
600 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
601
602 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
603 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
604 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
605 } else {
606 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
607 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
608 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
609
610 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
611 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
612 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
613
614 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
615 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
616 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
617
618 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
619 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
620 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
621 }
622
623 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
624 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
625
626 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
627 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
628
629 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
630 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
631}
632
633void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
634 struct GBAMemory* memory = &gba->memory;
635 memory->dma[dma].source = address & 0xFFFFFFFE;
636}
637
638void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
639 struct GBAMemory* memory = &gba->memory;
640 memory->dma[dma].dest = address & 0xFFFFFFFE;
641}
642
643void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
644 struct GBAMemory* memory = &gba->memory;
645 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
646}
647
648uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
649 struct GBAMemory* memory = &gba->memory;
650 struct GBADMA* currentDma = &memory->dma[dma];
651 int wasEnabled = currentDma->enable;
652 currentDma->packed = control;
653
654 if (currentDma->drq) {
655 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
656 }
657
658 if (!wasEnabled && currentDma->enable) {
659 currentDma->nextSource = currentDma->source;
660 currentDma->nextDest = currentDma->dest;
661 currentDma->nextCount = currentDma->count;
662 GBAMemoryScheduleDMA(gba, dma, currentDma);
663 }
664 // If the DMA has already occurred, this value might have changed since the function started
665 return currentDma->packed;
666};
667
668void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
669 struct ARMCore* cpu = gba->cpu;
670 switch (info->timing) {
671 case DMA_TIMING_NOW:
672 info->nextEvent = cpu->cycles;
673 GBAMemoryUpdateDMAs(gba, 0);
674 break;
675 case DMA_TIMING_HBLANK:
676 // Handled implicitly
677 info->nextEvent = INT_MAX;
678 break;
679 case DMA_TIMING_VBLANK:
680 // Handled implicitly
681 info->nextEvent = INT_MAX;
682 break;
683 case DMA_TIMING_CUSTOM:
684 info->nextEvent = INT_MAX;
685 switch (number) {
686 case 0:
687 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
688 break;
689 case 1:
690 case 2:
691 GBAAudioScheduleFifoDma(&gba->audio, number, info);
692 break;
693 case 3:
694 // GBAVideoScheduleVCaptureDma(dma, info);
695 break;
696 }
697 }
698}
699
700void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
701 struct GBAMemory* memory = &gba->memory;
702 struct GBADMA* dma;
703 int i;
704 for (i = 0; i < 4; ++i) {
705 dma = &memory->dma[i];
706 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
707 dma->nextEvent = cycles;
708 }
709 }
710 GBAMemoryUpdateDMAs(gba, 0);
711}
712
713void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
714 struct GBAMemory* memory = &gba->memory;
715 struct GBADMA* dma;
716 int i;
717 for (i = 0; i < 4; ++i) {
718 dma = &memory->dma[i];
719 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
720 dma->nextEvent = cycles;
721 }
722 }
723 GBAMemoryUpdateDMAs(gba, 0);
724}
725
726int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
727 struct GBAMemory* memory = &gba->memory;
728 if (memory->nextDMA == INT_MAX) {
729 return INT_MAX;
730 }
731 memory->nextDMA -= cycles;
732 memory->eventDiff += cycles;
733 if (memory->nextDMA <= 0) {
734 struct GBADMA* dma = &memory->dma[memory->activeDMA];
735 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
736 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
737 memory->eventDiff = 0;
738 }
739 return memory->nextDMA;
740}
741
742void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
743 int i;
744 struct GBAMemory* memory = &gba->memory;
745 struct ARMCore* cpu = gba->cpu;
746 memory->activeDMA = -1;
747 memory->nextDMA = INT_MAX;
748 for (i = 3; i >= 0; --i) {
749 struct GBADMA* dma = &memory->dma[i];
750 if (dma->nextEvent != INT_MAX) {
751 dma->nextEvent -= cycles;
752 if (dma->enable) {
753 memory->activeDMA = i;
754 memory->nextDMA = dma->nextEvent;
755 }
756 }
757 }
758 if (memory->nextDMA < cpu->nextEvent) {
759 cpu->nextEvent = memory->nextDMA;
760 }
761}
762
763void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
764 struct GBAMemory* memory = &gba->memory;
765 struct ARMCore* cpu = gba->cpu;
766 uint32_t width = info->width ? 4 : 2;
767 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
768 int destOffset = DMA_OFFSET[info->dstControl] * width;
769 int32_t wordsRemaining = info->nextCount;
770 uint32_t source = info->nextSource;
771 uint32_t dest = info->nextDest;
772 uint32_t sourceRegion = source >> BASE_OFFSET;
773 uint32_t destRegion = dest >> BASE_OFFSET;
774 int32_t cycles = 0;
775
776 if (source == info->source) {
777 // TODO: support 4 cycles for ROM access
778 cycles += 2;
779 if (width == 4) {
780 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
781 source &= 0xFFFFFFFC;
782 dest &= 0xFFFFFFFC;
783 } else {
784 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
785 }
786 } else {
787 if (width == 4) {
788 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
789 } else {
790 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
791 }
792 }
793
794 if (width == 4) {
795 int32_t word;
796 word = cpu->memory.load32(cpu, source, 0);
797 cpu->memory.store32(cpu, dest, word, 0);
798 source += sourceOffset;
799 dest += destOffset;
800 --wordsRemaining;
801 } else {
802 uint16_t word;
803 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
804 word = GBASavedataReadEEPROM(&memory->savedata);
805 cpu->memory.store16(cpu, dest, word, 0);
806 source += sourceOffset;
807 dest += destOffset;
808 --wordsRemaining;
809 } else if (destRegion == REGION_CART2_EX) {
810 if (memory->savedata.type == SAVEDATA_NONE) {
811 GBASavedataInitEEPROM(&memory->savedata);
812 }
813 word = cpu->memory.load16(cpu, source, 0);
814 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
815 source += sourceOffset;
816 dest += destOffset;
817 --wordsRemaining;
818 } else {
819 word = cpu->memory.load16(cpu, source, 0);
820 cpu->memory.store16(cpu, dest, word, 0);
821 source += sourceOffset;
822 dest += destOffset;
823 --wordsRemaining;
824 }
825 }
826
827 if (!wordsRemaining) {
828 if (!info->repeat) {
829 info->enable = 0;
830 info->nextEvent = INT_MAX;
831
832 // Clear the enable bit in memory
833 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
834 } else {
835 info->nextCount = info->count;
836 if (info->dstControl == DMA_INCREMENT_RELOAD) {
837 info->nextDest = info->dest;
838 }
839 GBAMemoryScheduleDMA(gba, number, info);
840 }
841 if (info->doIrq) {
842 GBARaiseIRQ(gba, IRQ_DMA0 + number);
843 }
844 } else {
845 info->nextDest = dest;
846 info->nextCount = wordsRemaining;
847 }
848 info->nextSource = source;
849
850 int i;
851 for (i = 0; i < 4; ++i) {
852 if (memory->dma[i].nextEvent != INT_MAX) {
853 memory->dma[i].nextEvent += cycles;
854 }
855 }
856 cpu->cycles += cycles;
857}
858
859void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
860 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
861 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
862}
863
864void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
865 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
866 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
867}