1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing2-GS.gb".
  3
  4[labels]
  501:47f0 check_asserts_cb
  601:4842 check_asserts_cb@check_asserts
  701:4864 check_asserts_cb@fail0
  801:4870 check_asserts_cb@ok0
  901:487a check_asserts_cb@skip0
 1001:4885 check_asserts_cb@out0
 1101:489c check_asserts_cb@fail1
 1201:48a8 check_asserts_cb@ok1
 1301:48b2 check_asserts_cb@skip1
 1401:48bd check_asserts_cb@out1
 1501:48dd check_asserts_cb@fail2
 1601:48e9 check_asserts_cb@ok2
 1701:48f3 check_asserts_cb@skip2
 1801:48fe check_asserts_cb@out2
 1901:4915 check_asserts_cb@fail3
 2001:4921 check_asserts_cb@ok3
 2101:492b check_asserts_cb@skip3
 2201:4936 check_asserts_cb@out3
 2301:4956 check_asserts_cb@fail4
 2401:4962 check_asserts_cb@ok4
 2501:496c check_asserts_cb@skip4
 2601:4977 check_asserts_cb@out4
 2701:498e check_asserts_cb@fail5
 2801:499a check_asserts_cb@ok5
 2901:49a4 check_asserts_cb@skip5
 3001:49af check_asserts_cb@out5
 3101:49cf check_asserts_cb@fail6
 3201:49db check_asserts_cb@ok6
 3301:49e5 check_asserts_cb@skip6
 3401:49f0 check_asserts_cb@out6
 3501:4a07 check_asserts_cb@fail7
 3601:4a13 check_asserts_cb@ok7
 3701:4a1d check_asserts_cb@skip7
 3801:4a28 check_asserts_cb@out7
 3901:4b7b clear_vram
 4001:4b3a disable_lcd_safe
 4101:4b40 disable_lcd_safe@wait_ly_0
 4201:4b8f memcpy
 4301:4b98 memset
 4401:4b58 print_hex4
 4501:4b85 print_hex8
 4601:4ba8 print_inline_string
 4701:4b64 print_load_font
 4801:4b70 print_newline
 4901:4a2b print_reg_dump
 5001:4ba1 print_string
 5101:4ab0 quit
 5201:4ac5 quit@cb_return
 5301:4aca quit@wait_ly_1
 5401:4ad0 quit@wait_ly_2
 5501:4ad6 quit@wait_ly_3
 5601:4adc quit@wait_ly_4
 5701:4ae6 quit@success
 5801:4b0d quit@failure
 5901:4b22 quit@halt
 6001:4b23 quit@halt_execution_0
 6101:4b26 reset_screen
 6201:4b49 serial_send_byte
 6301:4000 font
 6400:ff80 v_regs_save
 6500:ff80 v_regs_save.reg_f
 6600:ff81 v_regs_save.reg_a
 6700:ff82 v_regs_save.reg_c
 6800:ff83 v_regs_save.reg_b
 6900:ff84 v_regs_save.reg_e
 7000:ff85 v_regs_save.reg_d
 7100:ff86 v_regs_save.reg_l
 7200:ff87 v_regs_save.reg_h
 7300:ff88 v_regs_flags
 7400:ff89 v_regs_assert
 7500:ff89 v_regs_assert.reg_f
 7600:ff8a v_regs_assert.reg_a
 7700:ff8b v_regs_assert.reg_c
 7800:ff8c v_regs_assert.reg_b
 7900:ff8d v_regs_assert.reg_e
 8000:ff8e v_regs_assert.reg_d
 8100:ff8f v_regs_assert.reg_l
 8200:ff90 v_regs_assert.reg_h
 8300:0150 main
 8400:0151 main@wait_ly_5
 8500:0167 test_round1
 8600:0183 _delay_long_time_0
 8700:0193 finish_round1
 8800:01a2 test_round2
 8900:01bd _delay_long_time_1
 9000:01ce finish_round2
 9100:01dd test_round3
 9200:01f8 finish_round3
 9300:0207 test_round4
 9400:0221 finish_round4
 9500:026d fail_halt
 9600:0274 fail_halt@quit_inline_1
 9700:0288 fail_round1
 9800:028f fail_round1@quit_inline_2
 9900:02a6 fail_round2
10000:02ad fail_round2@quit_inline_3
10100:02c4 fail_round3
10200:02cb fail_round3@quit_inline_4
10300:02e2 fail_round4
10400:02e9 fail_round4@quit_inline_5
105
106[definitions]
1070000023b _sizeof_check_asserts_cb
1080000000a _sizeof_clear_vram
1090000000f _sizeof_disable_lcd_safe
11000000009 _sizeof_memcpy
11100000009 _sizeof_memset
1120000000c _sizeof_print_hex4
1130000000a _sizeof_print_hex8
11400000006 _sizeof_print_inline_string
1150000000c _sizeof_print_load_font
1160000000b _sizeof_print_newline
11700000085 _sizeof_print_reg_dump
11800000007 _sizeof_print_string
11900000076 _sizeof_quit
12000000014 _sizeof_reset_screen
1210000000f _sizeof_serial_send_byte
122000007f0 _sizeof_font
12300000008 _sizeof_v_regs_save
12400000001 _sizeof_v_regs_save.reg_f
12500000001 _sizeof_v_regs_save.reg_a
12600000001 _sizeof_v_regs_save.reg_c
12700000001 _sizeof_v_regs_save.reg_b
12800000001 _sizeof_v_regs_save.reg_e
12900000001 _sizeof_v_regs_save.reg_d
13000000001 _sizeof_v_regs_save.reg_l
13100000001 _sizeof_v_regs_save.reg_h
13200000001 _sizeof_v_regs_flags
13300000008 _sizeof_v_regs_assert
13400000001 _sizeof_v_regs_assert.reg_f
13500000001 _sizeof_v_regs_assert.reg_a
13600000001 _sizeof_v_regs_assert.reg_c
13700000001 _sizeof_v_regs_assert.reg_b
13800000001 _sizeof_v_regs_assert.reg_e
13900000001 _sizeof_v_regs_assert.reg_d
14000000001 _sizeof_v_regs_assert.reg_l
14100000001 _sizeof_v_regs_assert.reg_h
14200000017 _sizeof_main
1430000001c _sizeof_test_round1
14400000010 _sizeof__delay_long_time_0
1450000000f _sizeof_finish_round1
1460000001b _sizeof_test_round2
14700000011 _sizeof__delay_long_time_1
1480000000f _sizeof_finish_round2
1490000001b _sizeof_test_round3
1500000000f _sizeof_finish_round3
1510000001a _sizeof_test_round4
1520000004c _sizeof_finish_round4
1530000001b _sizeof_fail_halt
1540000001e _sizeof_fail_round1
1550000001e _sizeof_fail_round2
1560000001e _sizeof_fail_round3