src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259
260#define ADDR_MODE_4_WRITEBACK_LDM \
261 if (!((1 << rn) & rs)) { \
262 cpu->gprs[rn] = address; \
263 }
264
265#define ADDR_MODE_4_WRITEBACK_LDMv5 \
266 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
267 cpu->gprs[rn] = address; \
268 }
269
270#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
271
272#define ARM_LOAD_POST_BODY \
273 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
274 if (rd == ARM_PC) { \
275 ARM_WRITE_PC; \
276 }
277
278#define ARM_LOAD_POST_BODY_v5 \
279 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
280 if (rd == ARM_PC) { \
281 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
282 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
283 if (cpu->executionMode == MODE_THUMB) { \
284 THUMB_WRITE_PC; \
285 } else { \
286 ARM_WRITE_PC; \
287 } \
288 }
289
290#define ARM_STORE_POST_BODY \
291 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
292
293#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
294 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
295 int currentCycles = ARM_PREFETCH_CYCLES; \
296 BODY; \
297 cpu->cycles += currentCycles; \
298 }
299
300#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
301 DEFINE_INSTRUCTION_ARM(NAME, \
302 int rd = (opcode >> 12) & 0xF; \
303 int rn = (opcode >> 16) & 0xF; \
304 UNUSED(rn); \
305 SHIFTER(cpu, opcode); \
306 BODY; \
307 S_BODY; \
308 if (rd == ARM_PC) { \
309 if (cpu->executionMode == MODE_ARM) { \
310 ARM_WRITE_PC; \
311 } else { \
312 THUMB_WRITE_PC; \
313 } \
314 })
315
316#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
327
328#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
334
335#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
336 DEFINE_INSTRUCTION_ARM(NAME, \
337 int rd = (opcode >> 16) & 0xF; \
338 int rs = (opcode >> 8) & 0xF; \
339 int rm = opcode & 0xF; \
340 if (rd == ARM_PC) { \
341 return; \
342 } \
343 ARM_WAIT_MUL(cpu->gprs[rs]); \
344 BODY; \
345 S_BODY; \
346 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
347
348#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
349 DEFINE_INSTRUCTION_ARM(NAME, \
350 int rd = (opcode >> 12) & 0xF; \
351 int rdHi = (opcode >> 16) & 0xF; \
352 int rs = (opcode >> 8) & 0xF; \
353 int rm = opcode & 0xF; \
354 if (rdHi == ARM_PC || rd == ARM_PC) { \
355 return; \
356 } \
357 currentCycles += cpu->memory.stall(cpu, WAIT); \
358 BODY; \
359 S_BODY; \
360 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
361
362#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
363 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
364 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
365
366#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
367 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
368 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
369
370#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
371 DEFINE_INSTRUCTION_ARM(NAME, \
372 int rd = (opcode >> 16) & 0xF; \
373 int rs = (opcode >> 8) & 0xF; \
374 int rn = (opcode >> 12) & 0xF; \
375 int rm = opcode & 0xF; \
376 UNUSED(rn); \
377 if (rd == ARM_PC) { \
378 return; \
379 } \
380 /* TODO: Timing */ \
381 int32_t x; \
382 int32_t y; \
383 BODY; \
384 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
385
386#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
387 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
388 x = ARM_SXT_16(cpu->gprs[rm]); \
389 y = ARM_SXT_16(cpu->gprs[rs]); \
390 BODY) \
391 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
392 x = ARM_SXT_16(cpu->gprs[rm]); \
393 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
394 BODY) \
395 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
396 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
397 y = ARM_SXT_16(cpu->gprs[rs]); \
398 BODY) \
399 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
400 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
401 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
402 BODY)
403
404#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
405 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
406 y = ARM_SXT_16(cpu->gprs[rs]); \
407 BODY) \
408 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
409 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
410 BODY) \
411
412#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
413 DEFINE_INSTRUCTION_ARM(NAME, \
414 uint32_t address; \
415 int rn = (opcode >> 16) & 0xF; \
416 int rd = (opcode >> 12) & 0xF; \
417 int rm = opcode & 0xF; \
418 UNUSED(rm); \
419 address = ADDRESS; \
420 WRITEBACK; \
421 BODY;)
422
423#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
424 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
425 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
428 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
429 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
430
431#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
433 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
434 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
435 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
436 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
437 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
438 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
439 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
440 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
442
443#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
445 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
446 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
447 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
448 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
456
457#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
459 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
460
461#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
462 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
463 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
464 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
465 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
468
469#define ARM_MS_PRE \
470 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
471 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
472
473#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
474
475#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
476 DEFINE_INSTRUCTION_ARM(NAME, \
477 int rn = (opcode >> 16) & 0xF; \
478 int rs = opcode & 0x0000FFFF; \
479 uint32_t address = cpu->gprs[rn]; \
480 S_PRE; \
481 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
482 S_POST; \
483 POST_BODY; \
484 WRITEBACK;)
485
486
487#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
488 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
489 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
490 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
491 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
492 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
493 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
494 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
495 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
496
497#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
498 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
499 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
500 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
501 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
502 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
503 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
504 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
505 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
506 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
507
508// Begin ALU definitions
509
510DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
511 int32_t n = cpu->gprs[rn];
512 cpu->gprs[rd] = n + cpu->shifterOperand;)
513
514DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
515 int32_t n = cpu->gprs[rn];
516 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
517
518DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
519 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
520
521DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
522 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
523
524DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
525 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
526
527DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
528 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
529
530DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
531 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
532
533DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
534 cpu->gprs[rd] = cpu->shifterOperand;)
535
536DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
537 cpu->gprs[rd] = ~cpu->shifterOperand;)
538
539DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
540 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
541
542DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
543 int32_t n = cpu->gprs[rn];
544 cpu->gprs[rd] = cpu->shifterOperand - n;)
545
546DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
547 int32_t n = cpu->gprs[rn];
548 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
549
550DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
551 int32_t n = cpu->gprs[rn];
552 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
553
554DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
555 int32_t n = cpu->gprs[rn];
556 cpu->gprs[rd] = n - cpu->shifterOperand;)
557
558DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
559 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
560
561DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
562 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
563
564// End ALU definitions
565
566// Begin multiply definitions
567
568DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
569DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
570
571DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
572 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
573 int32_t dm = cpu->gprs[rd];
574 int32_t dn = d;
575 cpu->gprs[rd] = dm + dn;
576 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
577 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
578
579DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
580 int32_t dn = cpu->gprs[rn]; \
581 int32_t d = x * y; \
582 cpu->gprs[rd] = d + dn; \
583 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
584
585DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
586
587DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
588 int32_t dn = cpu->gprs[rn]; \
589 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
590 cpu->gprs[rd] = d + dn; \
591 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
592
593DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
594
595DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
596 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
597 cpu->gprs[rd] = d;
598 cpu->gprs[rdHi] = d >> 32;,
599 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
600
601DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
602 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
603 int32_t dm = cpu->gprs[rd];
604 int32_t dn = d;
605 cpu->gprs[rd] = dm + dn;
606 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
607 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
608
609DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
610 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
611 cpu->gprs[rd] = d;
612 cpu->gprs[rdHi] = d >> 32;,
613 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
614
615// End multiply definitions
616
617// Begin load/store definitions
618
619DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
620DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
621DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
622DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
623DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
624DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
625DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
626DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
627DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
628
629DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
630 enum PrivilegeMode priv = cpu->privilegeMode;
631 ARMSetPrivilegeMode(cpu, MODE_USER);
632 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
633 ARMSetPrivilegeMode(cpu, priv);
634 cpu->gprs[rd] = r;
635 ARM_LOAD_POST_BODY;)
636
637DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
638 enum PrivilegeMode priv = cpu->privilegeMode;
639 ARMSetPrivilegeMode(cpu, MODE_USER);
640 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
641 ARMSetPrivilegeMode(cpu, priv);
642 cpu->gprs[rd] = r;
643 ARM_LOAD_POST_BODY;)
644
645DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
646 enum PrivilegeMode priv = cpu->privilegeMode;
647 int32_t r = cpu->gprs[rd];
648 ARMSetPrivilegeMode(cpu, MODE_USER);
649 cpu->memory.store8(cpu, address, r, ¤tCycles);
650 ARMSetPrivilegeMode(cpu, priv);
651 ARM_STORE_POST_BODY;)
652
653DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
654 enum PrivilegeMode priv = cpu->privilegeMode;
655 int32_t r = cpu->gprs[rd];
656 ARMSetPrivilegeMode(cpu, MODE_USER);
657 cpu->memory.store32(cpu, address, r, ¤tCycles);
658 ARMSetPrivilegeMode(cpu, priv);
659 ARM_STORE_POST_BODY;)
660
661DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
662 load,
663 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
664 if (rs & 0x8000) {
665 ARM_WRITE_PC;
666 })
667
668DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
669 load,
670 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
671 if (rs & 0x8000) {
672 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
673 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
674 if (cpu->executionMode == MODE_THUMB) {
675 THUMB_WRITE_PC;
676 } else {
677 ARM_WRITE_PC;
678
679 }
680 })
681
682DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
683 store,
684 ARM_STORE_POST_BODY;)
685
686DEFINE_INSTRUCTION_ARM(SWP,
687 int rm = opcode & 0xF;
688 int rd = (opcode >> 12) & 0xF;
689 int rn = (opcode >> 16) & 0xF;
690 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
691 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
692 cpu->gprs[rd] = d;)
693
694DEFINE_INSTRUCTION_ARM(SWPB,
695 int rm = opcode & 0xF;
696 int rd = (opcode >> 12) & 0xF;
697 int rn = (opcode >> 16) & 0xF;
698 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
699 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
700 cpu->gprs[rd] = d;)
701
702// End load/store definitions
703
704// Begin branch definitions
705
706DEFINE_INSTRUCTION_ARM(B,
707 int32_t offset = opcode << 8;
708 offset >>= 6;
709 cpu->gprs[ARM_PC] += offset;
710 ARM_WRITE_PC;)
711
712DEFINE_INSTRUCTION_ARM(BL,
713 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
714 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
715 cpu->gprs[ARM_PC] += immediate >> 6;
716 ARM_WRITE_PC;)
717
718DEFINE_INSTRUCTION_ARM(BX,
719 int rm = opcode & 0x0000000F;
720 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
721 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
722 if (cpu->executionMode == MODE_THUMB) {
723 THUMB_WRITE_PC;
724 } else {
725 ARM_WRITE_PC;
726
727 })
728
729DEFINE_INSTRUCTION_ARM(BLX,
730 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
731 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
732 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
733 _ARMSetMode(cpu, MODE_THUMB);
734 THUMB_WRITE_PC;)
735
736DEFINE_INSTRUCTION_ARM(BLX2,
737 int rm = opcode & 0x0000000F;
738 int address = cpu->gprs[rm];
739 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
740 _ARMSetMode(cpu, address & 0x00000001);
741 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
742 if (cpu->executionMode == MODE_THUMB) {
743 THUMB_WRITE_PC;
744 } else {
745 ARM_WRITE_PC;
746 })
747
748// End branch definitions
749
750// Begin coprocessor definitions
751
752#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
753 DEFINE_INSTRUCTION_ARM(NAME, \
754 int op1 = (opcode >> 21) & 7; \
755 int op2 = (opcode >> 5) & 7; \
756 int rd = (opcode >> 12) & 0xF; \
757 int cp = (opcode >> 8) & 0xF; \
758 int crn = (opcode >> 16) & 0xF; \
759 int crm = opcode & 0xF; \
760 UNUSED(op1); \
761 UNUSED(op2); \
762 UNUSED(rd); \
763 UNUSED(crn); \
764 UNUSED(crm); \
765 BODY;)
766
767DEFINE_COPROCESSOR_INSTRUCTION(MRC,
768 if (cp == 15 && cpu->irqh.readCP15) {
769 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
770 } else {
771 ARM_STUB;
772 })
773
774DEFINE_COPROCESSOR_INSTRUCTION(MCR,
775 if (cp == 15 && cpu->irqh.writeCP15) {
776 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
777 } else {
778 ARM_STUB;
779 })
780
781DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
782DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
783DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
784
785// Begin miscellaneous definitions
786
787DEFINE_INSTRUCTION_ARM(CLZ,
788 int rm = opcode & 0xF;
789 int rd = (opcode >> 12) & 0xF;
790 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
791
792DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
793DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
794
795DEFINE_INSTRUCTION_ARM(MSR,
796 int c = opcode & 0x00010000;
797 int f = opcode & 0x00080000;
798 int32_t operand = cpu->gprs[opcode & 0x0000000F];
799 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
800 if (mask & PSR_USER_MASK) {
801 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
802 }
803 if (mask & PSR_STATE_MASK) {
804 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
805 }
806 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
807 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
808 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
809 }
810 _ARMReadCPSR(cpu);
811 if (cpu->executionMode == MODE_THUMB) {
812 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
813 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
814 } else {
815 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
816 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
817 })
818
819DEFINE_INSTRUCTION_ARM(MSRR,
820 int c = opcode & 0x00010000;
821 int f = opcode & 0x00080000;
822 int32_t operand = cpu->gprs[opcode & 0x0000000F];
823 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
824 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
825 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
826
827DEFINE_INSTRUCTION_ARM(MRS, \
828 int rd = (opcode >> 12) & 0xF; \
829 cpu->gprs[rd] = cpu->cpsr.packed;)
830
831DEFINE_INSTRUCTION_ARM(MRSR, \
832 int rd = (opcode >> 12) & 0xF; \
833 cpu->gprs[rd] = cpu->spsr.packed;)
834
835DEFINE_INSTRUCTION_ARM(MSRI,
836 int c = opcode & 0x00010000;
837 int f = opcode & 0x00080000;
838 int rotate = (opcode & 0x00000F00) >> 7;
839 int32_t operand = ROR(opcode & 0x000000FF, rotate);
840 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
841 if (mask & PSR_USER_MASK) {
842 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
843 }
844 if (mask & PSR_STATE_MASK) {
845 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
846 }
847 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
848 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
849 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
850 }
851 _ARMReadCPSR(cpu);
852 if (cpu->executionMode == MODE_THUMB) {
853 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
854 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
855 } else {
856 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
857 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
858 })
859
860DEFINE_INSTRUCTION_ARM(MSRRI,
861 int c = opcode & 0x00010000;
862 int f = opcode & 0x00080000;
863 int rotate = (opcode & 0x00000F00) >> 7;
864 int32_t operand = ROR(opcode & 0x000000FF, rotate);
865 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
866 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
867 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
868
869DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
870
871const ARMInstruction _armv4Table[0x1000] = {
872 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
873};
874
875const ARMInstruction _armv5Table[0x1000] = {
876 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
877};
878
879const ARMInstruction _armv4FTable[0x1000] = {
880 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
881};
882
883const ARMInstruction _armv5FTable[0x1000] = {
884 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
885};