src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_IE] = 0xE0,
105};
106
107static void _writeSGBBits(struct GB* gb, int bits) {
108 if (!bits) {
109 gb->sgbBit = 0;
110 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
111 }
112 if (bits == gb->currentSgbBits) {
113 return;
114 }
115 gb->currentSgbBits = bits;
116 if (gb->sgbBit == 128 && bits == 2) {
117 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
118 ++gb->sgbBit;
119 }
120 if (gb->sgbBit >= 128) {
121 return;
122 }
123 switch (bits) {
124 case 1:
125 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
126 // Fall through
127 case 2:
128 ++gb->sgbBit;
129 default:
130 break;
131 }
132}
133
134void GBIOInit(struct GB* gb) {
135 memset(gb->memory.io, 0, sizeof(gb->memory.io));
136}
137
138void GBIOReset(struct GB* gb) {
139 memset(gb->memory.io, 0, sizeof(gb->memory.io));
140
141 GBIOWrite(gb, REG_TIMA, 0);
142 GBIOWrite(gb, REG_TMA, 0);
143 GBIOWrite(gb, REG_TAC, 0);
144 GBIOWrite(gb, REG_IF, 1);
145 GBIOWrite(gb, REG_NR52, 0xF1);
146 GBIOWrite(gb, REG_NR14, 0x3F);
147 GBIOWrite(gb, REG_NR10, 0x80);
148 GBIOWrite(gb, REG_NR11, 0xBF);
149 GBIOWrite(gb, REG_NR12, 0xF3);
150 GBIOWrite(gb, REG_NR13, 0xF3);
151 GBIOWrite(gb, REG_NR24, 0x3F);
152 GBIOWrite(gb, REG_NR21, 0x3F);
153 GBIOWrite(gb, REG_NR22, 0x00);
154 GBIOWrite(gb, REG_NR34, 0x3F);
155 GBIOWrite(gb, REG_NR30, 0x7F);
156 GBIOWrite(gb, REG_NR31, 0xFF);
157 GBIOWrite(gb, REG_NR32, 0x9F);
158 GBIOWrite(gb, REG_NR44, 0x3F);
159 GBIOWrite(gb, REG_NR41, 0xFF);
160 GBIOWrite(gb, REG_NR42, 0x00);
161 GBIOWrite(gb, REG_NR43, 0x00);
162 GBIOWrite(gb, REG_NR50, 0x77);
163 GBIOWrite(gb, REG_NR51, 0xF3);
164 GBIOWrite(gb, REG_LCDC, 0x91);
165 GBIOWrite(gb, REG_SCY, 0x00);
166 GBIOWrite(gb, REG_SCX, 0x00);
167 GBIOWrite(gb, REG_LYC, 0x00);
168 GBIOWrite(gb, REG_BGP, 0xFC);
169 if (gb->model < GB_MODEL_CGB) {
170 GBIOWrite(gb, REG_OBP0, 0xFF);
171 GBIOWrite(gb, REG_OBP1, 0xFF);
172 }
173 GBIOWrite(gb, REG_WY, 0x00);
174 GBIOWrite(gb, REG_WX, 0x00);
175 if (gb->model >= GB_MODEL_CGB) {
176 GBIOWrite(gb, REG_UNK4C, 0);
177 GBIOWrite(gb, REG_JOYP, 0xFF);
178 GBIOWrite(gb, REG_VBK, 0);
179 GBIOWrite(gb, REG_BCPS, 0);
180 GBIOWrite(gb, REG_OCPS, 0);
181 GBIOWrite(gb, REG_SVBK, 1);
182 GBIOWrite(gb, REG_HDMA1, 0xFF);
183 GBIOWrite(gb, REG_HDMA2, 0xFF);
184 GBIOWrite(gb, REG_HDMA3, 0xFF);
185 GBIOWrite(gb, REG_HDMA4, 0xFF);
186 gb->memory.io[REG_HDMA5] = 0xFF;
187 } else if (gb->model == GB_MODEL_SGB) {
188 GBIOWrite(gb, REG_JOYP, 0xFF);
189 }
190 GBIOWrite(gb, REG_IE, 0x00);
191}
192
193void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
194 switch (address) {
195 case REG_SB:
196 GBSIOWriteSB(&gb->sio, value);
197 break;
198 case REG_SC:
199 GBSIOWriteSC(&gb->sio, value);
200 break;
201 case REG_DIV:
202 GBTimerDivReset(&gb->timer);
203 return;
204 case REG_NR10:
205 if (gb->audio.enable) {
206 GBAudioWriteNR10(&gb->audio, value);
207 } else {
208 value = 0;
209 }
210 break;
211 case REG_NR11:
212 if (gb->audio.enable) {
213 GBAudioWriteNR11(&gb->audio, value);
214 } else {
215 if (gb->audio.style == GB_AUDIO_DMG) {
216 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
217 }
218 value = 0;
219 }
220 break;
221 case REG_NR12:
222 if (gb->audio.enable) {
223 GBAudioWriteNR12(&gb->audio, value);
224 } else {
225 value = 0;
226 }
227 break;
228 case REG_NR13:
229 if (gb->audio.enable) {
230 GBAudioWriteNR13(&gb->audio, value);
231 } else {
232 value = 0;
233 }
234 break;
235 case REG_NR14:
236 if (gb->audio.enable) {
237 GBAudioWriteNR14(&gb->audio, value);
238 } else {
239 value = 0;
240 }
241 break;
242 case REG_NR21:
243 if (gb->audio.enable) {
244 GBAudioWriteNR21(&gb->audio, value);
245 } else {
246 if (gb->audio.style == GB_AUDIO_DMG) {
247 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
248 }
249 value = 0;
250 }
251 break;
252 case REG_NR22:
253 if (gb->audio.enable) {
254 GBAudioWriteNR22(&gb->audio, value);
255 } else {
256 value = 0;
257 }
258 break;
259 case REG_NR23:
260 if (gb->audio.enable) {
261 GBAudioWriteNR23(&gb->audio, value);
262 } else {
263 value = 0;
264 }
265 break;
266 case REG_NR24:
267 if (gb->audio.enable) {
268 GBAudioWriteNR24(&gb->audio, value);
269 } else {
270 value = 0;
271 }
272 break;
273 case REG_NR30:
274 if (gb->audio.enable) {
275 GBAudioWriteNR30(&gb->audio, value);
276 } else {
277 value = 0;
278 }
279 break;
280 case REG_NR31:
281 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
282 GBAudioWriteNR31(&gb->audio, value);
283 } else {
284 value = 0;
285 }
286 break;
287 case REG_NR32:
288 if (gb->audio.enable) {
289 GBAudioWriteNR32(&gb->audio, value);
290 } else {
291 value = 0;
292 }
293 break;
294 case REG_NR33:
295 if (gb->audio.enable) {
296 GBAudioWriteNR33(&gb->audio, value);
297 } else {
298 value = 0;
299 }
300 break;
301 case REG_NR34:
302 if (gb->audio.enable) {
303 GBAudioWriteNR34(&gb->audio, value);
304 } else {
305 value = 0;
306 }
307 break;
308 case REG_NR41:
309 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
310 GBAudioWriteNR41(&gb->audio, value);
311 } else {
312 value = 0;
313 }
314 break;
315 case REG_NR42:
316 if (gb->audio.enable) {
317 GBAudioWriteNR42(&gb->audio, value);
318 } else {
319 value = 0;
320 }
321 break;
322 case REG_NR43:
323 if (gb->audio.enable) {
324 GBAudioWriteNR43(&gb->audio, value);
325 } else {
326 value = 0;
327 }
328 break;
329 case REG_NR44:
330 if (gb->audio.enable) {
331 GBAudioWriteNR44(&gb->audio, value);
332 } else {
333 value = 0;
334 }
335 break;
336 case REG_NR50:
337 if (gb->audio.enable) {
338 GBAudioWriteNR50(&gb->audio, value);
339 } else {
340 value = 0;
341 }
342 break;
343 case REG_NR51:
344 if (gb->audio.enable) {
345 GBAudioWriteNR51(&gb->audio, value);
346 } else {
347 value = 0;
348 }
349 break;
350 case REG_NR52:
351 GBAudioWriteNR52(&gb->audio, value);
352 value &= 0x80;
353 value |= gb->memory.io[REG_NR52] & 0x0F;
354 break;
355 case REG_WAVE_0:
356 case REG_WAVE_1:
357 case REG_WAVE_2:
358 case REG_WAVE_3:
359 case REG_WAVE_4:
360 case REG_WAVE_5:
361 case REG_WAVE_6:
362 case REG_WAVE_7:
363 case REG_WAVE_8:
364 case REG_WAVE_9:
365 case REG_WAVE_A:
366 case REG_WAVE_B:
367 case REG_WAVE_C:
368 case REG_WAVE_D:
369 case REG_WAVE_E:
370 case REG_WAVE_F:
371 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
372 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
373 } else if(gb->audio.ch3.readable) {
374 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
375 }
376 break;
377 case REG_JOYP:
378 if (gb->model == GB_MODEL_SGB) {
379 _writeSGBBits(gb, (value >> 4) & 3);
380 }
381 break;
382 case REG_TIMA:
383 case REG_TMA:
384 // Handled transparently by the registers
385 break;
386 case REG_TAC:
387 value = GBTimerUpdateTAC(&gb->timer, value);
388 break;
389 case REG_IF:
390 gb->memory.io[REG_IF] = value | 0xE0;
391 GBUpdateIRQs(gb);
392 return;
393 case REG_LCDC:
394 // TODO: handle GBC differences
395 GBVideoProcessDots(&gb->video, 0);
396 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
397 GBVideoWriteLCDC(&gb->video, value);
398 break;
399 case REG_LYC:
400 GBVideoWriteLYC(&gb->video, value);
401 break;
402 case REG_DMA:
403 GBMemoryDMA(gb, value << 8);
404 break;
405 case REG_SCY:
406 case REG_SCX:
407 case REG_WY:
408 case REG_WX:
409 GBVideoProcessDots(&gb->video, 0);
410 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
411 break;
412 case REG_BGP:
413 case REG_OBP0:
414 case REG_OBP1:
415 GBVideoProcessDots(&gb->video, 0);
416 GBVideoWritePalette(&gb->video, address, value);
417 break;
418 case REG_STAT:
419 GBVideoWriteSTAT(&gb->video, value);
420 value = gb->video.stat;
421 break;
422 case 0x50:
423 if (gb->memory.romBase < gb->memory.rom || gb->memory.romBase > &gb->memory.rom[gb->memory.romSize - 1]) {
424 free(gb->memory.romBase);
425 gb->memory.romBase = gb->memory.rom;
426 }
427 if (gb->model >= GB_MODEL_CGB && gb->memory.io[REG_UNK4C] < 0x80) {
428 gb->model = GB_MODEL_DMG;
429 GBVideoDisableCGB(&gb->video);
430 }
431 break;
432 case REG_IE:
433 gb->memory.ie = value;
434 GBUpdateIRQs(gb);
435 return;
436 default:
437 if (gb->model >= GB_MODEL_CGB) {
438 switch (address) {
439 case REG_UNK4C:
440 break;
441 case REG_KEY1:
442 value &= 0x1;
443 value |= gb->memory.io[address] & 0x80;
444 break;
445 case REG_VBK:
446 GBVideoSwitchBank(&gb->video, value);
447 break;
448 case REG_HDMA1:
449 case REG_HDMA2:
450 case REG_HDMA3:
451 case REG_HDMA4:
452 // Handled transparently by the registers
453 break;
454 case REG_HDMA5:
455 value = GBMemoryWriteHDMA5(gb, value);
456 break;
457 case REG_BCPS:
458 gb->video.bcpIndex = value & 0x3F;
459 gb->video.bcpIncrement = value & 0x80;
460 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
461 break;
462 case REG_BCPD:
463 GBVideoProcessDots(&gb->video, 0);
464 GBVideoWritePalette(&gb->video, address, value);
465 return;
466 case REG_OCPS:
467 gb->video.ocpIndex = value & 0x3F;
468 gb->video.ocpIncrement = value & 0x80;
469 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
470 break;
471 case REG_OCPD:
472 GBVideoProcessDots(&gb->video, 0);
473 GBVideoWritePalette(&gb->video, address, value);
474 return;
475 case REG_SVBK:
476 GBMemorySwitchWramBank(&gb->memory, value);
477 value = gb->memory.wramCurrentBank;
478 break;
479 default:
480 goto failed;
481 }
482 goto success;
483 }
484 failed:
485 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
486 if (address >= GB_SIZE_IO) {
487 return;
488 }
489 break;
490 }
491 success:
492 gb->memory.io[address] = value;
493}
494
495static uint8_t _readKeys(struct GB* gb) {
496 uint8_t keys = *gb->keySource;
497 switch (gb->memory.io[REG_JOYP] & 0x30) {
498 case 0x30:
499 // TODO: Increment
500 keys = (gb->video.sgbCommandHeader >> 3) == SGB_MLT_REG ? 0xF : 0;
501 break;
502 case 0x20:
503 keys >>= 4;
504 break;
505 case 0x10:
506 break;
507 case 0x00:
508 keys |= keys >> 4;
509 break;
510 }
511 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
512}
513
514uint8_t GBIORead(struct GB* gb, unsigned address) {
515 switch (address) {
516 case REG_JOYP:
517 return _readKeys(gb);
518 case REG_IE:
519 return gb->memory.ie;
520 case REG_WAVE_0:
521 case REG_WAVE_1:
522 case REG_WAVE_2:
523 case REG_WAVE_3:
524 case REG_WAVE_4:
525 case REG_WAVE_5:
526 case REG_WAVE_6:
527 case REG_WAVE_7:
528 case REG_WAVE_8:
529 case REG_WAVE_9:
530 case REG_WAVE_A:
531 case REG_WAVE_B:
532 case REG_WAVE_C:
533 case REG_WAVE_D:
534 case REG_WAVE_E:
535 case REG_WAVE_F:
536 if (gb->audio.playingCh3) {
537 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
538 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
539 } else {
540 return 0xFF;
541 }
542 } else {
543 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
544 }
545 break;
546 case REG_SB:
547 case REG_SC:
548 case REG_IF:
549 case REG_NR10:
550 case REG_NR11:
551 case REG_NR12:
552 case REG_NR14:
553 case REG_NR21:
554 case REG_NR22:
555 case REG_NR24:
556 case REG_NR30:
557 case REG_NR32:
558 case REG_NR34:
559 case REG_NR41:
560 case REG_NR42:
561 case REG_NR43:
562 case REG_NR44:
563 case REG_NR50:
564 case REG_NR51:
565 case REG_NR52:
566 case REG_DIV:
567 case REG_TIMA:
568 case REG_TMA:
569 case REG_TAC:
570 case REG_STAT:
571 case REG_LCDC:
572 case REG_SCY:
573 case REG_SCX:
574 case REG_LY:
575 case REG_LYC:
576 case REG_BGP:
577 case REG_OBP0:
578 case REG_OBP1:
579 case REG_WY:
580 case REG_WX:
581 // Handled transparently by the registers
582 break;
583 default:
584 if (gb->model >= GB_MODEL_CGB) {
585 switch (address) {
586 case REG_KEY1:
587 case REG_VBK:
588 case REG_HDMA1:
589 case REG_HDMA2:
590 case REG_HDMA3:
591 case REG_HDMA4:
592 case REG_HDMA5:
593 case REG_BCPS:
594 case REG_BCPD:
595 case REG_OCPS:
596 case REG_OCPD:
597 case REG_SVBK:
598 // Handled transparently by the registers
599 goto success;
600 case REG_DMA:
601 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
602 return 0;
603 default:
604 break;
605 }
606 }
607 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
608 return 0xFF;
609 }
610 success:
611 return gb->memory.io[address] | _registerMask[address];
612}
613
614void GBTestKeypadIRQ(struct GB* gb) {
615 if (_readKeys(gb)) {
616 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
617 GBUpdateIRQs(gb);
618 }
619}
620
621struct GBSerializedState;
622void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
623 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
624 state->ie = gb->memory.ie;
625}
626
627void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
628 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
629 gb->memory.ie = state->ie;
630
631 if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
632 GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
633 GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
634 GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
635 GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
636 gb->audio.ch1.control.frequency &= 0xFF;
637 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
638 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
639 GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
640 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
641 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
642 gb->audio.ch2.control.frequency &= 0xFF;
643 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
644 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
645 GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
646 GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
647 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
648 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
649 gb->audio.ch3.rate &= 0xFF;
650 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
651 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
652 GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
653 GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
654 GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
655 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
656 GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
657 GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
658 }
659
660 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
661 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
662 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
663 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
664 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
665 if (gb->model == GB_MODEL_SGB) {
666 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
667 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
668 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
669 }
670 gb->video.stat = state->io[REG_STAT];
671}