1#ifndef ARM_H
  2#define ARM_H
  3
  4#include "util/common.h"
  5
  6enum {
  7	ARM_SP = 13,
  8	ARM_LR = 14,
  9	ARM_PC = 15
 10};
 11
 12enum ExecutionMode {
 13	MODE_ARM = 0,
 14	MODE_THUMB = 1
 15};
 16
 17enum PrivilegeMode {
 18	MODE_USER = 0x10,
 19	MODE_FIQ = 0x11,
 20	MODE_IRQ = 0x12,
 21	MODE_SUPERVISOR = 0x13,
 22	MODE_ABORT = 0x17,
 23	MODE_UNDEFINED = 0x1B,
 24	MODE_SYSTEM = 0x1F
 25};
 26
 27enum WordSize {
 28	WORD_SIZE_ARM = 4,
 29	WORD_SIZE_THUMB = 2
 30};
 31
 32enum ExecutionVector {
 33	BASE_RESET = 0x00000000,
 34	BASE_UNDEF = 0x00000004,
 35	BASE_SWI = 0x00000008,
 36	BASE_PABT = 0x0000000C,
 37	BASE_DABT = 0x00000010,
 38	BASE_IRQ = 0x00000018,
 39	BASE_FIQ = 0x0000001C
 40};
 41
 42enum RegisterBank {
 43	BANK_NONE = 0,
 44	BANK_FIQ = 1,
 45	BANK_IRQ = 2,
 46	BANK_SUPERVISOR = 3,
 47	BANK_ABORT = 4,
 48	BANK_UNDEFINED = 5
 49};
 50
 51enum LSMDirection {
 52	LSM_B = 1,
 53	LSM_D = 2,
 54	LSM_IA = 0,
 55	LSM_IB = 1,
 56	LSM_DA = 2,
 57	LSM_DB = 3
 58};
 59
 60struct ARMCore;
 61
 62union PSR {
 63	struct {
 64#if defined(__POWERPC__) || defined(__PPC__)
 65		unsigned n : 1;
 66		unsigned z : 1;
 67		unsigned c : 1;
 68		unsigned v : 1;
 69		unsigned : 20;
 70		unsigned i : 1;
 71		unsigned f : 1;
 72		enum ExecutionMode t : 1;
 73		enum PrivilegeMode priv : 5;
 74#else
 75		enum PrivilegeMode priv : 5;
 76		enum ExecutionMode t : 1;
 77		unsigned f : 1;
 78		unsigned i : 1;
 79		unsigned : 20;
 80		unsigned v : 1;
 81		unsigned c : 1;
 82		unsigned z : 1;
 83		unsigned n : 1;
 84#endif
 85	};
 86
 87	int32_t packed;
 88};
 89
 90struct ARMMemory {
 91	int32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 92	int16_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 93	uint16_t (*loadU16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 94	int8_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 95	uint8_t (*loadU8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 96
 97	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
 98	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
 99	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
100
101	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction, int* cycleCounter);
102	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction, int* cycleCounter);
103
104	uint32_t* activeRegion;
105	uint32_t activeMask;
106	uint32_t activeSeqCycles32;
107	uint32_t activeSeqCycles16;
108	uint32_t activeNonseqCycles32;
109	uint32_t activeNonseqCycles16;
110	uint32_t activeUncachedCycles32;
111	uint32_t activeUncachedCycles16;
112	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
113};
114
115struct ARMInterruptHandler {
116	void (*reset)(struct ARMCore* cpu);
117	void (*processEvents)(struct ARMCore* cpu);
118	void (*swi16)(struct ARMCore* cpu, int immediate);
119	void (*swi32)(struct ARMCore* cpu, int immediate);
120	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
121	void (*readCPSR)(struct ARMCore* cpu);
122
123	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
124};
125
126struct ARMComponent {
127	uint32_t id;
128	void (*init)(struct ARMCore* cpu, struct ARMComponent* component);
129	void (*deinit)(struct ARMComponent* component);
130};
131
132struct ARMCore {
133	int32_t gprs[16];
134	union PSR cpsr;
135	union PSR spsr;
136
137	int32_t cycles;
138	int32_t nextEvent;
139	int halted;
140
141	int32_t bankedRegisters[6][7];
142	int32_t bankedSPSRs[6];
143
144	int32_t shifterOperand;
145	int32_t shifterCarryOut;
146
147	uint32_t prefetch;
148	enum ExecutionMode executionMode;
149	enum PrivilegeMode privilegeMode;
150
151	struct ARMMemory memory;
152	struct ARMInterruptHandler irqh;
153
154	struct ARMComponent* master;
155
156	int numComponents;
157	struct ARMComponent** components;
158};
159
160void ARMInit(struct ARMCore* cpu);
161void ARMDeinit(struct ARMCore* cpu);
162void ARMSetComponents(struct ARMCore* cpu, struct ARMComponent* master, int extra, struct ARMComponent** extras);
163
164void ARMReset(struct ARMCore* cpu);
165void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
166void ARMRaiseIRQ(struct ARMCore*);
167void ARMRaiseSWI(struct ARMCore*);
168
169void ARMRun(struct ARMCore* cpu);
170void ARMRunLoop(struct ARMCore* cpu);
171
172#endif