src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "core/interface.h"
9#include "gb/gb.h"
10#include "gb/io.h"
11
12#include "util/memory.h"
13
14#include <time.h>
15
16mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC");
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
18
19static void _GBMBCNone(struct GBMemory* memory, uint16_t address, uint8_t value) {
20 UNUSED(memory);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GBMemory*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GBMemory*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GBMemory*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GBMemory*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GBMemory*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static void _GBMBC7Write(struct GBMemory*, uint16_t address, uint8_t value);
35
36static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
37 if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
38 cpu->memory.setActiveRegion(cpu, address);
39 return cpu->memory.cpuLoad8(cpu, address);
40 }
41 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
42}
43
44static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
45 struct GB* gb = (struct GB*) cpu->master;
46 struct GBMemory* memory = &gb->memory;
47 switch (address >> 12) {
48 case GB_REGION_CART_BANK0:
49 case GB_REGION_CART_BANK0 + 1:
50 case GB_REGION_CART_BANK0 + 2:
51 case GB_REGION_CART_BANK0 + 3:
52 cpu->memory.cpuLoad8 = GBFastLoad8;
53 cpu->memory.activeRegion = memory->rom;
54 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
55 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
56 break;
57 case GB_REGION_CART_BANK1:
58 case GB_REGION_CART_BANK1 + 1:
59 case GB_REGION_CART_BANK1 + 2:
60 case GB_REGION_CART_BANK1 + 3:
61 cpu->memory.cpuLoad8 = GBFastLoad8;
62 cpu->memory.activeRegion = memory->romBank;
63 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
64 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
65 break;
66 default:
67 cpu->memory.cpuLoad8 = GBLoad8;
68 break;
69 }
70}
71
72static void _GBMemoryDMAService(struct GB* gb);
73static void _GBMemoryHDMAService(struct GB* gb);
74
75void GBMemoryInit(struct GB* gb) {
76 struct LR35902Core* cpu = gb->cpu;
77 cpu->memory.cpuLoad8 = GBLoad8;
78 cpu->memory.load8 = GBLoad8;
79 cpu->memory.store8 = GBStore8;
80 cpu->memory.setActiveRegion = GBSetActiveRegion;
81
82 gb->memory.wram = 0;
83 gb->memory.wramBank = 0;
84 gb->memory.rom = 0;
85 gb->memory.romBank = 0;
86 gb->memory.romSize = 0;
87 gb->memory.sram = 0;
88 gb->memory.mbcType = GB_MBC_NONE;
89 gb->memory.mbc = 0;
90
91 gb->memory.rtc = NULL;
92
93 GBIOInit(gb);
94}
95
96void GBMemoryDeinit(struct GB* gb) {
97 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
98 if (gb->memory.rom) {
99 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
100 }
101}
102
103void GBMemoryReset(struct GB* gb) {
104 if (gb->memory.wram) {
105 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
106 }
107 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
108 GBMemorySwitchWramBank(&gb->memory, 1);
109 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
110 gb->memory.currentBank = 1;
111 if (!gb->memory.sram) {
112 gb->memory.sram = anonymousMemoryMap(0x20000);
113 }
114 gb->memory.sramCurrentBank = 0;
115 gb->memory.sramBank = gb->memory.sram;
116
117 gb->memory.ime = false;
118 gb->memory.ie = 0;
119
120 gb->memory.dmaNext = INT_MAX;
121 gb->memory.dmaRemaining = 0;
122 gb->memory.dmaSource = 0;
123 gb->memory.dmaDest = 0;
124 gb->memory.hdmaNext = INT_MAX;
125 gb->memory.hdmaRemaining = 0;
126 gb->memory.hdmaSource = 0;
127 gb->memory.hdmaDest = 0;
128 gb->memory.isHdma = false;
129
130 gb->memory.sramAccess = false;
131 gb->memory.rtcAccess = false;
132 gb->memory.activeRtcReg = 0;
133 gb->memory.rtcLatched = 0;
134 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
135
136 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
137
138 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
139 switch (cart->type) {
140 case 0:
141 case 8:
142 case 9:
143 gb->memory.mbc = _GBMBCNone;
144 gb->memory.mbcType = GB_MBC_NONE;
145 break;
146 case 1:
147 case 2:
148 case 3:
149 gb->memory.mbc = _GBMBC1;
150 gb->memory.mbcType = GB_MBC1;
151 break;
152 case 5:
153 case 6:
154 gb->memory.mbc = _GBMBC2;
155 gb->memory.mbcType = GB_MBC2;
156 break;
157 case 0x0F:
158 case 0x10:
159 case 0x11:
160 case 0x12:
161 case 0x13:
162 gb->memory.mbc = _GBMBC3;
163 gb->memory.mbcType = GB_MBC3;
164 break;
165 default:
166 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
167 case 0x19:
168 case 0x1A:
169 case 0x1B:
170 gb->memory.mbc = _GBMBC5;
171 gb->memory.mbcType = GB_MBC5;
172 break;
173 case 0x1C:
174 case 0x1D:
175 case 0x1E:
176 gb->memory.mbc = _GBMBC5;
177 gb->memory.mbcType = GB_MBC5_RUMBLE;
178 break;
179 case 0x20:
180 gb->memory.mbc = _GBMBC6;
181 gb->memory.mbcType = GB_MBC6;
182 break;
183 case 0x22:
184 gb->memory.mbc = _GBMBC7;
185 gb->memory.mbcType = GB_MBC7;
186 memset(&gb->memory.mbcState.mbc7, 0, sizeof(gb->memory.mbcState.mbc7));
187 break;
188 }
189
190 if (!gb->memory.wram) {
191 GBMemoryDeinit(gb);
192 }
193}
194
195void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
196 bank &= 7;
197 if (!bank) {
198 bank = 1;
199 }
200 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
201 memory->wramCurrentBank = bank;
202}
203
204uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
205 struct GB* gb = (struct GB*) cpu->master;
206 struct GBMemory* memory = &gb->memory;
207 switch (address >> 12) {
208 case GB_REGION_CART_BANK0:
209 case GB_REGION_CART_BANK0 + 1:
210 case GB_REGION_CART_BANK0 + 2:
211 case GB_REGION_CART_BANK0 + 3:
212 return memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
213 case GB_REGION_CART_BANK1:
214 case GB_REGION_CART_BANK1 + 1:
215 case GB_REGION_CART_BANK1 + 2:
216 case GB_REGION_CART_BANK1 + 3:
217 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
218 case GB_REGION_VRAM:
219 case GB_REGION_VRAM + 1:
220 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
221 case GB_REGION_EXTERNAL_RAM:
222 case GB_REGION_EXTERNAL_RAM + 1:
223 if (memory->rtcAccess) {
224 return gb->memory.rtcRegs[memory->activeRtcReg];
225 } else if (memory->sramAccess) {
226 return gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
227 } else if (memory->mbcType == GB_MBC7) {
228 return _GBMBC7Read(memory, address);
229 }
230 return 0xFF;
231 case GB_REGION_WORKING_RAM_BANK0:
232 case GB_REGION_WORKING_RAM_BANK0 + 2:
233 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
234 case GB_REGION_WORKING_RAM_BANK1:
235 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
236 default:
237 if (address < GB_BASE_OAM) {
238 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
239 }
240 if (address < GB_BASE_UNUSABLE) {
241 if (gb->video.mode < 2) {
242 return gb->video.oam.raw[address & 0xFF];
243 }
244 return 0xFF;
245 }
246 if (address < GB_BASE_IO) {
247 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
248 return 0xFF;
249 }
250 if (address < GB_BASE_HRAM) {
251 return GBIORead(gb, address & (GB_SIZE_IO - 1));
252 }
253 if (address < GB_BASE_IE) {
254 return memory->hram[address & GB_SIZE_HRAM];
255 }
256 return GBIORead(gb, REG_IE);
257 }
258}
259
260void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
261 struct GB* gb = (struct GB*) cpu->master;
262 struct GBMemory* memory = &gb->memory;
263 switch (address >> 12) {
264 case GB_REGION_CART_BANK0:
265 case GB_REGION_CART_BANK0 + 1:
266 case GB_REGION_CART_BANK0 + 2:
267 case GB_REGION_CART_BANK0 + 3:
268 case GB_REGION_CART_BANK1:
269 case GB_REGION_CART_BANK1 + 1:
270 case GB_REGION_CART_BANK1 + 2:
271 case GB_REGION_CART_BANK1 + 3:
272 memory->mbc(memory, address, value);
273 cpu->memory.setActiveRegion(cpu, cpu->pc);
274 return;
275 case GB_REGION_VRAM:
276 case GB_REGION_VRAM + 1:
277 // TODO: Block access in wrong modes
278 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
279 return;
280 case GB_REGION_EXTERNAL_RAM:
281 case GB_REGION_EXTERNAL_RAM + 1:
282 if (memory->rtcAccess) {
283 gb->memory.rtcRegs[memory->activeRtcReg] = value;
284 } else if (memory->sramAccess) {
285 gb->memory.sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
286 } else if (gb->memory.mbcType == GB_MBC7) {
287 _GBMBC7Write(&gb->memory, address, value);
288 }
289 return;
290 case GB_REGION_WORKING_RAM_BANK0:
291 case GB_REGION_WORKING_RAM_BANK0 + 2:
292 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
293 return;
294 case GB_REGION_WORKING_RAM_BANK1:
295 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
296 return;
297 default:
298 if (address < GB_BASE_OAM) {
299 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
300 } else if (address < GB_BASE_UNUSABLE) {
301 if (gb->video.mode < 2) {
302 gb->video.oam.raw[address & 0xFF] = value;
303 }
304 } else if (address < GB_BASE_IO) {
305 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
306 } else if (address < GB_BASE_HRAM) {
307 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
308 } else if (address < GB_BASE_IE) {
309 memory->hram[address & GB_SIZE_HRAM] = value;
310 } else {
311 GBIOWrite(gb, REG_IE, value);
312 }
313 }
314}
315
316int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
317 int nextEvent = INT_MAX;
318 if (gb->memory.dmaRemaining) {
319 gb->memory.dmaNext -= cycles;
320 if (gb->memory.dmaNext <= 0) {
321 _GBMemoryDMAService(gb);
322 }
323 nextEvent = gb->memory.dmaNext;
324 }
325 if (gb->memory.hdmaRemaining) {
326 gb->memory.hdmaNext -= cycles;
327 if (gb->memory.hdmaNext <= 0) {
328 _GBMemoryHDMAService(gb);
329 }
330 if (gb->memory.hdmaNext < nextEvent) {
331 nextEvent = gb->memory.hdmaNext;
332 }
333 }
334 return nextEvent;
335}
336
337void GBMemoryDMA(struct GB* gb, uint16_t base) {
338 if (base > 0xF100) {
339 return;
340 }
341 gb->cpu->memory.store8 = GBDMAStore8;
342 gb->cpu->memory.load8 = GBDMALoad8;
343 gb->cpu->memory.cpuLoad8 = GBDMALoad8;
344 gb->memory.dmaNext = gb->cpu->cycles + 8;
345 if (gb->memory.dmaNext < gb->cpu->nextEvent) {
346 gb->cpu->nextEvent = gb->memory.dmaNext;
347 }
348 gb->memory.dmaSource = base;
349 gb->memory.dmaDest = 0;
350 gb->memory.dmaRemaining = 0xA0;
351}
352
353void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
354 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
355 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
356 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
357 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
358 gb->memory.hdmaSource &= 0xFFF0;
359 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
360 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
361 return;
362 }
363 gb->memory.hdmaDest &= 0x1FF0;
364 gb->memory.hdmaDest |= 0x8000;
365 bool wasHdma = gb->memory.isHdma;
366 gb->memory.isHdma = value & 0x80;
367 if (!wasHdma && !gb->memory.isHdma) {
368 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
369 gb->memory.hdmaNext = gb->cpu->cycles;
370 gb->cpu->nextEvent = gb->cpu->cycles;
371 }
372}
373
374void _GBMemoryDMAService(struct GB* gb) {
375 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
376 // TODO: Can DMA write OAM during modes 2-3?
377 gb->video.oam.raw[gb->memory.dmaDest] = b;
378 ++gb->memory.dmaSource;
379 ++gb->memory.dmaDest;
380 --gb->memory.dmaRemaining;
381 if (gb->memory.dmaRemaining) {
382 gb->memory.dmaNext += 4;
383 } else {
384 gb->memory.dmaNext = INT_MAX;
385 gb->cpu->memory.store8 = GBStore8;
386 gb->cpu->memory.load8 = GBLoad8;
387 }
388}
389
390void _GBMemoryHDMAService(struct GB* gb) {
391 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
392 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
393 ++gb->memory.hdmaSource;
394 ++gb->memory.hdmaDest;
395 --gb->memory.hdmaRemaining;
396 gb->cpu->cycles += 2;
397 if (gb->memory.hdmaRemaining) {
398 gb->memory.hdmaNext += 2;
399 } else {
400 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
401 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
402 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
403 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
404 if (gb->memory.isHdma) {
405 --gb->memory.io[REG_HDMA5];
406 if (gb->memory.io[REG_HDMA5] == 0xFF) {
407 gb->memory.isHdma = false;
408 }
409 } else {
410 gb->memory.io[REG_HDMA5] |= 0x80;
411 }
412 }
413}
414
415uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
416 struct GB* gb = (struct GB*) cpu->master;
417 struct GBMemory* memory = &gb->memory;
418 if (address < 0xFF80 || address == 0xFFFF) {
419 return 0xFF;
420 }
421 return memory->hram[address & GB_SIZE_HRAM];
422}
423
424void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
425 struct GB* gb = (struct GB*) cpu->master;
426 struct GBMemory* memory = &gb->memory;
427 if (address < 0xFF80 || address == 0xFFFF) {
428 return;
429 }
430 memory->hram[address & GB_SIZE_HRAM] = value;
431}
432
433uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
434
435void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
436
437static void _switchBank(struct GBMemory* memory, int bank) {
438 size_t bankStart = bank * GB_SIZE_CART_BANK0;
439 if (bankStart + GB_SIZE_CART_BANK0 > memory->romSize) {
440 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
441 bankStart &= (memory->romSize - 1);
442 bank = bankStart / GB_SIZE_CART_BANK0;
443 }
444 memory->romBank = &memory->rom[bankStart];
445 memory->currentBank = bank;
446}
447
448static void _switchSramBank(struct GBMemory* memory, int bank) {
449 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
450 memory->sramBank = &memory->sram[bankStart];
451 memory->sramCurrentBank = bank;
452}
453
454static void _latchRtc(struct GBMemory* memory) {
455 time_t t;
456 struct mRTCSource* rtc = memory->rtc;
457 if (rtc) {
458 if (rtc->sample) {
459 rtc->sample(rtc);
460 }
461 t = rtc->unixTime(rtc);
462 } else {
463 t = time(0);
464 }
465 struct tm date;
466 localtime_r(&t, &date);
467 memory->rtcRegs[0] = date.tm_sec;
468 memory->rtcRegs[1] = date.tm_min;
469 memory->rtcRegs[2] = date.tm_hour;
470 memory->rtcRegs[3] = date.tm_yday; // TODO: Persist day counter
471 memory->rtcRegs[4] &= 0xF0;
472 memory->rtcRegs[4] |= date.tm_yday >> 8;
473}
474
475void _GBMBC1(struct GBMemory* memory, uint16_t address, uint8_t value) {
476 int bank = value & 0x1F;
477 switch (address >> 13) {
478 case 0x0:
479 switch (value) {
480 case 0:
481 memory->sramAccess = false;
482 break;
483 case 0xA:
484 memory->sramAccess = true;
485 _switchSramBank(memory, memory->sramCurrentBank);
486 break;
487 default:
488 // TODO
489 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
490 break;
491 }
492 break;
493 case 0x1:
494 if (!bank) {
495 ++bank;
496 }
497 _switchBank(memory, bank | (memory->currentBank & 0x60));
498 break;
499 case 0x2:
500 bank &= 3;
501 if (!memory->mbcState.mbc1.mode) {
502 _switchBank(memory, (bank << 5) | (memory->currentBank & 0x1F));
503 } else {
504 _switchSramBank(memory, bank);
505 }
506 break;
507 case 0x3:
508 memory->mbcState.mbc1.mode = value & 1;
509 if (memory->mbcState.mbc1.mode) {
510 _switchBank(memory, memory->currentBank & 0x1F);
511 } else {
512 _switchSramBank(memory, 0);
513 }
514 break;
515 default:
516 // TODO
517 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
518 break;
519 }
520}
521
522void _GBMBC2(struct GBMemory* memory, uint16_t address, uint8_t value) {
523 int bank = value & 0xF;
524 switch (address >> 13) {
525 case 0x0:
526 switch (value) {
527 case 0:
528 memory->sramAccess = false;
529 break;
530 case 0xA:
531 memory->sramAccess = true;
532 _switchSramBank(memory, memory->sramCurrentBank);
533 break;
534 default:
535 // TODO
536 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
537 break;
538 }
539 break;
540 case 0x1:
541 if (!bank) {
542 ++bank;
543 }
544 _switchBank(memory, bank);
545 break;
546 default:
547 // TODO
548 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
549 break;
550 }}
551
552void _GBMBC3(struct GBMemory* memory, uint16_t address, uint8_t value) {
553 int bank = value & 0x7F;
554 switch (address >> 13) {
555 case 0x0:
556 switch (value) {
557 case 0:
558 memory->sramAccess = false;
559 break;
560 case 0xA:
561 memory->sramAccess = true;
562 _switchSramBank(memory, memory->sramCurrentBank);
563 break;
564 default:
565 // TODO
566 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
567 break;
568 }
569 break;
570 case 0x1:
571 if (!bank) {
572 ++bank;
573 }
574 _switchBank(memory, bank);
575 break;
576 case 0x2:
577 if (value < 4) {
578 _switchSramBank(memory, value);
579 memory->rtcAccess = false;
580 } else if (value >= 8 && value <= 0xC) {
581 memory->activeRtcReg = value - 8;
582 memory->rtcAccess = true;
583 }
584 break;
585 case 0x3:
586 if (memory->rtcLatched && value == 0) {
587 memory->rtcLatched = value;
588 } else if (!memory->rtcLatched && value == 1) {
589 _latchRtc(memory);
590 }
591 break;
592 }
593}
594
595void _GBMBC5(struct GBMemory* memory, uint16_t address, uint8_t value) {
596 int bank;
597 switch (address >> 12) {
598 case 0x0:
599 case 0x1:
600 switch (value) {
601 case 0:
602 memory->sramAccess = false;
603 break;
604 case 0xA:
605 memory->sramAccess = true;
606 _switchSramBank(memory, memory->sramCurrentBank);
607 break;
608 default:
609 // TODO
610 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
611 break;
612 }
613 break;
614 case 0x2:
615 bank = (memory->currentBank & 0x100) | value;
616 _switchBank(memory, bank);
617 break;
618 case 0x3:
619 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
620 _switchBank(memory, bank);
621 break;
622 case 0x4:
623 case 0x5:
624 if (memory->mbcType == GB_MBC5_RUMBLE) {
625 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
626 value &= ~8;
627 }
628 _switchSramBank(memory, value & 0xF);
629 break;
630 default:
631 // TODO
632 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
633 break;
634 }
635}
636
637void _GBMBC6(struct GBMemory* memory, uint16_t address, uint8_t value) {
638 // TODO
639 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
640}
641
642void _GBMBC7(struct GBMemory* memory, uint16_t address, uint8_t value) {
643 int bank = value & 0x7F;
644 switch (address >> 13) {
645 case 0x1:
646 _switchBank(memory, bank);
647 break;
648 case 0x2:
649 if (value < 0x10) {
650 _switchSramBank(memory, value);
651 }
652 break;
653 default:
654 // TODO
655 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
656 break;
657 }
658}
659
660uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
661 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
662 switch (address & 0xF0) {
663 case 0x00:
664 case 0x10:
665 case 0x60:
666 case 0x70:
667 return 0;
668 case 0x20:
669 if (memory->rotation && memory->rotation->readTiltX) {
670 int32_t x = -memory->rotation->readTiltX(memory->rotation);
671 x >>= 21;
672 x += 2047;
673 return x;
674 }
675 return 0xFF;
676 case 0x30:
677 if (memory->rotation && memory->rotation->readTiltX) {
678 int32_t x = -memory->rotation->readTiltX(memory->rotation);
679 x >>= 21;
680 x += 2047;
681 return x >> 8;
682 }
683 return 7;
684 case 0x40:
685 if (memory->rotation && memory->rotation->readTiltY) {
686 int32_t y = -memory->rotation->readTiltY(memory->rotation);
687 y >>= 21;
688 y += 2047;
689 return y;
690 }
691 return 0xFF;
692 case 0x50:
693 if (memory->rotation && memory->rotation->readTiltY) {
694 int32_t y = -memory->rotation->readTiltY(memory->rotation);
695 y >>= 21;
696 y += 2047;
697 return y >> 8;
698 }
699 return 7;
700 case 0x80:
701 return (mbc7->sr >> 16) & 1;
702 default:
703 return 0xFF;
704 }
705}
706
707void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
708 if ((address & 0xF0) != 0x80) {
709 return;
710 }
711 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
712 GBMBC7Field old = memory->mbcState.mbc7.field;
713 mbc7->field = GBMBC7FieldClearIO(value);
714 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
715 if (mbc7->state == GBMBC7_STATE_WRITE) {
716 if (mbc7->writable) {
717 memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
718 memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
719 }
720 mbc7->sr = 0x1FFFF;
721 mbc7->state = GBMBC7_STATE_NULL;
722 } else {
723 mbc7->state = GBMBC7_STATE_IDLE;
724 }
725 }
726 if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
727 if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
728 mbc7->sr <<= 1;
729 mbc7->sr |= GBMBC7FieldGetIO(value);
730 ++mbc7->srBits;
731 }
732 switch (mbc7->state) {
733 case GBMBC7_STATE_IDLE:
734 if (GBMBC7FieldIsIO(value)) {
735 mbc7->state = GBMBC7_STATE_READ_COMMAND;
736 mbc7->srBits = 0;
737 mbc7->sr = 0;
738 }
739 break;
740 case GBMBC7_STATE_READ_COMMAND:
741 if (mbc7->srBits == 2) {
742 mbc7->state = GBMBC7_STATE_READ_ADDRESS;
743 mbc7->srBits = 0;
744 mbc7->command = mbc7->sr;
745 }
746 break;
747 case GBMBC7_STATE_READ_ADDRESS:
748 if (mbc7->srBits == 8) {
749 mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
750 mbc7->srBits = 0;
751 mbc7->address = mbc7->sr;
752 if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
753 switch (mbc7->address >> 6) {
754 case 0:
755 mbc7->writable = false;
756 mbc7->state = GBMBC7_STATE_NULL;
757 break;
758 case 3:
759 mbc7->writable = true;
760 mbc7->state = GBMBC7_STATE_NULL;
761 break;
762 }
763 }
764 }
765 break;
766 case GBMBC7_STATE_COMMAND_0:
767 if (mbc7->srBits == 16) {
768 switch (mbc7->address >> 6) {
769 case 0:
770 mbc7->writable = false;
771 mbc7->state = GBMBC7_STATE_NULL;
772 break;
773 case 1:
774 mbc7->state = GBMBC7_STATE_WRITE;
775 if (mbc7->writable) {
776 int i;
777 for (i = 0; i < 256; ++i) {
778 memory->sramBank[i * 2] = mbc7->sr >> 8;
779 memory->sramBank[i * 2 + 1] = mbc7->sr;
780 }
781 }
782 break;
783 case 2:
784 mbc7->state = GBMBC7_STATE_WRITE;
785 if (mbc7->writable) {
786 int i;
787 for (i = 0; i < 256; ++i) {
788 memory->sramBank[i * 2] = 0xFF;
789 memory->sramBank[i * 2 + 1] = 0xFF;
790 }
791 }
792 break;
793 case 3:
794 mbc7->writable = true;
795 mbc7->state = GBMBC7_STATE_NULL;
796 break;
797 }
798 }
799 break;
800 case GBMBC7_STATE_COMMAND_SR_WRITE:
801 if (mbc7->srBits == 16) {
802 mbc7->srBits = 0;
803 mbc7->state = GBMBC7_STATE_WRITE;
804 }
805 break;
806 case GBMBC7_STATE_COMMAND_SR_READ:
807 if (mbc7->srBits == 1) {
808 mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
809 mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
810 mbc7->srBits = 0;
811 mbc7->state = GBMBC7_STATE_READ;
812 }
813 break;
814 case GBMBC7_STATE_COMMAND_SR_FILL:
815 if (mbc7->srBits == 16) {
816 mbc7->sr = 0xFFFF;
817 mbc7->srBits = 0;
818 mbc7->state = GBMBC7_STATE_WRITE;
819 }
820 break;
821 default:
822 break;
823 }
824 } else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
825 if (mbc7->state == GBMBC7_STATE_READ) {
826 mbc7->sr <<= 1;
827 ++mbc7->srBits;
828 if (mbc7->srBits == 16) {
829 mbc7->srBits = 0;
830 mbc7->state = GBMBC7_STATE_NULL;
831 }
832 }
833 }
834}