src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
35
36void GBMBCSwitchBank(struct GB* gb, int bank) {
37 size_t bankStart = bank * GB_SIZE_CART_BANK0;
38 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
39 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
40 bankStart &= (gb->memory.romSize - 1);
41 bank = bankStart / GB_SIZE_CART_BANK0;
42 if (!bank) {
43 ++bank;
44 }
45 }
46 gb->memory.romBank = &gb->memory.rom[bankStart];
47 gb->memory.currentBank = bank;
48 if (gb->cpu->pc < GB_BASE_VRAM) {
49 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
50 }
51}
52
53void GBMBCSwitchBank0(struct GB* gb, int bank) {
54 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
55 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
56 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
57 bankStart &= (gb->memory.romSize - 1);
58 }
59 gb->memory.romBase = &gb->memory.rom[bankStart];
60 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
61 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
62 }
63}
64
65static bool _isMulticart(const uint8_t* mem) {
66 bool success = true;
67 struct VFile* vf;
68
69 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
70 success = success && GBIsROM(vf);
71 vf->close(vf);
72
73 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
74 success = success && GBIsROM(vf);
75 vf->close(vf);
76
77 return success;
78}
79
80void GBMBCSwitchSramBank(struct GB* gb, int bank) {
81 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
82 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
83 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
84 bankStart &= (gb->sramSize - 1);
85 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
86 }
87 gb->memory.sramBank = &gb->memory.sram[bankStart];
88 gb->memory.sramCurrentBank = bank;
89}
90
91void GBMBCInit(struct GB* gb) {
92 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
93 if (gb->memory.rom) {
94 switch (cart->ramSize) {
95 case 0:
96 gb->sramSize = 0;
97 break;
98 case 1:
99 gb->sramSize = 0x800;
100 break;
101 default:
102 case 2:
103 gb->sramSize = 0x2000;
104 break;
105 case 3:
106 gb->sramSize = 0x8000;
107 break;
108 case 4:
109 gb->sramSize = 0x20000;
110 break;
111 case 5:
112 gb->sramSize = 0x10000;
113 break;
114 }
115
116 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
117 switch (cart->type) {
118 case 0:
119 case 8:
120 case 9:
121 gb->memory.mbcType = GB_MBC_NONE;
122 break;
123 case 1:
124 case 2:
125 case 3:
126 gb->memory.mbcType = GB_MBC1;
127 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
128 gb->memory.mbcState.mbc1.multicartStride = 4;
129 } else {
130 gb->memory.mbcState.mbc1.multicartStride = 5;
131 }
132 break;
133 case 5:
134 case 6:
135 gb->memory.mbcType = GB_MBC2;
136 break;
137 case 0x0F:
138 case 0x10:
139 gb->memory.mbcType = GB_MBC3_RTC;
140 break;
141 case 0x11:
142 case 0x12:
143 case 0x13:
144 gb->memory.mbcType = GB_MBC3;
145 break;
146 default:
147 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
148 // Fall through
149 case 0x19:
150 case 0x1A:
151 case 0x1B:
152 gb->memory.mbcType = GB_MBC5;
153 break;
154 case 0x1C:
155 case 0x1D:
156 case 0x1E:
157 gb->memory.mbcType = GB_MBC5_RUMBLE;
158 break;
159 case 0x20:
160 gb->memory.mbcType = GB_MBC6;
161 break;
162 case 0x22:
163 gb->memory.mbcType = GB_MBC7;
164 break;
165 case 0xFC:
166 gb->memory.mbcType = GB_POCKETCAM;
167 break;
168 case 0xFD:
169 gb->memory.mbcType = GB_HuC1;
170 break;
171 case 0xFE:
172 gb->memory.mbcType = GB_HuC3;
173 break;
174 }
175 }
176 } else {
177 gb->memory.mbcType = GB_MBC_NONE;
178 }
179 gb->memory.mbcRead = NULL;
180 switch (gb->memory.mbcType) {
181 case GB_MBC_NONE:
182 gb->memory.mbcWrite = _GBMBCNone;
183 break;
184 case GB_MBC1:
185 gb->memory.mbcWrite = _GBMBC1;
186 break;
187 case GB_MBC2:
188 gb->memory.mbcWrite = _GBMBC2;
189 gb->sramSize = 0x200;
190 break;
191 case GB_MBC3:
192 gb->memory.mbcWrite = _GBMBC3;
193 break;
194 default:
195 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
196 // Fall through
197 case GB_MBC5:
198 gb->memory.mbcWrite = _GBMBC5;
199 break;
200 case GB_MBC6:
201 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
202 gb->memory.mbcWrite = _GBMBC6;
203 break;
204 case GB_MBC7:
205 gb->memory.mbcWrite = _GBMBC7;
206 gb->memory.mbcRead = _GBMBC7Read;
207 gb->sramSize = 0x100;
208 break;
209 case GB_MMM01:
210 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
211 gb->memory.mbcWrite = _GBMBC1;
212 break;
213 case GB_HuC1:
214 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
215 gb->memory.mbcWrite = _GBMBC1;
216 break;
217 case GB_HuC3:
218 gb->memory.mbcWrite = _GBHuC3;
219 break;
220 case GB_MBC3_RTC:
221 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
222 gb->memory.mbcWrite = _GBMBC3;
223 break;
224 case GB_MBC5_RUMBLE:
225 gb->memory.mbcWrite = _GBMBC5;
226 break;
227 case GB_POCKETCAM:
228 gb->memory.mbcWrite = _GBPocketCam;
229 gb->memory.mbcRead = _GBPocketCamRead;
230 break;
231 }
232
233 gb->memory.currentBank = 1;
234 gb->memory.sramCurrentBank = 0;
235 gb->memory.sramAccess = false;
236 gb->memory.rtcAccess = false;
237 gb->memory.activeRtcReg = 0;
238 gb->memory.rtcLatched = false;
239 gb->memory.rtcLastLatch = 0;
240 if (gb->memory.rtc) {
241 if (gb->memory.rtc->sample) {
242 gb->memory.rtc->sample(gb->memory.rtc);
243 }
244 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
245 } else {
246 gb->memory.rtcLastLatch = time(0);
247 }
248 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
249
250 GBResizeSram(gb, gb->sramSize);
251
252 if (gb->memory.mbcType == GB_MBC3_RTC) {
253 GBMBCRTCRead(gb);
254 }
255}
256
257static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
258 time_t t;
259 if (rtc) {
260 if (rtc->sample) {
261 rtc->sample(rtc);
262 }
263 t = rtc->unixTime(rtc);
264 } else {
265 t = time(0);
266 }
267 time_t currentLatch = t;
268 t -= *rtcLastLatch;
269 *rtcLastLatch = currentLatch;
270
271 int64_t diff;
272 diff = rtcRegs[0] + t % 60;
273 if (diff < 0) {
274 diff += 60;
275 t -= 60;
276 }
277 rtcRegs[0] = diff % 60;
278 t /= 60;
279 t += diff / 60;
280
281 diff = rtcRegs[1] + t % 60;
282 if (diff < 0) {
283 diff += 60;
284 t -= 60;
285 }
286 rtcRegs[1] = diff % 60;
287 t /= 60;
288 t += diff / 60;
289
290 diff = rtcRegs[2] + t % 24;
291 if (diff < 0) {
292 diff += 24;
293 t -= 24;
294 }
295 rtcRegs[2] = diff % 24;
296 t /= 24;
297 t += diff / 24;
298
299 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
300 rtcRegs[3] = diff;
301 rtcRegs[4] &= 0xFE;
302 rtcRegs[4] |= (diff >> 8) & 1;
303 if (diff & 0x200) {
304 rtcRegs[4] |= 0x80;
305 }
306}
307
308void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
309 struct GBMemory* memory = &gb->memory;
310 int bank = value & 0x1F;
311 int stride = 1 << memory->mbcState.mbc1.multicartStride;
312 switch (address >> 13) {
313 case 0x0:
314 switch (value) {
315 case 0:
316 memory->sramAccess = false;
317 break;
318 case 0xA:
319 memory->sramAccess = true;
320 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
321 break;
322 default:
323 // TODO
324 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
325 break;
326 }
327 break;
328 case 0x1:
329 if (!bank) {
330 ++bank;
331 }
332 bank &= stride - 1;
333 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
334 break;
335 case 0x2:
336 bank &= 3;
337 if (memory->mbcState.mbc1.mode) {
338 GBMBCSwitchBank0(gb, bank);
339 GBMBCSwitchSramBank(gb, bank);
340 }
341 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
342 break;
343 case 0x3:
344 memory->mbcState.mbc1.mode = value & 1;
345 if (memory->mbcState.mbc1.mode) {
346 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
347 } else {
348 GBMBCSwitchBank0(gb, 0);
349 GBMBCSwitchSramBank(gb, 0);
350 }
351 break;
352 default:
353 // TODO
354 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
355 break;
356 }
357}
358
359void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
360 struct GBMemory* memory = &gb->memory;
361 int bank = value & 0xF;
362 switch (address >> 13) {
363 case 0x0:
364 switch (value) {
365 case 0:
366 memory->sramAccess = false;
367 break;
368 case 0xA:
369 memory->sramAccess = true;
370 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
371 break;
372 default:
373 // TODO
374 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
375 break;
376 }
377 break;
378 case 0x1:
379 if (!bank) {
380 ++bank;
381 }
382 GBMBCSwitchBank(gb, bank);
383 break;
384 default:
385 // TODO
386 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
387 break;
388 }
389}
390
391void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
392 struct GBMemory* memory = &gb->memory;
393 int bank = value & 0x7F;
394 switch (address >> 13) {
395 case 0x0:
396 switch (value) {
397 case 0:
398 memory->sramAccess = false;
399 break;
400 case 0xA:
401 memory->sramAccess = true;
402 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
403 break;
404 default:
405 // TODO
406 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
407 break;
408 }
409 break;
410 case 0x1:
411 if (!bank) {
412 ++bank;
413 }
414 GBMBCSwitchBank(gb, bank);
415 break;
416 case 0x2:
417 if (value < 4) {
418 GBMBCSwitchSramBank(gb, value);
419 memory->rtcAccess = false;
420 } else if (value >= 8 && value <= 0xC) {
421 memory->activeRtcReg = value - 8;
422 memory->rtcAccess = true;
423 }
424 break;
425 case 0x3:
426 if (memory->rtcLatched && value == 0) {
427 memory->rtcLatched = false;
428 } else if (!memory->rtcLatched && value == 1) {
429 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
430 memory->rtcLatched = true;
431 }
432 break;
433 }
434}
435
436void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
437 struct GBMemory* memory = &gb->memory;
438 int bank;
439 switch (address >> 12) {
440 case 0x0:
441 case 0x1:
442 switch (value) {
443 case 0:
444 memory->sramAccess = false;
445 break;
446 case 0xA:
447 memory->sramAccess = true;
448 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
449 break;
450 default:
451 // TODO
452 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
453 break;
454 }
455 break;
456 case 0x2:
457 bank = (memory->currentBank & 0x100) | value;
458 GBMBCSwitchBank(gb, bank);
459 break;
460 case 0x3:
461 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
462 GBMBCSwitchBank(gb, bank);
463 break;
464 case 0x4:
465 case 0x5:
466 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
467 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
468 value &= ~8;
469 }
470 GBMBCSwitchSramBank(gb, value & 0xF);
471 break;
472 default:
473 // TODO
474 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
475 break;
476 }
477}
478
479void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
480 // TODO
481 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
482 UNUSED(gb);
483 UNUSED(address);
484 UNUSED(value);
485}
486
487void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
488 int bank = value & 0x7F;
489 switch (address >> 13) {
490 case 0x0:
491 switch (value) {
492 default:
493 case 0:
494 gb->memory.mbcState.mbc7.access = 0;
495 break;
496 case 0xA:
497 gb->memory.mbcState.mbc7.access |= 1;
498 break;
499 }
500 break;
501 case 0x1:
502 GBMBCSwitchBank(gb, bank);
503 break;
504 case 0x2:
505 if (value == 0x40) {
506 gb->memory.mbcState.mbc7.access |= 2;
507 } else {
508 gb->memory.mbcState.mbc7.access &= ~2;
509 }
510 break;
511 default:
512 // TODO
513 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
514 break;
515 }
516}
517
518uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
519 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
520 if (mbc7->access != 3) {
521 return 0xFF;
522 }
523 switch (address & 0xF0) {
524 case 0x20:
525 if (memory->rotation && memory->rotation->readTiltX) {
526 int32_t x = -memory->rotation->readTiltX(memory->rotation);
527 x >>= 21;
528 x += 0x81D0;
529 return x;
530 }
531 return 0xFF;
532 case 0x30:
533 if (memory->rotation && memory->rotation->readTiltX) {
534 int32_t x = -memory->rotation->readTiltX(memory->rotation);
535 x >>= 21;
536 x += 0x81D0;
537 return x >> 8;
538 }
539 return 7;
540 case 0x40:
541 if (memory->rotation && memory->rotation->readTiltY) {
542 int32_t y = -memory->rotation->readTiltY(memory->rotation);
543 y >>= 21;
544 y += 0x81D0;
545 return y;
546 }
547 return 0xFF;
548 case 0x50:
549 if (memory->rotation && memory->rotation->readTiltY) {
550 int32_t y = -memory->rotation->readTiltY(memory->rotation);
551 y >>= 21;
552 y += 0x81D0;
553 return y >> 8;
554 }
555 return 7;
556 case 0x60:
557 return 0;
558 case 0x80:
559 return mbc7->eeprom;
560 default:
561 return 0xFF;
562 }
563}
564
565void GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
566 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
567 if (mbc7->access != 3) {
568 return;
569 }
570 switch (address & 0xF0) {
571 case 0x00:
572 mbc7->latch = (value & 0x55) == 0x55;
573 return;
574 case 0x10:
575 mbc7->latch |= (value & 0xAA);
576 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
577 memory->rotation->sample(memory->rotation);
578 }
579 mbc7->latch = 0;
580 return;
581 default:
582 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
583 return;
584 case 0x80:
585 break;
586 }
587 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
588 value = GBMBC7FieldFillDO(value); // Hi-Z
589 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
590 mbc7->state = GBMBC7_STATE_IDLE;
591 }
592 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
593 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
594 mbc7->sr <<= 1;
595 mbc7->sr |= GBMBC7FieldGetDI(value);
596 ++mbc7->srBits;
597 }
598 switch (mbc7->state) {
599 case GBMBC7_STATE_IDLE:
600 if (GBMBC7FieldIsDI(value)) {
601 mbc7->state = GBMBC7_STATE_READ_COMMAND;
602 mbc7->srBits = 0;
603 mbc7->sr = 0;
604 }
605 break;
606 case GBMBC7_STATE_READ_COMMAND:
607 if (mbc7->srBits == 10) {
608 mbc7->state = 0x10 | (mbc7->sr >> 6);
609 if (mbc7->state & 0xC) {
610 mbc7->state &= ~0x3;
611 }
612 mbc7->srBits = 0;
613 mbc7->address = mbc7->sr & 0x7F;
614 }
615 break;
616 case GBMBC7_STATE_DO:
617 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
618 mbc7->sr <<= 1;
619 --mbc7->srBits;
620 if (!mbc7->srBits) {
621 mbc7->state = GBMBC7_STATE_IDLE;
622 }
623 break;
624 default:
625 break;
626 }
627 switch (mbc7->state) {
628 case GBMBC7_STATE_EEPROM_EWEN:
629 mbc7->writable = true;
630 mbc7->state = GBMBC7_STATE_IDLE;
631 break;
632 case GBMBC7_STATE_EEPROM_EWDS:
633 mbc7->writable = false;
634 mbc7->state = GBMBC7_STATE_IDLE;
635 break;
636 case GBMBC7_STATE_EEPROM_WRITE:
637 if (mbc7->srBits == 16) {
638 if (mbc7->writable) {
639 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
640 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
641 }
642 mbc7->state = GBMBC7_STATE_IDLE;
643 }
644 break;
645 case GBMBC7_STATE_EEPROM_ERASE:
646 if (mbc7->writable) {
647 memory->sram[mbc7->address * 2] = 0xFF;
648 memory->sram[mbc7->address * 2 + 1] = 0xFF;
649 }
650 mbc7->state = GBMBC7_STATE_IDLE;
651 break;
652 case GBMBC7_STATE_EEPROM_READ:
653 mbc7->srBits = 16;
654 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
655 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
656 mbc7->state = GBMBC7_STATE_DO;
657 value = GBMBC7FieldClearDO(value);
658 break;
659 case GBMBC7_STATE_EEPROM_WRAL:
660 if (mbc7->srBits == 16) {
661 if (mbc7->writable) {
662 int i;
663 for (i = 0; i < 128; ++i) {
664 memory->sram[i * 2] = mbc7->sr >> 8;
665 memory->sram[i * 2 + 1] = mbc7->sr;
666 }
667 }
668 mbc7->state = GBMBC7_STATE_IDLE;
669 }
670 break;
671 case GBMBC7_STATE_EEPROM_ERAL:
672 if (mbc7->writable) {
673 int i;
674 for (i = 0; i < 128; ++i) {
675 memory->sram[i * 2] = 0xFF;
676 memory->sram[i * 2 + 1] = 0xFF;
677 }
678 }
679 mbc7->state = GBMBC7_STATE_IDLE;
680 break;
681 default:
682 break;
683 }
684 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
685 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
686 }
687 mbc7->eeprom = value;
688}
689
690void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
691 struct GBMemory* memory = &gb->memory;
692 int bank = value & 0x3F;
693 if (address & 0x1FFF) {
694 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
695 }
696
697 switch (address >> 13) {
698 case 0x0:
699 switch (value) {
700 case 0xA:
701 memory->sramAccess = true;
702 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
703 break;
704 default:
705 memory->sramAccess = false;
706 break;
707 }
708 break;
709 case 0x1:
710 GBMBCSwitchBank(gb, bank);
711 break;
712 case 0x2:
713 GBMBCSwitchSramBank(gb, bank);
714 break;
715 default:
716 // TODO
717 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
718 break;
719 }
720}
721
722void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
723 struct GBMemory* memory = &gb->memory;
724 int bank = value & 0x3F;
725 switch (address >> 13) {
726 case 0x0:
727 switch (value) {
728 case 0:
729 memory->sramAccess = false;
730 break;
731 case 0xA:
732 memory->sramAccess = true;
733 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
734 break;
735 default:
736 // TODO
737 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
738 break;
739 }
740 break;
741 case 0x1:
742 GBMBCSwitchBank(gb, bank);
743 break;
744 case 0x2:
745 if (value < 0x10) {
746 GBMBCSwitchSramBank(gb, value);
747 memory->mbcState.pocketCam.registersActive = false;
748 } else {
749 memory->mbcState.pocketCam.registersActive = true;
750 }
751 break;
752 default:
753 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
754 break;
755 }
756}
757
758uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
759 if (memory->mbcState.pocketCam.registersActive) {
760 return 0;
761 }
762 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
763}
764
765void GBMBCRTCRead(struct GB* gb) {
766 struct GBMBCRTCSaveBuffer rtcBuffer;
767 struct VFile* vf = gb->sramVf;
768 if (!vf) {
769 return;
770 }
771 vf->seek(vf, gb->sramSize, SEEK_SET);
772 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
773 return;
774 }
775
776 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
777 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
778 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
779 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
780 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
781 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
782}
783
784void GBMBCRTCWrite(struct GB* gb) {
785 struct VFile* vf = gb->sramVf;
786 if (!vf) {
787 return;
788 }
789
790 uint8_t rtcRegs[5];
791 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
792 time_t rtcLastLatch = gb->memory.rtcLastLatch;
793 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
794
795 struct GBMBCRTCSaveBuffer rtcBuffer;
796 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
797 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
798 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
799 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
800 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
801 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
802 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
803 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
804 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
805 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
806 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
807
808 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
809 // Writing past the end of the file can invalidate the file mapping
810 vf->unmap(vf, gb->memory.sram, gb->sramSize);
811 gb->memory.sram = NULL;
812 }
813 vf->seek(vf, gb->sramSize, SEEK_SET);
814 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
815 if (!gb->memory.sram) {
816 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
817 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
818 }
819}